1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Copyright (C) 2022 Helge Deller <deller@gmx.de>
7 * Significantly tweaked by LaMont Jones <lamont@debian.org>
8 */
9
10 #include <linux/sched/signal.h>
11 #include <linux/signal.h>
12 #include <linux/ratelimit.h>
13 #include <linux/uaccess.h>
14 #include <linux/sysctl.h>
15 #include <linux/unaligned.h>
16 #include <asm/hardirq.h>
17 #include <asm/traps.h>
18 #include "unaligned.h"
19
20 /* #define DEBUG_UNALIGNED 1 */
21
22 #ifdef DEBUG_UNALIGNED
23 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
24 #else
25 #define DPRINTF(fmt, args...)
26 #endif
27
28 #define RFMT "%#08lx"
29
30 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
31 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
32 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
33 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
34 #define OPCODE4(a) ((a)<<26)
35 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
36 #define OPCODE2_MASK OPCODE2(0x3f,1)
37 #define OPCODE3_MASK OPCODE3(0x3f,1)
38 #define OPCODE4_MASK OPCODE4(0x3f)
39
40 /* skip LDB - never unaligned (index) */
41 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
42 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
43 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
44 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
45 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
46 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
47 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
48 /* skip LDB - never unaligned (short) */
49 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
50 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
51 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
52 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
53 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
54 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
55 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
56 /* skip STB - never unaligned */
57 #define OPCODE_STH OPCODE1(0x03,1,0x9)
58 #define OPCODE_STW OPCODE1(0x03,1,0xa)
59 #define OPCODE_STD OPCODE1(0x03,1,0xb)
60 /* skip STBY - never unaligned */
61 /* skip STDBY - never unaligned */
62 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
63 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
64
65 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
66 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
67 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
68 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
69 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
70 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
71 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
72 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
73 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
74 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
75 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
76 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
77
78 #define OPCODE_LDD_L OPCODE2(0x14,0)
79 #define OPCODE_FLDD_L OPCODE2(0x14,1)
80 #define OPCODE_STD_L OPCODE2(0x1c,0)
81 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
82
83 #define OPCODE_LDW_M OPCODE3(0x17,1)
84 #define OPCODE_FLDW_L OPCODE3(0x17,0)
85 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
86 #define OPCODE_STW_M OPCODE3(0x1f,1)
87
88 #define OPCODE_LDH_L OPCODE4(0x11)
89 #define OPCODE_LDW_L OPCODE4(0x12)
90 #define OPCODE_LDWM OPCODE4(0x13)
91 #define OPCODE_STH_L OPCODE4(0x19)
92 #define OPCODE_STW_L OPCODE4(0x1A)
93 #define OPCODE_STWM OPCODE4(0x1B)
94
95 #define MAJOR_OP(i) (((i)>>26)&0x3f)
96 #define R1(i) (((i)>>21)&0x1f)
97 #define R2(i) (((i)>>16)&0x1f)
98 #define R3(i) ((i)&0x1f)
99 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
100 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
101 #define IM5_2(i) IM((i)>>16,5)
102 #define IM5_3(i) IM((i),5)
103 #define IM14(i) IM((i),14)
104
105 #define ERR_NOTHANDLED -1
106
107 int unaligned_enabled __read_mostly = 1;
108 int no_unaligned_warning __read_mostly;
109
emulate_ldh(struct pt_regs * regs,int toreg)110 static int emulate_ldh(struct pt_regs *regs, int toreg)
111 {
112 unsigned long saddr = regs->ior;
113 unsigned long val = 0, temp1;
114 ASM_EXCEPTIONTABLE_VAR(ret);
115
116 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
117 regs->isr, regs->ior, toreg);
118
119 __asm__ __volatile__ (
120 " mtsp %4, %%sr1\n"
121 "1: ldbs 0(%%sr1,%3), %2\n"
122 "2: ldbs 1(%%sr1,%3), %0\n"
123 " depw %2, 23, 24, %0\n"
124 "3: \n"
125 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
126 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
127 : "+r" (val), "+r" (ret), "=&r" (temp1)
128 : "r" (saddr), "r" (regs->isr) );
129
130 DPRINTF("val = " RFMT "\n", val);
131
132 if (toreg)
133 regs->gr[toreg] = val;
134
135 return ret;
136 }
137
emulate_ldw(struct pt_regs * regs,int toreg,int flop)138 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
139 {
140 unsigned long saddr = regs->ior;
141 unsigned long val = 0, temp1, temp2;
142 ASM_EXCEPTIONTABLE_VAR(ret);
143
144 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
145 regs->isr, regs->ior, toreg);
146
147 __asm__ __volatile__ (
148 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
149 " mtsp %5, %%sr1\n"
150 " depw %%r0,31,2,%4\n"
151 "1: ldw 0(%%sr1,%4),%0\n"
152 "2: ldw 4(%%sr1,%4),%3\n"
153 " subi 32,%2,%2\n"
154 " mtctl %2,11\n"
155 " vshd %0,%3,%0\n"
156 "3: \n"
157 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
158 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
159 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
160 : "r" (saddr), "r" (regs->isr) );
161
162 DPRINTF("val = " RFMT "\n", val);
163
164 if (flop)
165 ((__u32*)(regs->fr))[toreg] = val;
166 else if (toreg)
167 regs->gr[toreg] = val;
168
169 return ret;
170 }
emulate_ldd(struct pt_regs * regs,int toreg,int flop)171 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
172 {
173 unsigned long saddr = regs->ior;
174 unsigned long shift, temp1;
175 __u64 val = 0;
176 ASM_EXCEPTIONTABLE_VAR(ret);
177
178 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
179 regs->isr, regs->ior, toreg);
180
181 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
182 return ERR_NOTHANDLED;
183
184 #ifdef CONFIG_64BIT
185 __asm__ __volatile__ (
186 " depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */
187 " mtsp %5, %%sr1\n"
188 " depd %%r0,63,3,%2\n"
189 "1: ldd 0(%%sr1,%2),%0\n"
190 "2: ldd 8(%%sr1,%2),%4\n"
191 " subi 64,%3,%3\n"
192 " mtsar %3\n"
193 " shrpd %0,%4,%%sar,%0\n"
194 "3: \n"
195 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
196 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
197 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
198 : "r" (regs->isr) );
199 #else
200 __asm__ __volatile__ (
201 " zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */
202 " mtsp %5, %%sr1\n"
203 " dep %%r0,31,2,%2\n"
204 "1: ldw 0(%%sr1,%2),%0\n"
205 "2: ldw 4(%%sr1,%2),%R0\n"
206 "3: ldw 8(%%sr1,%2),%4\n"
207 " subi 32,%3,%3\n"
208 " mtsar %3\n"
209 " vshd %0,%R0,%0\n"
210 " vshd %R0,%4,%R0\n"
211 "4: \n"
212 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
213 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
214 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
215 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
216 : "r" (regs->isr) );
217 #endif
218
219 DPRINTF("val = 0x%llx\n", val);
220
221 if (flop)
222 regs->fr[toreg] = val;
223 else if (toreg)
224 regs->gr[toreg] = val;
225
226 return ret;
227 }
228
emulate_sth(struct pt_regs * regs,int frreg)229 static int emulate_sth(struct pt_regs *regs, int frreg)
230 {
231 unsigned long val = regs->gr[frreg], temp1;
232 ASM_EXCEPTIONTABLE_VAR(ret);
233
234 if (!frreg)
235 val = 0;
236
237 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
238 val, regs->isr, regs->ior);
239
240 __asm__ __volatile__ (
241 " mtsp %4, %%sr1\n"
242 " extrw,u %2, 23, 8, %1\n"
243 "1: stb %1, 0(%%sr1, %3)\n"
244 "2: stb %2, 1(%%sr1, %3)\n"
245 "3: \n"
246 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
247 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
248 : "+r" (ret), "=&r" (temp1)
249 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
250
251 return ret;
252 }
253
emulate_stw(struct pt_regs * regs,int frreg,int flop)254 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
255 {
256 unsigned long val;
257 ASM_EXCEPTIONTABLE_VAR(ret);
258
259 if (flop)
260 val = ((__u32*)(regs->fr))[frreg];
261 else if (frreg)
262 val = regs->gr[frreg];
263 else
264 val = 0;
265
266 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
267 val, regs->isr, regs->ior);
268
269
270 __asm__ __volatile__ (
271 " mtsp %3, %%sr1\n"
272 " zdep %2, 28, 2, %%r19\n"
273 " dep %%r0, 31, 2, %2\n"
274 " mtsar %%r19\n"
275 " depwi,z -2, %%sar, 32, %%r19\n"
276 "1: ldw 0(%%sr1,%2),%%r20\n"
277 "2: ldw 4(%%sr1,%2),%%r21\n"
278 " vshd %%r0, %1, %%r22\n"
279 " vshd %1, %%r0, %%r1\n"
280 " and %%r20, %%r19, %%r20\n"
281 " andcm %%r21, %%r19, %%r21\n"
282 " or %%r22, %%r20, %%r20\n"
283 " or %%r1, %%r21, %%r21\n"
284 " stw %%r20,0(%%sr1,%2)\n"
285 " stw %%r21,4(%%sr1,%2)\n"
286 "3: \n"
287 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
288 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
289 : "+r" (ret)
290 : "r" (val), "r" (regs->ior), "r" (regs->isr)
291 : "r19", "r20", "r21", "r22", "r1" );
292
293 return ret;
294 }
emulate_std(struct pt_regs * regs,int frreg,int flop)295 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
296 {
297 __u64 val;
298 ASM_EXCEPTIONTABLE_VAR(ret);
299
300 if (flop)
301 val = regs->fr[frreg];
302 else if (frreg)
303 val = regs->gr[frreg];
304 else
305 val = 0;
306
307 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
308 val, regs->isr, regs->ior);
309
310 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
311 return ERR_NOTHANDLED;
312
313 #ifdef CONFIG_64BIT
314 __asm__ __volatile__ (
315 " mtsp %3, %%sr1\n"
316 " depd,z %2, 60, 3, %%r19\n"
317 " depd %%r0, 63, 3, %2\n"
318 " mtsar %%r19\n"
319 " depdi,z -2, %%sar, 64, %%r19\n"
320 "1: ldd 0(%%sr1,%2),%%r20\n"
321 "2: ldd 8(%%sr1,%2),%%r21\n"
322 " shrpd %%r0, %1, %%sar, %%r22\n"
323 " shrpd %1, %%r0, %%sar, %%r1\n"
324 " and %%r20, %%r19, %%r20\n"
325 " andcm %%r21, %%r19, %%r21\n"
326 " or %%r22, %%r20, %%r20\n"
327 " or %%r1, %%r21, %%r21\n"
328 "3: std %%r20,0(%%sr1,%2)\n"
329 "4: std %%r21,8(%%sr1,%2)\n"
330 "5: \n"
331 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
334 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
335 : "+r" (ret)
336 : "r" (val), "r" (regs->ior), "r" (regs->isr)
337 : "r19", "r20", "r21", "r22", "r1" );
338 #else
339 {
340 __asm__ __volatile__ (
341 " mtsp %3, %%sr1\n"
342 " zdep %R1, 29, 2, %%r19\n"
343 " dep %%r0, 31, 2, %2\n"
344 " mtsar %%r19\n"
345 " zvdepi -2, 32, %%r19\n"
346 "1: ldw 0(%%sr1,%2),%%r20\n"
347 "2: ldw 8(%%sr1,%2),%%r21\n"
348 " vshd %1, %R1, %%r1\n"
349 " vshd %%r0, %1, %1\n"
350 " vshd %R1, %%r0, %R1\n"
351 " and %%r20, %%r19, %%r20\n"
352 " andcm %%r21, %%r19, %%r21\n"
353 " or %1, %%r20, %1\n"
354 " or %R1, %%r21, %R1\n"
355 "3: stw %1,0(%%sr1,%2)\n"
356 "4: stw %%r1,4(%%sr1,%2)\n"
357 "5: stw %R1,8(%%sr1,%2)\n"
358 "6: \n"
359 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
362 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
363 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
364 : "+r" (ret)
365 : "r" (val), "r" (regs->ior), "r" (regs->isr)
366 : "r19", "r20", "r21", "r1" );
367 }
368 #endif
369
370 return ret;
371 }
372
handle_unaligned(struct pt_regs * regs)373 void handle_unaligned(struct pt_regs *regs)
374 {
375 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
376 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
377 int modify = 0;
378 int ret = ERR_NOTHANDLED;
379
380 __inc_irq_stat(irq_unaligned_count);
381
382 /* log a message with pacing */
383 if (user_mode(regs)) {
384 if (current->thread.flags & PARISC_UAC_SIGBUS) {
385 goto force_sigbus;
386 }
387
388 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
389 __ratelimit(&ratelimit)) {
390 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
391 " at ip " RFMT " (iir " RFMT ")\n",
392 current->comm, task_pid_nr(current), regs->ior,
393 regs->iaoq[0], regs->iir);
394 #ifdef DEBUG_UNALIGNED
395 show_regs(regs);
396 #endif
397 }
398
399 if (!unaligned_enabled)
400 goto force_sigbus;
401 } else {
402 static DEFINE_RATELIMIT_STATE(kernel_ratelimit, 5 * HZ, 5);
403 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
404 !no_unaligned_warning &&
405 __ratelimit(&kernel_ratelimit))
406 pr_warn("Kernel: unaligned access to " RFMT " in %pS "
407 "(iir " RFMT ")\n",
408 regs->ior, (void *)regs->iaoq[0], regs->iir);
409 }
410
411 /* handle modification - OK, it's ugly, see the instruction manual */
412 switch (MAJOR_OP(regs->iir))
413 {
414 case 0x03:
415 case 0x09:
416 case 0x0b:
417 if (regs->iir&0x20)
418 {
419 modify = 1;
420 if (regs->iir&0x1000) /* short loads */
421 if (regs->iir&0x200)
422 newbase += IM5_3(regs->iir);
423 else
424 newbase += IM5_2(regs->iir);
425 else if (regs->iir&0x2000) /* scaled indexed */
426 {
427 int shift=0;
428 switch (regs->iir & OPCODE1_MASK)
429 {
430 case OPCODE_LDH_I:
431 shift= 1; break;
432 case OPCODE_LDW_I:
433 shift= 2; break;
434 case OPCODE_LDD_I:
435 case OPCODE_LDDA_I:
436 shift= 3; break;
437 }
438 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
439 } else /* simple indexed */
440 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
441 }
442 break;
443 case 0x13:
444 case 0x1b:
445 modify = 1;
446 newbase += IM14(regs->iir);
447 break;
448 case 0x14:
449 case 0x1c:
450 if (regs->iir&8)
451 {
452 modify = 1;
453 newbase += IM14(regs->iir&~0xe);
454 }
455 break;
456 case 0x16:
457 case 0x1e:
458 modify = 1;
459 newbase += IM14(regs->iir&6);
460 break;
461 case 0x17:
462 case 0x1f:
463 if (regs->iir&4)
464 {
465 modify = 1;
466 newbase += IM14(regs->iir&~4);
467 }
468 break;
469 }
470
471 /* TODO: make this cleaner... */
472 switch (regs->iir & OPCODE1_MASK)
473 {
474 case OPCODE_LDH_I:
475 case OPCODE_LDH_S:
476 ret = emulate_ldh(regs, R3(regs->iir));
477 break;
478
479 case OPCODE_LDW_I:
480 case OPCODE_LDWA_I:
481 case OPCODE_LDW_S:
482 case OPCODE_LDWA_S:
483 ret = emulate_ldw(regs, R3(regs->iir), 0);
484 break;
485
486 case OPCODE_STH:
487 ret = emulate_sth(regs, R2(regs->iir));
488 break;
489
490 case OPCODE_STW:
491 case OPCODE_STWA:
492 ret = emulate_stw(regs, R2(regs->iir), 0);
493 break;
494
495 #ifdef CONFIG_64BIT
496 case OPCODE_LDD_I:
497 case OPCODE_LDDA_I:
498 case OPCODE_LDD_S:
499 case OPCODE_LDDA_S:
500 ret = emulate_ldd(regs, R3(regs->iir), 0);
501 break;
502
503 case OPCODE_STD:
504 case OPCODE_STDA:
505 ret = emulate_std(regs, R2(regs->iir), 0);
506 break;
507 #endif
508
509 case OPCODE_FLDWX:
510 case OPCODE_FLDWS:
511 case OPCODE_FLDWXR:
512 case OPCODE_FLDWSR:
513 ret = emulate_ldw(regs, FR3(regs->iir), 1);
514 break;
515
516 case OPCODE_FLDDX:
517 case OPCODE_FLDDS:
518 ret = emulate_ldd(regs, R3(regs->iir), 1);
519 break;
520
521 case OPCODE_FSTWX:
522 case OPCODE_FSTWS:
523 case OPCODE_FSTWXR:
524 case OPCODE_FSTWSR:
525 ret = emulate_stw(regs, FR3(regs->iir), 1);
526 break;
527
528 case OPCODE_FSTDX:
529 case OPCODE_FSTDS:
530 ret = emulate_std(regs, R3(regs->iir), 1);
531 break;
532
533 case OPCODE_LDCD_I:
534 case OPCODE_LDCW_I:
535 case OPCODE_LDCD_S:
536 case OPCODE_LDCW_S:
537 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
538 break;
539 }
540 switch (regs->iir & OPCODE2_MASK)
541 {
542 case OPCODE_FLDD_L:
543 ret = emulate_ldd(regs,R2(regs->iir),1);
544 break;
545 case OPCODE_FSTD_L:
546 ret = emulate_std(regs, R2(regs->iir),1);
547 break;
548 #ifdef CONFIG_64BIT
549 case OPCODE_LDD_L:
550 ret = emulate_ldd(regs, R2(regs->iir),0);
551 break;
552 case OPCODE_STD_L:
553 ret = emulate_std(regs, R2(regs->iir),0);
554 break;
555 #endif
556 }
557 switch (regs->iir & OPCODE3_MASK)
558 {
559 case OPCODE_FLDW_L:
560 ret = emulate_ldw(regs, R2(regs->iir), 1);
561 break;
562 case OPCODE_LDW_M:
563 ret = emulate_ldw(regs, R2(regs->iir), 0);
564 break;
565
566 case OPCODE_FSTW_L:
567 ret = emulate_stw(regs, R2(regs->iir),1);
568 break;
569 case OPCODE_STW_M:
570 ret = emulate_stw(regs, R2(regs->iir),0);
571 break;
572 }
573 switch (regs->iir & OPCODE4_MASK)
574 {
575 case OPCODE_LDH_L:
576 ret = emulate_ldh(regs, R2(regs->iir));
577 break;
578 case OPCODE_LDW_L:
579 case OPCODE_LDWM:
580 ret = emulate_ldw(regs, R2(regs->iir),0);
581 break;
582 case OPCODE_STH_L:
583 ret = emulate_sth(regs, R2(regs->iir));
584 break;
585 case OPCODE_STW_L:
586 case OPCODE_STWM:
587 ret = emulate_stw(regs, R2(regs->iir),0);
588 break;
589 }
590
591 if (ret == 0 && modify && R1(regs->iir))
592 regs->gr[R1(regs->iir)] = newbase;
593
594
595 if (ret == ERR_NOTHANDLED)
596 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
597
598 DPRINTF("ret = %d\n", ret);
599
600 if (ret)
601 {
602 /*
603 * The unaligned handler failed.
604 * If we were called by __get_user() or __put_user() jump
605 * to it's exception fixup handler instead of crashing.
606 */
607 if (!user_mode(regs) && fixup_exception(regs))
608 return;
609
610 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
611 die_if_kernel("Unaligned data reference", regs, 28);
612
613 if (ret == -EFAULT)
614 {
615 force_sig_fault(SIGSEGV, SEGV_MAPERR,
616 (void __user *)regs->ior);
617 }
618 else
619 {
620 force_sigbus:
621 /* couldn't handle it ... */
622 force_sig_fault(SIGBUS, BUS_ADRALN,
623 (void __user *)regs->ior);
624 }
625
626 return;
627 }
628
629 /* else we handled it, let life go on. */
630 regs->gr[0]|=PSW_N;
631 }
632
633 /*
634 * NB: check_unaligned() is only used for PCXS processors right
635 * now, so we only check for PA1.1 encodings at this point.
636 */
637
638 int
check_unaligned(struct pt_regs * regs)639 check_unaligned(struct pt_regs *regs)
640 {
641 unsigned long align_mask;
642
643 /* Get alignment mask */
644
645 align_mask = 0UL;
646 switch (regs->iir & OPCODE1_MASK) {
647
648 case OPCODE_LDH_I:
649 case OPCODE_LDH_S:
650 case OPCODE_STH:
651 align_mask = 1UL;
652 break;
653
654 case OPCODE_LDW_I:
655 case OPCODE_LDWA_I:
656 case OPCODE_LDW_S:
657 case OPCODE_LDWA_S:
658 case OPCODE_STW:
659 case OPCODE_STWA:
660 align_mask = 3UL;
661 break;
662
663 default:
664 switch (regs->iir & OPCODE4_MASK) {
665 case OPCODE_LDH_L:
666 case OPCODE_STH_L:
667 align_mask = 1UL;
668 break;
669 case OPCODE_LDW_L:
670 case OPCODE_LDWM:
671 case OPCODE_STW_L:
672 case OPCODE_STWM:
673 align_mask = 3UL;
674 break;
675 }
676 break;
677 }
678
679 return (int)(regs->ior & align_mask);
680 }
681
682