1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.txt. 5# 6 7config OPENRISC 8 def_bool y 9 select OF 10 select OF_EARLY_FLATTREE 11 select IRQ_DOMAIN 12 select HANDLE_DOMAIN_IRQ 13 select HAVE_MEMBLOCK 14 select GPIOLIB 15 select HAVE_ARCH_TRACEHOOK 16 select SPARSE_IRQ 17 select GENERIC_IRQ_CHIP 18 select GENERIC_IRQ_PROBE 19 select GENERIC_IRQ_SHOW 20 select GENERIC_IOMAP 21 select GENERIC_CPU_DEVICES 22 select HAVE_UID16 23 select GENERIC_ATOMIC64 24 select GENERIC_CLOCKEVENTS 25 select GENERIC_CLOCKEVENTS_BROADCAST 26 select GENERIC_STRNCPY_FROM_USER 27 select GENERIC_STRNLEN_USER 28 select GENERIC_SMP_IDLE_THREAD 29 select MODULES_USE_ELF_RELA 30 select HAVE_DEBUG_STACKOVERFLOW 31 select OR1K_PIC 32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 33 select NO_BOOTMEM 34 select ARCH_USE_QUEUED_SPINLOCKS 35 select ARCH_USE_QUEUED_RWLOCKS 36 select OMPIC if SMP 37 select ARCH_WANT_FRAME_POINTERS 38 select GENERIC_IRQ_MULTI_HANDLER 39 40config CPU_BIG_ENDIAN 41 def_bool y 42 43config MMU 44 def_bool y 45 46config RWSEM_GENERIC_SPINLOCK 47 def_bool y 48 49config RWSEM_XCHGADD_ALGORITHM 50 def_bool n 51 52config GENERIC_HWEIGHT 53 def_bool y 54 55config NO_IOPORT_MAP 56 def_bool y 57 58config TRACE_IRQFLAGS_SUPPORT 59 def_bool y 60 61# For now, use generic checksum functions 62#These can be reimplemented in assembly later if so inclined 63config GENERIC_CSUM 64 def_bool y 65 66config STACKTRACE_SUPPORT 67 def_bool y 68 69config LOCKDEP_SUPPORT 70 def_bool y 71 72source "init/Kconfig" 73 74source "kernel/Kconfig.freezer" 75 76menu "Processor type and features" 77 78choice 79 prompt "Subarchitecture" 80 default OR1K_1200 81 82config OR1K_1200 83 bool "OR1200" 84 help 85 Generic OpenRISC 1200 architecture 86 87endchoice 88 89config DCACHE_WRITETHROUGH 90 bool "Have write through data caches" 91 default n 92 help 93 Select this if your implementation features write through data caches. 94 Selecting 'N' here will allow the kernel to force flushing of data 95 caches at relevant times. Most OpenRISC implementations support write- 96 through data caches. 97 98 If unsure say N here 99 100config OPENRISC_BUILTIN_DTB 101 string "Builtin DTB" 102 default "" 103 104menu "Class II Instructions" 105 106config OPENRISC_HAVE_INST_FF1 107 bool "Have instruction l.ff1" 108 default y 109 help 110 Select this if your implementation has the Class II instruction l.ff1 111 112config OPENRISC_HAVE_INST_FL1 113 bool "Have instruction l.fl1" 114 default y 115 help 116 Select this if your implementation has the Class II instruction l.fl1 117 118config OPENRISC_HAVE_INST_MUL 119 bool "Have instruction l.mul for hardware multiply" 120 default y 121 help 122 Select this if your implementation has a hardware multiply instruction 123 124config OPENRISC_HAVE_INST_DIV 125 bool "Have instruction l.div for hardware divide" 126 default y 127 help 128 Select this if your implementation has a hardware divide instruction 129endmenu 130 131config NR_CPUS 132 int "Maximum number of CPUs (2-32)" 133 range 2 32 134 depends on SMP 135 default "2" 136 137config SMP 138 bool "Symmetric Multi-Processing support" 139 help 140 This enables support for systems with more than one CPU. If you have 141 a system with only one CPU, say N. If you have a system with more 142 than one CPU, say Y. 143 144 If you don't know what to do here, say N. 145 146source kernel/Kconfig.hz 147source kernel/Kconfig.preempt 148source "mm/Kconfig" 149 150config OPENRISC_NO_SPR_SR_DSX 151 bool "use SPR_SR_DSX software emulation" if OR1K_1200 152 default y 153 help 154 SPR_SR_DSX bit is status register bit indicating whether 155 the last exception has happened in delay slot. 156 157 OpenRISC architecture makes it optional to have it implemented 158 in hardware and the OR1200 does not have it. 159 160 Say N here if you know that your OpenRISC processor has 161 SPR_SR_DSX bit implemented. Say Y if you are unsure. 162 163config OPENRISC_HAVE_SHADOW_GPRS 164 bool "Support for shadow gpr files" if !SMP 165 default y if SMP 166 help 167 Say Y here if your OpenRISC processor features shadowed 168 register files. They will in such case be used as a 169 scratch reg storage on exception entry. 170 171 On SMP systems, this feature is mandatory. 172 On a unicore system it's safe to say N here if you are unsure. 173 174config CMDLINE 175 string "Default kernel command string" 176 default "" 177 help 178 On some architectures there is currently no way for the boot loader 179 to pass arguments to the kernel. For these architectures, you should 180 supply some command-line options at build time by entering them 181 here. 182 183menu "Debugging options" 184 185config JUMP_UPON_UNHANDLED_EXCEPTION 186 bool "Try to die gracefully" 187 default y 188 help 189 Now this puts kernel into infinite loop after first oops. Till 190 your kernel crashes this doesn't have any influence. 191 192 Say Y if you are unsure. 193 194config OPENRISC_ESR_EXCEPTION_BUG_CHECK 195 bool "Check for possible ESR exception bug" 196 default n 197 help 198 This option enables some checks that might expose some problems 199 in kernel. 200 201 Say N if you are unsure. 202 203endmenu 204 205endmenu 206 207menu "Executable file formats" 208 209source "fs/Kconfig.binfmt" 210 211endmenu 212 213source "net/Kconfig" 214 215source "drivers/Kconfig" 216 217source "fs/Kconfig" 218 219source "security/Kconfig" 220 221source "crypto/Kconfig" 222 223source "lib/Kconfig" 224 225menu "Kernel hacking" 226 227source "lib/Kconfig.debug" 228 229endmenu 230