1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select COMMON_CLK 14 select OF 15 select OF_EARLY_FLATTREE 16 select IRQ_DOMAIN 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select SPARSE_IRQ 20 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_PROBE 22 select GENERIC_IRQ_SHOW 23 select GENERIC_PCI_IOMAP 24 select GENERIC_IOREMAP 25 select GENERIC_CPU_DEVICES 26 select HAVE_PCI 27 select HAVE_UID16 28 select HAVE_PAGE_SIZE_8KB 29 select GENERIC_ATOMIC64 30 select GENERIC_CLOCKEVENTS_BROADCAST 31 select GENERIC_SMP_IDLE_THREAD 32 select MODULES_USE_ELF_RELA 33 select HAVE_DEBUG_STACKOVERFLOW 34 select OR1K_PIC 35 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 36 select ARCH_USE_QUEUED_RWLOCKS 37 select OMPIC if SMP 38 select PCI_DOMAINS_GENERIC if PCI 39 select PCI_MSI if PCI 40 select ARCH_WANT_FRAME_POINTERS 41 select GENERIC_IRQ_MULTI_HANDLER 42 select MMU_GATHER_NO_RANGE if MMU 43 select TRACE_IRQFLAGS_SUPPORT 44 45config CPU_BIG_ENDIAN 46 def_bool y 47 48config MMU 49 def_bool y 50 51config GENERIC_HWEIGHT 52 def_bool y 53 54config NO_IOPORT_MAP 55 def_bool y 56 57# For now, use generic checksum functions 58#These can be reimplemented in assembly later if so inclined 59config GENERIC_CSUM 60 def_bool y 61 62config STACKTRACE_SUPPORT 63 def_bool y 64 65config LOCKDEP_SUPPORT 66 def_bool y 67 68config FIX_EARLYCON_MEM 69 def_bool y 70 71menu "Processor type and features" 72 73choice 74 prompt "Subarchitecture" 75 default OR1K_1200 76 77config OR1K_1200 78 bool "OR1200" 79 help 80 Generic OpenRISC 1200 architecture 81 82endchoice 83 84config DCACHE_WRITETHROUGH 85 bool "Have write through data caches" 86 default n 87 help 88 Select this if your implementation features write through data caches. 89 Selecting 'N' here will allow the kernel to force flushing of data 90 caches at relevant times. Most OpenRISC implementations support write- 91 through data caches. 92 93 If unsure say N here 94 95config OPENRISC_BUILTIN_DTB 96 string "Builtin DTB" 97 default "" 98 99menu "Class II Instructions" 100 101config OPENRISC_HAVE_INST_FF1 102 bool "Have instruction l.ff1" 103 default y 104 help 105 Select this if your implementation has the Class II instruction l.ff1 106 107config OPENRISC_HAVE_INST_FL1 108 bool "Have instruction l.fl1" 109 default y 110 help 111 Select this if your implementation has the Class II instruction l.fl1 112 113config OPENRISC_HAVE_INST_MUL 114 bool "Have instruction l.mul for hardware multiply" 115 default y 116 help 117 Select this if your implementation has a hardware multiply instruction 118 119config OPENRISC_HAVE_INST_DIV 120 bool "Have instruction l.div for hardware divide" 121 default y 122 help 123 Select this if your implementation has a hardware divide instruction 124 125config OPENRISC_HAVE_INST_CMOV 126 bool "Have instruction l.cmov for conditional move" 127 default n 128 help 129 This config enables gcc to generate l.cmov instructions when compiling 130 the kernel which in general will improve performance and reduce the 131 binary size. 132 133 Select this if your implementation has support for the Class II 134 l.cmov conistional move instruction. 135 136 Say N if you are unsure. 137 138config OPENRISC_HAVE_INST_ROR 139 bool "Have instruction l.ror for rotate right" 140 default n 141 help 142 This config enables gcc to generate l.ror instructions when compiling 143 the kernel which in general will improve performance and reduce the 144 binary size. 145 146 Select this if your implementation has support for the Class II 147 l.ror rotate right instruction. 148 149 Say N if you are unsure. 150 151config OPENRISC_HAVE_INST_RORI 152 bool "Have instruction l.rori for rotate right with immediate" 153 default n 154 help 155 This config enables gcc to generate l.rori instructions when compiling 156 the kernel which in general will improve performance and reduce the 157 binary size. 158 159 Select this if your implementation has support for the Class II 160 l.rori rotate right with immediate instruction. 161 162 Say N if you are unsure. 163 164config OPENRISC_HAVE_INST_SEXT 165 bool "Have instructions l.ext* for sign extension" 166 default n 167 help 168 This config enables gcc to generate l.ext* instructions when compiling 169 the kernel which in general will improve performance and reduce the 170 binary size. 171 172 Select this if your implementation has support for the Class II 173 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 174 175 Say N if you are unsure. 176 177endmenu 178 179config NR_CPUS 180 int "Maximum number of CPUs (2-32)" 181 range 2 32 182 depends on SMP 183 default "2" 184 185config SMP 186 bool "Symmetric Multi-Processing support" 187 help 188 This enables support for systems with more than one CPU. If you have 189 a system with only one CPU, say N. If you have a system with more 190 than one CPU, say Y. 191 192 If you don't know what to do here, say N. 193 194config FPU 195 bool "FPU support" 196 default y 197 help 198 Say N here if you want to disable all floating-point related procedures 199 in the kernel and reduce binary size. 200 201 If you don't know what to do here, say Y. 202 203source "kernel/Kconfig.hz" 204 205config OPENRISC_NO_SPR_SR_DSX 206 bool "use SPR_SR_DSX software emulation" if OR1K_1200 207 default y 208 help 209 SPR_SR_DSX bit is status register bit indicating whether 210 the last exception has happened in delay slot. 211 212 OpenRISC architecture makes it optional to have it implemented 213 in hardware and the OR1200 does not have it. 214 215 Say N here if you know that your OpenRISC processor has 216 SPR_SR_DSX bit implemented. Say Y if you are unsure. 217 218config OPENRISC_HAVE_SHADOW_GPRS 219 bool "Support for shadow gpr files" if !SMP 220 default y if SMP 221 help 222 Say Y here if your OpenRISC processor features shadowed 223 register files. They will in such case be used as a 224 scratch reg storage on exception entry. 225 226 On SMP systems, this feature is mandatory. 227 On a unicore system it's safe to say N here if you are unsure. 228 229config CMDLINE 230 string "Default kernel command string" 231 default "" 232 help 233 On some architectures there is currently no way for the boot loader 234 to pass arguments to the kernel. For these architectures, you should 235 supply some command-line options at build time by entering them 236 here. 237 238menu "Debugging options" 239 240config JUMP_UPON_UNHANDLED_EXCEPTION 241 bool "Try to die gracefully" 242 default y 243 help 244 Now this puts kernel into infinite loop after first oops. Till 245 your kernel crashes this doesn't have any influence. 246 247 Say Y if you are unsure. 248 249config OPENRISC_ESR_EXCEPTION_BUG_CHECK 250 bool "Check for possible ESR exception bug" 251 default n 252 help 253 This option enables some checks that might expose some problems 254 in kernel. 255 256 Say N if you are unsure. 257 258endmenu 259 260endmenu 261