1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select COMMON_CLK 14 select OF 15 select OF_EARLY_FLATTREE 16 select IRQ_DOMAIN 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select SPARSE_IRQ 20 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_PROBE 22 select GENERIC_IRQ_SHOW 23 select GENERIC_PCI_IOMAP 24 select GENERIC_CPU_DEVICES 25 select HAVE_PCI 26 select HAVE_UID16 27 select GENERIC_ATOMIC64 28 select GENERIC_CLOCKEVENTS_BROADCAST 29 select GENERIC_SMP_IDLE_THREAD 30 select MODULES_USE_ELF_RELA 31 select HAVE_DEBUG_STACKOVERFLOW 32 select OR1K_PIC 33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 34 select ARCH_USE_QUEUED_RWLOCKS 35 select OMPIC if SMP 36 select PCI_DOMAINS_GENERIC if PCI 37 select PCI_MSI if PCI 38 select ARCH_WANT_FRAME_POINTERS 39 select GENERIC_IRQ_MULTI_HANDLER 40 select MMU_GATHER_NO_RANGE if MMU 41 select TRACE_IRQFLAGS_SUPPORT 42 43config CPU_BIG_ENDIAN 44 def_bool y 45 46config MMU 47 def_bool y 48 49config GENERIC_HWEIGHT 50 def_bool y 51 52config NO_IOPORT_MAP 53 def_bool y 54 55# For now, use generic checksum functions 56#These can be reimplemented in assembly later if so inclined 57config GENERIC_CSUM 58 def_bool y 59 60config STACKTRACE_SUPPORT 61 def_bool y 62 63config LOCKDEP_SUPPORT 64 def_bool y 65 66menu "Processor type and features" 67 68choice 69 prompt "Subarchitecture" 70 default OR1K_1200 71 72config OR1K_1200 73 bool "OR1200" 74 help 75 Generic OpenRISC 1200 architecture 76 77endchoice 78 79config DCACHE_WRITETHROUGH 80 bool "Have write through data caches" 81 default n 82 help 83 Select this if your implementation features write through data caches. 84 Selecting 'N' here will allow the kernel to force flushing of data 85 caches at relevant times. Most OpenRISC implementations support write- 86 through data caches. 87 88 If unsure say N here 89 90config OPENRISC_BUILTIN_DTB 91 string "Builtin DTB" 92 default "" 93 94menu "Class II Instructions" 95 96config OPENRISC_HAVE_INST_FF1 97 bool "Have instruction l.ff1" 98 default y 99 help 100 Select this if your implementation has the Class II instruction l.ff1 101 102config OPENRISC_HAVE_INST_FL1 103 bool "Have instruction l.fl1" 104 default y 105 help 106 Select this if your implementation has the Class II instruction l.fl1 107 108config OPENRISC_HAVE_INST_MUL 109 bool "Have instruction l.mul for hardware multiply" 110 default y 111 help 112 Select this if your implementation has a hardware multiply instruction 113 114config OPENRISC_HAVE_INST_DIV 115 bool "Have instruction l.div for hardware divide" 116 default y 117 help 118 Select this if your implementation has a hardware divide instruction 119 120config OPENRISC_HAVE_INST_CMOV 121 bool "Have instruction l.cmov for conditional move" 122 default n 123 help 124 This config enables gcc to generate l.cmov instructions when compiling 125 the kernel which in general will improve performance and reduce the 126 binary size. 127 128 Select this if your implementation has support for the Class II 129 l.cmov conistional move instruction. 130 131 Say N if you are unsure. 132 133config OPENRISC_HAVE_INST_ROR 134 bool "Have instruction l.ror for rotate right" 135 default n 136 help 137 This config enables gcc to generate l.ror instructions when compiling 138 the kernel which in general will improve performance and reduce the 139 binary size. 140 141 Select this if your implementation has support for the Class II 142 l.ror rotate right instruction. 143 144 Say N if you are unsure. 145 146config OPENRISC_HAVE_INST_RORI 147 bool "Have instruction l.rori for rotate right with immediate" 148 default n 149 help 150 This config enables gcc to generate l.rori instructions when compiling 151 the kernel which in general will improve performance and reduce the 152 binary size. 153 154 Select this if your implementation has support for the Class II 155 l.rori rotate right with immediate instruction. 156 157 Say N if you are unsure. 158 159config OPENRISC_HAVE_INST_SEXT 160 bool "Have instructions l.ext* for sign extension" 161 default n 162 help 163 This config enables gcc to generate l.ext* instructions when compiling 164 the kernel which in general will improve performance and reduce the 165 binary size. 166 167 Select this if your implementation has support for the Class II 168 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 169 170 Say N if you are unsure. 171 172endmenu 173 174config NR_CPUS 175 int "Maximum number of CPUs (2-32)" 176 range 2 32 177 depends on SMP 178 default "2" 179 180config SMP 181 bool "Symmetric Multi-Processing support" 182 help 183 This enables support for systems with more than one CPU. If you have 184 a system with only one CPU, say N. If you have a system with more 185 than one CPU, say Y. 186 187 If you don't know what to do here, say N. 188 189source "kernel/Kconfig.hz" 190 191config OPENRISC_NO_SPR_SR_DSX 192 bool "use SPR_SR_DSX software emulation" if OR1K_1200 193 default y 194 help 195 SPR_SR_DSX bit is status register bit indicating whether 196 the last exception has happened in delay slot. 197 198 OpenRISC architecture makes it optional to have it implemented 199 in hardware and the OR1200 does not have it. 200 201 Say N here if you know that your OpenRISC processor has 202 SPR_SR_DSX bit implemented. Say Y if you are unsure. 203 204config OPENRISC_HAVE_SHADOW_GPRS 205 bool "Support for shadow gpr files" if !SMP 206 default y if SMP 207 help 208 Say Y here if your OpenRISC processor features shadowed 209 register files. They will in such case be used as a 210 scratch reg storage on exception entry. 211 212 On SMP systems, this feature is mandatory. 213 On a unicore system it's safe to say N here if you are unsure. 214 215config CMDLINE 216 string "Default kernel command string" 217 default "" 218 help 219 On some architectures there is currently no way for the boot loader 220 to pass arguments to the kernel. For these architectures, you should 221 supply some command-line options at build time by entering them 222 here. 223 224menu "Debugging options" 225 226config JUMP_UPON_UNHANDLED_EXCEPTION 227 bool "Try to die gracefully" 228 default y 229 help 230 Now this puts kernel into infinite loop after first oops. Till 231 your kernel crashes this doesn't have any influence. 232 233 Say Y if you are unsure. 234 235config OPENRISC_ESR_EXCEPTION_BUG_CHECK 236 bool "Check for possible ESR exception bug" 237 default n 238 help 239 This option enables some checks that might expose some problems 240 in kernel. 241 242 Say N if you are unsure. 243 244endmenu 245 246endmenu 247