1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DELAY_TIMER 11 select ARCH_HAS_DMA_SET_UNCACHED 12 select ARCH_HAS_DMA_CLEAR_UNCACHED 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 14 select GENERIC_BUILTIN_DTB 15 select COMMON_CLK 16 select OF 17 select OF_EARLY_FLATTREE 18 select IRQ_DOMAIN 19 select GPIOLIB 20 select HAVE_ARCH_TRACEHOOK 21 select SPARSE_IRQ 22 select GENERIC_IRQ_CHIP 23 select GENERIC_IRQ_PROBE 24 select GENERIC_IRQ_SHOW 25 select GENERIC_PCI_IOMAP 26 select GENERIC_IOREMAP 27 select GENERIC_CPU_DEVICES 28 select HAVE_ARCH_JUMP_LABEL 29 select HAVE_ARCH_JUMP_LABEL_RELATIVE 30 select HAVE_PCI 31 select HAVE_UID16 32 select HAVE_PAGE_SIZE_8KB 33 select HAVE_REGS_AND_STACK_ACCESS_API 34 select HAVE_RSEQ 35 select GENERIC_ATOMIC64 36 select GENERIC_CLOCKEVENTS_BROADCAST 37 select GENERIC_SMP_IDLE_THREAD 38 select MODULES_USE_ELF_RELA 39 select HAVE_DEBUG_STACKOVERFLOW 40 select OR1K_PIC 41 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 42 select ARCH_USE_QUEUED_RWLOCKS 43 select OMPIC if SMP 44 select PCI_DOMAINS_GENERIC if PCI 45 select PCI_MSI if PCI 46 select ARCH_WANT_FRAME_POINTERS 47 select GENERIC_IRQ_MULTI_HANDLER 48 select MMU_GATHER_NO_RANGE if MMU 49 select TRACE_IRQFLAGS_SUPPORT 50 51config CPU_BIG_ENDIAN 52 def_bool y 53 54config MMU 55 def_bool y 56 57config GENERIC_HWEIGHT 58 def_bool y 59 60config NO_IOPORT_MAP 61 def_bool y 62 63# For now, use generic checksum functions 64#These can be reimplemented in assembly later if so inclined 65config GENERIC_CSUM 66 def_bool y 67 68config STACKTRACE_SUPPORT 69 def_bool y 70 71config LOCKDEP_SUPPORT 72 def_bool y 73 74config FIX_EARLYCON_MEM 75 def_bool y 76 77menu "Processor type and features" 78 79choice 80 prompt "Subarchitecture" 81 default OR1K_1200 82 83config OR1K_1200 84 bool "OR1200" 85 help 86 Generic OpenRISC 1200 architecture 87 88endchoice 89 90config DCACHE_WRITETHROUGH 91 bool "Have write through data caches" 92 default n 93 help 94 Select this if your implementation features write through data caches. 95 Selecting 'N' here will allow the kernel to force flushing of data 96 caches at relevant times. Most OpenRISC implementations support write- 97 through data caches. 98 99 If unsure say N here 100 101config BUILTIN_DTB_NAME 102 string "Builtin DTB" 103 default "" 104 105menu "Class II Instructions" 106 107config OPENRISC_HAVE_INST_FF1 108 bool "Have instruction l.ff1" 109 default y 110 help 111 Select this if your implementation has the Class II instruction l.ff1 112 113config OPENRISC_HAVE_INST_FL1 114 bool "Have instruction l.fl1" 115 default y 116 help 117 Select this if your implementation has the Class II instruction l.fl1 118 119config OPENRISC_HAVE_INST_MUL 120 bool "Have instruction l.mul for hardware multiply" 121 default y 122 help 123 Select this if your implementation has a hardware multiply instruction 124 125config OPENRISC_HAVE_INST_DIV 126 bool "Have instruction l.div for hardware divide" 127 default y 128 help 129 Select this if your implementation has a hardware divide instruction 130 131config OPENRISC_HAVE_INST_CMOV 132 bool "Have instruction l.cmov for conditional move" 133 default n 134 help 135 This config enables gcc to generate l.cmov instructions when compiling 136 the kernel which in general will improve performance and reduce the 137 binary size. 138 139 Select this if your implementation has support for the Class II 140 l.cmov conistional move instruction. 141 142 Say N if you are unsure. 143 144config OPENRISC_HAVE_INST_ROR 145 bool "Have instruction l.ror for rotate right" 146 default n 147 help 148 This config enables gcc to generate l.ror instructions when compiling 149 the kernel which in general will improve performance and reduce the 150 binary size. 151 152 Select this if your implementation has support for the Class II 153 l.ror rotate right instruction. 154 155 Say N if you are unsure. 156 157config OPENRISC_HAVE_INST_RORI 158 bool "Have instruction l.rori for rotate right with immediate" 159 default n 160 help 161 This config enables gcc to generate l.rori instructions when compiling 162 the kernel which in general will improve performance and reduce the 163 binary size. 164 165 Select this if your implementation has support for the Class II 166 l.rori rotate right with immediate instruction. 167 168 Say N if you are unsure. 169 170config OPENRISC_HAVE_INST_SEXT 171 bool "Have instructions l.ext* for sign extension" 172 default n 173 help 174 This config enables gcc to generate l.ext* instructions when compiling 175 the kernel which in general will improve performance and reduce the 176 binary size. 177 178 Select this if your implementation has support for the Class II 179 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 180 181 Say N if you are unsure. 182 183endmenu 184 185config NR_CPUS 186 int "Maximum number of CPUs (2-32)" 187 range 2 32 188 depends on SMP 189 default "2" 190 191config SMP 192 bool "Symmetric Multi-Processing support" 193 help 194 This enables support for systems with more than one CPU. If you have 195 a system with only one CPU, say N. If you have a system with more 196 than one CPU, say Y. 197 198 If you don't know what to do here, say N. 199 200config FPU 201 bool "FPU support" 202 default y 203 help 204 Say N here if you want to disable all floating-point related procedures 205 in the kernel and reduce binary size. 206 207 If you don't know what to do here, say Y. 208 209source "kernel/Kconfig.hz" 210 211config OPENRISC_NO_SPR_SR_DSX 212 bool "use SPR_SR_DSX software emulation" if OR1K_1200 213 default y 214 help 215 SPR_SR_DSX bit is status register bit indicating whether 216 the last exception has happened in delay slot. 217 218 OpenRISC architecture makes it optional to have it implemented 219 in hardware and the OR1200 does not have it. 220 221 Say N here if you know that your OpenRISC processor has 222 SPR_SR_DSX bit implemented. Say Y if you are unsure. 223 224config OPENRISC_HAVE_SHADOW_GPRS 225 bool "Support for shadow gpr files" if !SMP 226 default y if SMP 227 help 228 Say Y here if your OpenRISC processor features shadowed 229 register files. They will in such case be used as a 230 scratch reg storage on exception entry. 231 232 On SMP systems, this feature is mandatory. 233 On a unicore system it's safe to say N here if you are unsure. 234 235config CMDLINE 236 string "Default kernel command string" 237 default "" 238 help 239 On some architectures there is currently no way for the boot loader 240 to pass arguments to the kernel. For these architectures, you should 241 supply some command-line options at build time by entering them 242 here. 243 244menu "Debugging options" 245 246config JUMP_UPON_UNHANDLED_EXCEPTION 247 bool "Try to die gracefully" 248 default y 249 help 250 Now this puts kernel into infinite loop after first oops. Till 251 your kernel crashes this doesn't have any influence. 252 253 Say Y if you are unsure. 254 255config OPENRISC_ESR_EXCEPTION_BUG_CHECK 256 bool "Check for possible ESR exception bug" 257 default n 258 help 259 This option enables some checks that might expose some problems 260 in kernel. 261 262 Say N if you are unsure. 263 264endmenu 265 266endmenu 267