1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select OF 14 select OF_EARLY_FLATTREE 15 select IRQ_DOMAIN 16 select HANDLE_DOMAIN_IRQ 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select HAVE_COPY_THREAD_TLS 20 select SPARSE_IRQ 21 select GENERIC_IRQ_CHIP 22 select GENERIC_IRQ_PROBE 23 select GENERIC_IRQ_SHOW 24 select GENERIC_IOMAP 25 select GENERIC_CPU_DEVICES 26 select HAVE_UID16 27 select GENERIC_ATOMIC64 28 select GENERIC_CLOCKEVENTS 29 select GENERIC_CLOCKEVENTS_BROADCAST 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select GENERIC_SMP_IDLE_THREAD 33 select MODULES_USE_ELF_RELA 34 select HAVE_DEBUG_STACKOVERFLOW 35 select OR1K_PIC 36 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 37 select ARCH_USE_QUEUED_SPINLOCKS 38 select ARCH_USE_QUEUED_RWLOCKS 39 select OMPIC if SMP 40 select ARCH_WANT_FRAME_POINTERS 41 select GENERIC_IRQ_MULTI_HANDLER 42 select MMU_GATHER_NO_RANGE if MMU 43 44config CPU_BIG_ENDIAN 45 def_bool y 46 47config MMU 48 def_bool y 49 50config GENERIC_HWEIGHT 51 def_bool y 52 53config NO_IOPORT_MAP 54 def_bool y 55 56config TRACE_IRQFLAGS_SUPPORT 57 def_bool y 58 59# For now, use generic checksum functions 60#These can be reimplemented in assembly later if so inclined 61config GENERIC_CSUM 62 def_bool y 63 64config STACKTRACE_SUPPORT 65 def_bool y 66 67config LOCKDEP_SUPPORT 68 def_bool y 69 70menu "Processor type and features" 71 72choice 73 prompt "Subarchitecture" 74 default OR1K_1200 75 76config OR1K_1200 77 bool "OR1200" 78 help 79 Generic OpenRISC 1200 architecture 80 81endchoice 82 83config DCACHE_WRITETHROUGH 84 bool "Have write through data caches" 85 default n 86 help 87 Select this if your implementation features write through data caches. 88 Selecting 'N' here will allow the kernel to force flushing of data 89 caches at relevant times. Most OpenRISC implementations support write- 90 through data caches. 91 92 If unsure say N here 93 94config OPENRISC_BUILTIN_DTB 95 string "Builtin DTB" 96 default "" 97 98menu "Class II Instructions" 99 100config OPENRISC_HAVE_INST_FF1 101 bool "Have instruction l.ff1" 102 default y 103 help 104 Select this if your implementation has the Class II instruction l.ff1 105 106config OPENRISC_HAVE_INST_FL1 107 bool "Have instruction l.fl1" 108 default y 109 help 110 Select this if your implementation has the Class II instruction l.fl1 111 112config OPENRISC_HAVE_INST_MUL 113 bool "Have instruction l.mul for hardware multiply" 114 default y 115 help 116 Select this if your implementation has a hardware multiply instruction 117 118config OPENRISC_HAVE_INST_DIV 119 bool "Have instruction l.div for hardware divide" 120 default y 121 help 122 Select this if your implementation has a hardware divide instruction 123endmenu 124 125config NR_CPUS 126 int "Maximum number of CPUs (2-32)" 127 range 2 32 128 depends on SMP 129 default "2" 130 131config SMP 132 bool "Symmetric Multi-Processing support" 133 help 134 This enables support for systems with more than one CPU. If you have 135 a system with only one CPU, say N. If you have a system with more 136 than one CPU, say Y. 137 138 If you don't know what to do here, say N. 139 140source "kernel/Kconfig.hz" 141 142config OPENRISC_NO_SPR_SR_DSX 143 bool "use SPR_SR_DSX software emulation" if OR1K_1200 144 default y 145 help 146 SPR_SR_DSX bit is status register bit indicating whether 147 the last exception has happened in delay slot. 148 149 OpenRISC architecture makes it optional to have it implemented 150 in hardware and the OR1200 does not have it. 151 152 Say N here if you know that your OpenRISC processor has 153 SPR_SR_DSX bit implemented. Say Y if you are unsure. 154 155config OPENRISC_HAVE_SHADOW_GPRS 156 bool "Support for shadow gpr files" if !SMP 157 default y if SMP 158 help 159 Say Y here if your OpenRISC processor features shadowed 160 register files. They will in such case be used as a 161 scratch reg storage on exception entry. 162 163 On SMP systems, this feature is mandatory. 164 On a unicore system it's safe to say N here if you are unsure. 165 166config CMDLINE 167 string "Default kernel command string" 168 default "" 169 help 170 On some architectures there is currently no way for the boot loader 171 to pass arguments to the kernel. For these architectures, you should 172 supply some command-line options at build time by entering them 173 here. 174 175menu "Debugging options" 176 177config JUMP_UPON_UNHANDLED_EXCEPTION 178 bool "Try to die gracefully" 179 default y 180 help 181 Now this puts kernel into infinite loop after first oops. Till 182 your kernel crashes this doesn't have any influence. 183 184 Say Y if you are unsure. 185 186config OPENRISC_ESR_EXCEPTION_BUG_CHECK 187 bool "Check for possible ESR exception bug" 188 default n 189 help 190 This option enables some checks that might expose some problems 191 in kernel. 192 193 Say N if you are unsure. 194 195endmenu 196 197endmenu 198