1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * KVM/MIPS: MIPS specific KVM APIs 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/errno.h> 14 #include <linux/err.h> 15 #include <linux/kdebug.h> 16 #include <linux/module.h> 17 #include <linux/uaccess.h> 18 #include <linux/vmalloc.h> 19 #include <linux/sched/signal.h> 20 #include <linux/fs.h> 21 #include <linux/bootmem.h> 22 23 #include <asm/fpu.h> 24 #include <asm/page.h> 25 #include <asm/cacheflush.h> 26 #include <asm/mmu_context.h> 27 #include <asm/pgalloc.h> 28 #include <asm/pgtable.h> 29 30 #include <linux/kvm_host.h> 31 32 #include "interrupt.h" 33 #include "commpage.h" 34 35 #define CREATE_TRACE_POINTS 36 #include "trace.h" 37 38 #ifndef VECTORSPACING 39 #define VECTORSPACING 0x100 /* for EI/VI mode */ 40 #endif 41 42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) 43 struct kvm_stats_debugfs_item debugfs_entries[] = { 44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, 45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, 46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, 47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, 48 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, 49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, 50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, 51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, 52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, 53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, 54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, 55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, 56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, 57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, 58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, 59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, 60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, 61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, 62 #ifdef CONFIG_KVM_MIPS_VZ 63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU }, 64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU }, 65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU }, 66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU }, 67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU }, 68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU }, 69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU }, 70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU }, 71 #endif 72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, 73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, 74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, 75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, 76 {NULL} 77 }; 78 79 bool kvm_trace_guest_mode_change; 80 81 int kvm_guest_mode_change_trace_reg(void) 82 { 83 kvm_trace_guest_mode_change = 1; 84 return 0; 85 } 86 87 void kvm_guest_mode_change_trace_unreg(void) 88 { 89 kvm_trace_guest_mode_change = 0; 90 } 91 92 /* 93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in 94 * Config7, so we are "runnable" if interrupts are pending 95 */ 96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 97 { 98 return !!(vcpu->arch.pending_exceptions); 99 } 100 101 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 102 { 103 return 1; 104 } 105 106 int kvm_arch_hardware_enable(void) 107 { 108 return kvm_mips_callbacks->hardware_enable(); 109 } 110 111 void kvm_arch_hardware_disable(void) 112 { 113 kvm_mips_callbacks->hardware_disable(); 114 } 115 116 int kvm_arch_hardware_setup(void) 117 { 118 return 0; 119 } 120 121 void kvm_arch_check_processor_compat(void *rtn) 122 { 123 *(int *)rtn = 0; 124 } 125 126 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) 127 { 128 switch (type) { 129 #ifdef CONFIG_KVM_MIPS_VZ 130 case KVM_VM_MIPS_VZ: 131 #else 132 case KVM_VM_MIPS_TE: 133 #endif 134 break; 135 default: 136 /* Unsupported KVM type */ 137 return -EINVAL; 138 }; 139 140 /* Allocate page table to map GPA -> RPA */ 141 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); 142 if (!kvm->arch.gpa_mm.pgd) 143 return -ENOMEM; 144 145 return 0; 146 } 147 148 bool kvm_arch_has_vcpu_debugfs(void) 149 { 150 return false; 151 } 152 153 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) 154 { 155 return 0; 156 } 157 158 void kvm_mips_free_vcpus(struct kvm *kvm) 159 { 160 unsigned int i; 161 struct kvm_vcpu *vcpu; 162 163 kvm_for_each_vcpu(i, vcpu, kvm) { 164 kvm_arch_vcpu_free(vcpu); 165 } 166 167 mutex_lock(&kvm->lock); 168 169 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) 170 kvm->vcpus[i] = NULL; 171 172 atomic_set(&kvm->online_vcpus, 0); 173 174 mutex_unlock(&kvm->lock); 175 } 176 177 static void kvm_mips_free_gpa_pt(struct kvm *kvm) 178 { 179 /* It should always be safe to remove after flushing the whole range */ 180 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); 181 pgd_free(NULL, kvm->arch.gpa_mm.pgd); 182 } 183 184 void kvm_arch_destroy_vm(struct kvm *kvm) 185 { 186 kvm_mips_free_vcpus(kvm); 187 kvm_mips_free_gpa_pt(kvm); 188 } 189 190 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, 191 unsigned long arg) 192 { 193 return -ENOIOCTLCMD; 194 } 195 196 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, 197 unsigned long npages) 198 { 199 return 0; 200 } 201 202 void kvm_arch_flush_shadow_all(struct kvm *kvm) 203 { 204 /* Flush whole GPA */ 205 kvm_mips_flush_gpa_pt(kvm, 0, ~0); 206 207 /* Let implementation do the rest */ 208 kvm_mips_callbacks->flush_shadow_all(kvm); 209 } 210 211 void kvm_arch_flush_shadow_memslot(struct kvm *kvm, 212 struct kvm_memory_slot *slot) 213 { 214 /* 215 * The slot has been made invalid (ready for moving or deletion), so we 216 * need to ensure that it can no longer be accessed by any guest VCPUs. 217 */ 218 219 spin_lock(&kvm->mmu_lock); 220 /* Flush slot from GPA */ 221 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, 222 slot->base_gfn + slot->npages - 1); 223 /* Let implementation do the rest */ 224 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); 225 spin_unlock(&kvm->mmu_lock); 226 } 227 228 int kvm_arch_prepare_memory_region(struct kvm *kvm, 229 struct kvm_memory_slot *memslot, 230 const struct kvm_userspace_memory_region *mem, 231 enum kvm_mr_change change) 232 { 233 return 0; 234 } 235 236 void kvm_arch_commit_memory_region(struct kvm *kvm, 237 const struct kvm_userspace_memory_region *mem, 238 const struct kvm_memory_slot *old, 239 const struct kvm_memory_slot *new, 240 enum kvm_mr_change change) 241 { 242 int needs_flush; 243 244 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", 245 __func__, kvm, mem->slot, mem->guest_phys_addr, 246 mem->memory_size, mem->userspace_addr); 247 248 /* 249 * If dirty page logging is enabled, write protect all pages in the slot 250 * ready for dirty logging. 251 * 252 * There is no need to do this in any of the following cases: 253 * CREATE: No dirty mappings will already exist. 254 * MOVE/DELETE: The old mappings will already have been cleaned up by 255 * kvm_arch_flush_shadow_memslot() 256 */ 257 if (change == KVM_MR_FLAGS_ONLY && 258 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && 259 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { 260 spin_lock(&kvm->mmu_lock); 261 /* Write protect GPA page table entries */ 262 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, 263 new->base_gfn + new->npages - 1); 264 /* Let implementation do the rest */ 265 if (needs_flush) 266 kvm_mips_callbacks->flush_shadow_memslot(kvm, new); 267 spin_unlock(&kvm->mmu_lock); 268 } 269 } 270 271 static inline void dump_handler(const char *symbol, void *start, void *end) 272 { 273 u32 *p; 274 275 pr_debug("LEAF(%s)\n", symbol); 276 277 pr_debug("\t.set push\n"); 278 pr_debug("\t.set noreorder\n"); 279 280 for (p = start; p < (u32 *)end; ++p) 281 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); 282 283 pr_debug("\t.set\tpop\n"); 284 285 pr_debug("\tEND(%s)\n", symbol); 286 } 287 288 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) 289 { 290 int err, size; 291 void *gebase, *p, *handler, *refill_start, *refill_end; 292 int i; 293 294 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); 295 296 if (!vcpu) { 297 err = -ENOMEM; 298 goto out; 299 } 300 301 err = kvm_vcpu_init(vcpu, kvm, id); 302 303 if (err) 304 goto out_free_cpu; 305 306 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); 307 308 /* 309 * Allocate space for host mode exception handlers that handle 310 * guest mode exits 311 */ 312 if (cpu_has_veic || cpu_has_vint) 313 size = 0x200 + VECTORSPACING * 64; 314 else 315 size = 0x4000; 316 317 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); 318 319 if (!gebase) { 320 err = -ENOMEM; 321 goto out_uninit_cpu; 322 } 323 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", 324 ALIGN(size, PAGE_SIZE), gebase); 325 326 /* 327 * Check new ebase actually fits in CP0_EBase. The lack of a write gate 328 * limits us to the low 512MB of physical address space. If the memory 329 * we allocate is out of range, just give up now. 330 */ 331 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { 332 kvm_err("CP0_EBase.WG required for guest exception base %pK\n", 333 gebase); 334 err = -ENOMEM; 335 goto out_free_gebase; 336 } 337 338 /* Save new ebase */ 339 vcpu->arch.guest_ebase = gebase; 340 341 /* Build guest exception vectors dynamically in unmapped memory */ 342 handler = gebase + 0x2000; 343 344 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */ 345 refill_start = gebase; 346 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT)) 347 refill_start += 0x080; 348 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); 349 350 /* General Exception Entry point */ 351 kvm_mips_build_exception(gebase + 0x180, handler); 352 353 /* For vectored interrupts poke the exception code @ all offsets 0-7 */ 354 for (i = 0; i < 8; i++) { 355 kvm_debug("L1 Vectored handler @ %p\n", 356 gebase + 0x200 + (i * VECTORSPACING)); 357 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, 358 handler); 359 } 360 361 /* General exit handler */ 362 p = handler; 363 p = kvm_mips_build_exit(p); 364 365 /* Guest entry routine */ 366 vcpu->arch.vcpu_run = p; 367 p = kvm_mips_build_vcpu_run(p); 368 369 /* Dump the generated code */ 370 pr_debug("#include <asm/asm.h>\n"); 371 pr_debug("#include <asm/regdef.h>\n"); 372 pr_debug("\n"); 373 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); 374 dump_handler("kvm_tlb_refill", refill_start, refill_end); 375 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); 376 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); 377 378 /* Invalidate the icache for these ranges */ 379 flush_icache_range((unsigned long)gebase, 380 (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); 381 382 /* 383 * Allocate comm page for guest kernel, a TLB will be reserved for 384 * mapping GVA @ 0xFFFF8000 to this page 385 */ 386 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); 387 388 if (!vcpu->arch.kseg0_commpage) { 389 err = -ENOMEM; 390 goto out_free_gebase; 391 } 392 393 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); 394 kvm_mips_commpage_init(vcpu); 395 396 /* Init */ 397 vcpu->arch.last_sched_cpu = -1; 398 vcpu->arch.last_exec_cpu = -1; 399 400 return vcpu; 401 402 out_free_gebase: 403 kfree(gebase); 404 405 out_uninit_cpu: 406 kvm_vcpu_uninit(vcpu); 407 408 out_free_cpu: 409 kfree(vcpu); 410 411 out: 412 return ERR_PTR(err); 413 } 414 415 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) 416 { 417 hrtimer_cancel(&vcpu->arch.comparecount_timer); 418 419 kvm_vcpu_uninit(vcpu); 420 421 kvm_mips_dump_stats(vcpu); 422 423 kvm_mmu_free_memory_caches(vcpu); 424 kfree(vcpu->arch.guest_ebase); 425 kfree(vcpu->arch.kseg0_commpage); 426 kfree(vcpu); 427 } 428 429 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 430 { 431 kvm_arch_vcpu_free(vcpu); 432 } 433 434 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 435 struct kvm_guest_debug *dbg) 436 { 437 return -ENOIOCTLCMD; 438 } 439 440 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) 441 { 442 int r = -EINTR; 443 sigset_t sigsaved; 444 445 if (vcpu->sigset_active) 446 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); 447 448 if (vcpu->mmio_needed) { 449 if (!vcpu->mmio_is_write) 450 kvm_mips_complete_mmio_load(vcpu, run); 451 vcpu->mmio_needed = 0; 452 } 453 454 if (run->immediate_exit) 455 goto out; 456 457 lose_fpu(1); 458 459 local_irq_disable(); 460 guest_enter_irqoff(); 461 trace_kvm_enter(vcpu); 462 463 /* 464 * Make sure the read of VCPU requests in vcpu_run() callback is not 465 * reordered ahead of the write to vcpu->mode, or we could miss a TLB 466 * flush request while the requester sees the VCPU as outside of guest 467 * mode and not needing an IPI. 468 */ 469 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 470 471 r = kvm_mips_callbacks->vcpu_run(run, vcpu); 472 473 trace_kvm_out(vcpu); 474 guest_exit_irqoff(); 475 local_irq_enable(); 476 477 out: 478 if (vcpu->sigset_active) 479 sigprocmask(SIG_SETMASK, &sigsaved, NULL); 480 481 return r; 482 } 483 484 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, 485 struct kvm_mips_interrupt *irq) 486 { 487 int intr = (int)irq->irq; 488 struct kvm_vcpu *dvcpu = NULL; 489 490 if (intr == 3 || intr == -3 || intr == 4 || intr == -4) 491 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, 492 (int)intr); 493 494 if (irq->cpu == -1) 495 dvcpu = vcpu; 496 else 497 dvcpu = vcpu->kvm->vcpus[irq->cpu]; 498 499 if (intr == 2 || intr == 3 || intr == 4) { 500 kvm_mips_callbacks->queue_io_int(dvcpu, irq); 501 502 } else if (intr == -2 || intr == -3 || intr == -4) { 503 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); 504 } else { 505 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, 506 irq->cpu, irq->irq); 507 return -EINVAL; 508 } 509 510 dvcpu->arch.wait = 0; 511 512 if (swait_active(&dvcpu->wq)) 513 swake_up(&dvcpu->wq); 514 515 return 0; 516 } 517 518 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 519 struct kvm_mp_state *mp_state) 520 { 521 return -ENOIOCTLCMD; 522 } 523 524 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 525 struct kvm_mp_state *mp_state) 526 { 527 return -ENOIOCTLCMD; 528 } 529 530 static u64 kvm_mips_get_one_regs[] = { 531 KVM_REG_MIPS_R0, 532 KVM_REG_MIPS_R1, 533 KVM_REG_MIPS_R2, 534 KVM_REG_MIPS_R3, 535 KVM_REG_MIPS_R4, 536 KVM_REG_MIPS_R5, 537 KVM_REG_MIPS_R6, 538 KVM_REG_MIPS_R7, 539 KVM_REG_MIPS_R8, 540 KVM_REG_MIPS_R9, 541 KVM_REG_MIPS_R10, 542 KVM_REG_MIPS_R11, 543 KVM_REG_MIPS_R12, 544 KVM_REG_MIPS_R13, 545 KVM_REG_MIPS_R14, 546 KVM_REG_MIPS_R15, 547 KVM_REG_MIPS_R16, 548 KVM_REG_MIPS_R17, 549 KVM_REG_MIPS_R18, 550 KVM_REG_MIPS_R19, 551 KVM_REG_MIPS_R20, 552 KVM_REG_MIPS_R21, 553 KVM_REG_MIPS_R22, 554 KVM_REG_MIPS_R23, 555 KVM_REG_MIPS_R24, 556 KVM_REG_MIPS_R25, 557 KVM_REG_MIPS_R26, 558 KVM_REG_MIPS_R27, 559 KVM_REG_MIPS_R28, 560 KVM_REG_MIPS_R29, 561 KVM_REG_MIPS_R30, 562 KVM_REG_MIPS_R31, 563 564 #ifndef CONFIG_CPU_MIPSR6 565 KVM_REG_MIPS_HI, 566 KVM_REG_MIPS_LO, 567 #endif 568 KVM_REG_MIPS_PC, 569 }; 570 571 static u64 kvm_mips_get_one_regs_fpu[] = { 572 KVM_REG_MIPS_FCR_IR, 573 KVM_REG_MIPS_FCR_CSR, 574 }; 575 576 static u64 kvm_mips_get_one_regs_msa[] = { 577 KVM_REG_MIPS_MSA_IR, 578 KVM_REG_MIPS_MSA_CSR, 579 }; 580 581 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) 582 { 583 unsigned long ret; 584 585 ret = ARRAY_SIZE(kvm_mips_get_one_regs); 586 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 587 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; 588 /* odd doubles */ 589 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) 590 ret += 16; 591 } 592 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) 593 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; 594 ret += kvm_mips_callbacks->num_regs(vcpu); 595 596 return ret; 597 } 598 599 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) 600 { 601 u64 index; 602 unsigned int i; 603 604 if (copy_to_user(indices, kvm_mips_get_one_regs, 605 sizeof(kvm_mips_get_one_regs))) 606 return -EFAULT; 607 indices += ARRAY_SIZE(kvm_mips_get_one_regs); 608 609 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { 610 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, 611 sizeof(kvm_mips_get_one_regs_fpu))) 612 return -EFAULT; 613 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); 614 615 for (i = 0; i < 32; ++i) { 616 index = KVM_REG_MIPS_FPR_32(i); 617 if (copy_to_user(indices, &index, sizeof(index))) 618 return -EFAULT; 619 ++indices; 620 621 /* skip odd doubles if no F64 */ 622 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) 623 continue; 624 625 index = KVM_REG_MIPS_FPR_64(i); 626 if (copy_to_user(indices, &index, sizeof(index))) 627 return -EFAULT; 628 ++indices; 629 } 630 } 631 632 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { 633 if (copy_to_user(indices, kvm_mips_get_one_regs_msa, 634 sizeof(kvm_mips_get_one_regs_msa))) 635 return -EFAULT; 636 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); 637 638 for (i = 0; i < 32; ++i) { 639 index = KVM_REG_MIPS_VEC_128(i); 640 if (copy_to_user(indices, &index, sizeof(index))) 641 return -EFAULT; 642 ++indices; 643 } 644 } 645 646 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); 647 } 648 649 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 650 const struct kvm_one_reg *reg) 651 { 652 struct mips_coproc *cop0 = vcpu->arch.cop0; 653 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 654 int ret; 655 s64 v; 656 s64 vs[2]; 657 unsigned int idx; 658 659 switch (reg->id) { 660 /* General purpose registers */ 661 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: 662 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; 663 break; 664 #ifndef CONFIG_CPU_MIPSR6 665 case KVM_REG_MIPS_HI: 666 v = (long)vcpu->arch.hi; 667 break; 668 case KVM_REG_MIPS_LO: 669 v = (long)vcpu->arch.lo; 670 break; 671 #endif 672 case KVM_REG_MIPS_PC: 673 v = (long)vcpu->arch.pc; 674 break; 675 676 /* Floating point registers */ 677 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 678 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 679 return -EINVAL; 680 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 681 /* Odd singles in top of even double when FR=0 */ 682 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 683 v = get_fpr32(&fpu->fpr[idx], 0); 684 else 685 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); 686 break; 687 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 688 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 689 return -EINVAL; 690 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 691 /* Can't access odd doubles in FR=0 mode */ 692 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 693 return -EINVAL; 694 v = get_fpr64(&fpu->fpr[idx], 0); 695 break; 696 case KVM_REG_MIPS_FCR_IR: 697 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 698 return -EINVAL; 699 v = boot_cpu_data.fpu_id; 700 break; 701 case KVM_REG_MIPS_FCR_CSR: 702 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 703 return -EINVAL; 704 v = fpu->fcr31; 705 break; 706 707 /* MIPS SIMD Architecture (MSA) registers */ 708 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 709 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 710 return -EINVAL; 711 /* Can't access MSA registers in FR=0 mode */ 712 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) 713 return -EINVAL; 714 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 715 #ifdef CONFIG_CPU_LITTLE_ENDIAN 716 /* least significant byte first */ 717 vs[0] = get_fpr64(&fpu->fpr[idx], 0); 718 vs[1] = get_fpr64(&fpu->fpr[idx], 1); 719 #else 720 /* most significant byte first */ 721 vs[0] = get_fpr64(&fpu->fpr[idx], 1); 722 vs[1] = get_fpr64(&fpu->fpr[idx], 0); 723 #endif 724 break; 725 case KVM_REG_MIPS_MSA_IR: 726 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 727 return -EINVAL; 728 v = boot_cpu_data.msa_id; 729 break; 730 case KVM_REG_MIPS_MSA_CSR: 731 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 732 return -EINVAL; 733 v = fpu->msacsr; 734 break; 735 736 /* registers to be handled specially */ 737 default: 738 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); 739 if (ret) 740 return ret; 741 break; 742 } 743 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 744 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 745 746 return put_user(v, uaddr64); 747 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 748 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 749 u32 v32 = (u32)v; 750 751 return put_user(v32, uaddr32); 752 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 753 void __user *uaddr = (void __user *)(long)reg->addr; 754 755 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; 756 } else { 757 return -EINVAL; 758 } 759 } 760 761 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 762 const struct kvm_one_reg *reg) 763 { 764 struct mips_coproc *cop0 = vcpu->arch.cop0; 765 struct mips_fpu_struct *fpu = &vcpu->arch.fpu; 766 s64 v; 767 s64 vs[2]; 768 unsigned int idx; 769 770 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { 771 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; 772 773 if (get_user(v, uaddr64) != 0) 774 return -EFAULT; 775 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { 776 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; 777 s32 v32; 778 779 if (get_user(v32, uaddr32) != 0) 780 return -EFAULT; 781 v = (s64)v32; 782 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { 783 void __user *uaddr = (void __user *)(long)reg->addr; 784 785 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; 786 } else { 787 return -EINVAL; 788 } 789 790 switch (reg->id) { 791 /* General purpose registers */ 792 case KVM_REG_MIPS_R0: 793 /* Silently ignore requests to set $0 */ 794 break; 795 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: 796 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; 797 break; 798 #ifndef CONFIG_CPU_MIPSR6 799 case KVM_REG_MIPS_HI: 800 vcpu->arch.hi = v; 801 break; 802 case KVM_REG_MIPS_LO: 803 vcpu->arch.lo = v; 804 break; 805 #endif 806 case KVM_REG_MIPS_PC: 807 vcpu->arch.pc = v; 808 break; 809 810 /* Floating point registers */ 811 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): 812 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 813 return -EINVAL; 814 idx = reg->id - KVM_REG_MIPS_FPR_32(0); 815 /* Odd singles in top of even double when FR=0 */ 816 if (kvm_read_c0_guest_status(cop0) & ST0_FR) 817 set_fpr32(&fpu->fpr[idx], 0, v); 818 else 819 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); 820 break; 821 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): 822 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 823 return -EINVAL; 824 idx = reg->id - KVM_REG_MIPS_FPR_64(0); 825 /* Can't access odd doubles in FR=0 mode */ 826 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) 827 return -EINVAL; 828 set_fpr64(&fpu->fpr[idx], 0, v); 829 break; 830 case KVM_REG_MIPS_FCR_IR: 831 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 832 return -EINVAL; 833 /* Read-only */ 834 break; 835 case KVM_REG_MIPS_FCR_CSR: 836 if (!kvm_mips_guest_has_fpu(&vcpu->arch)) 837 return -EINVAL; 838 fpu->fcr31 = v; 839 break; 840 841 /* MIPS SIMD Architecture (MSA) registers */ 842 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): 843 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 844 return -EINVAL; 845 idx = reg->id - KVM_REG_MIPS_VEC_128(0); 846 #ifdef CONFIG_CPU_LITTLE_ENDIAN 847 /* least significant byte first */ 848 set_fpr64(&fpu->fpr[idx], 0, vs[0]); 849 set_fpr64(&fpu->fpr[idx], 1, vs[1]); 850 #else 851 /* most significant byte first */ 852 set_fpr64(&fpu->fpr[idx], 1, vs[0]); 853 set_fpr64(&fpu->fpr[idx], 0, vs[1]); 854 #endif 855 break; 856 case KVM_REG_MIPS_MSA_IR: 857 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 858 return -EINVAL; 859 /* Read-only */ 860 break; 861 case KVM_REG_MIPS_MSA_CSR: 862 if (!kvm_mips_guest_has_msa(&vcpu->arch)) 863 return -EINVAL; 864 fpu->msacsr = v; 865 break; 866 867 /* registers to be handled specially */ 868 default: 869 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); 870 } 871 return 0; 872 } 873 874 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 875 struct kvm_enable_cap *cap) 876 { 877 int r = 0; 878 879 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) 880 return -EINVAL; 881 if (cap->flags) 882 return -EINVAL; 883 if (cap->args[0]) 884 return -EINVAL; 885 886 switch (cap->cap) { 887 case KVM_CAP_MIPS_FPU: 888 vcpu->arch.fpu_enabled = true; 889 break; 890 case KVM_CAP_MIPS_MSA: 891 vcpu->arch.msa_enabled = true; 892 break; 893 default: 894 r = -EINVAL; 895 break; 896 } 897 898 return r; 899 } 900 901 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, 902 unsigned long arg) 903 { 904 struct kvm_vcpu *vcpu = filp->private_data; 905 void __user *argp = (void __user *)arg; 906 long r; 907 908 switch (ioctl) { 909 case KVM_SET_ONE_REG: 910 case KVM_GET_ONE_REG: { 911 struct kvm_one_reg reg; 912 913 if (copy_from_user(®, argp, sizeof(reg))) 914 return -EFAULT; 915 if (ioctl == KVM_SET_ONE_REG) 916 return kvm_mips_set_reg(vcpu, ®); 917 else 918 return kvm_mips_get_reg(vcpu, ®); 919 } 920 case KVM_GET_REG_LIST: { 921 struct kvm_reg_list __user *user_list = argp; 922 struct kvm_reg_list reg_list; 923 unsigned n; 924 925 if (copy_from_user(®_list, user_list, sizeof(reg_list))) 926 return -EFAULT; 927 n = reg_list.n; 928 reg_list.n = kvm_mips_num_regs(vcpu); 929 if (copy_to_user(user_list, ®_list, sizeof(reg_list))) 930 return -EFAULT; 931 if (n < reg_list.n) 932 return -E2BIG; 933 return kvm_mips_copy_reg_indices(vcpu, user_list->reg); 934 } 935 case KVM_INTERRUPT: 936 { 937 struct kvm_mips_interrupt irq; 938 939 if (copy_from_user(&irq, argp, sizeof(irq))) 940 return -EFAULT; 941 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, 942 irq.irq); 943 944 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); 945 break; 946 } 947 case KVM_ENABLE_CAP: { 948 struct kvm_enable_cap cap; 949 950 if (copy_from_user(&cap, argp, sizeof(cap))) 951 return -EFAULT; 952 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 953 break; 954 } 955 default: 956 r = -ENOIOCTLCMD; 957 } 958 return r; 959 } 960 961 /** 962 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot 963 * @kvm: kvm instance 964 * @log: slot id and address to which we copy the log 965 * 966 * Steps 1-4 below provide general overview of dirty page logging. See 967 * kvm_get_dirty_log_protect() function description for additional details. 968 * 969 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we 970 * always flush the TLB (step 4) even if previous step failed and the dirty 971 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API 972 * does not preclude user space subsequent dirty log read. Flushing TLB ensures 973 * writes will be marked dirty for next log read. 974 * 975 * 1. Take a snapshot of the bit and clear it if needed. 976 * 2. Write protect the corresponding page. 977 * 3. Copy the snapshot to the userspace. 978 * 4. Flush TLB's if needed. 979 */ 980 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) 981 { 982 struct kvm_memslots *slots; 983 struct kvm_memory_slot *memslot; 984 bool is_dirty = false; 985 int r; 986 987 mutex_lock(&kvm->slots_lock); 988 989 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); 990 991 if (is_dirty) { 992 slots = kvm_memslots(kvm); 993 memslot = id_to_memslot(slots, log->slot); 994 995 /* Let implementation handle TLB/GVA invalidation */ 996 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); 997 } 998 999 mutex_unlock(&kvm->slots_lock); 1000 return r; 1001 } 1002 1003 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) 1004 { 1005 long r; 1006 1007 switch (ioctl) { 1008 default: 1009 r = -ENOIOCTLCMD; 1010 } 1011 1012 return r; 1013 } 1014 1015 int kvm_arch_init(void *opaque) 1016 { 1017 if (kvm_mips_callbacks) { 1018 kvm_err("kvm: module already exists\n"); 1019 return -EEXIST; 1020 } 1021 1022 return kvm_mips_emulation_init(&kvm_mips_callbacks); 1023 } 1024 1025 void kvm_arch_exit(void) 1026 { 1027 kvm_mips_callbacks = NULL; 1028 } 1029 1030 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, 1031 struct kvm_sregs *sregs) 1032 { 1033 return -ENOIOCTLCMD; 1034 } 1035 1036 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, 1037 struct kvm_sregs *sregs) 1038 { 1039 return -ENOIOCTLCMD; 1040 } 1041 1042 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1043 { 1044 } 1045 1046 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1047 { 1048 return -ENOIOCTLCMD; 1049 } 1050 1051 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1052 { 1053 return -ENOIOCTLCMD; 1054 } 1055 1056 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 1057 { 1058 return VM_FAULT_SIGBUS; 1059 } 1060 1061 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) 1062 { 1063 int r; 1064 1065 switch (ext) { 1066 case KVM_CAP_ONE_REG: 1067 case KVM_CAP_ENABLE_CAP: 1068 case KVM_CAP_READONLY_MEM: 1069 case KVM_CAP_SYNC_MMU: 1070 case KVM_CAP_IMMEDIATE_EXIT: 1071 r = 1; 1072 break; 1073 case KVM_CAP_NR_VCPUS: 1074 r = num_online_cpus(); 1075 break; 1076 case KVM_CAP_MAX_VCPUS: 1077 r = KVM_MAX_VCPUS; 1078 break; 1079 case KVM_CAP_MIPS_FPU: 1080 /* We don't handle systems with inconsistent cpu_has_fpu */ 1081 r = !!raw_cpu_has_fpu; 1082 break; 1083 case KVM_CAP_MIPS_MSA: 1084 /* 1085 * We don't support MSA vector partitioning yet: 1086 * 1) It would require explicit support which can't be tested 1087 * yet due to lack of support in current hardware. 1088 * 2) It extends the state that would need to be saved/restored 1089 * by e.g. QEMU for migration. 1090 * 1091 * When vector partitioning hardware becomes available, support 1092 * could be added by requiring a flag when enabling 1093 * KVM_CAP_MIPS_MSA capability to indicate that userland knows 1094 * to save/restore the appropriate extra state. 1095 */ 1096 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); 1097 break; 1098 default: 1099 r = kvm_mips_callbacks->check_extension(kvm, ext); 1100 break; 1101 } 1102 return r; 1103 } 1104 1105 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 1106 { 1107 return kvm_mips_pending_timer(vcpu) || 1108 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI; 1109 } 1110 1111 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 1112 { 1113 int i; 1114 struct mips_coproc *cop0; 1115 1116 if (!vcpu) 1117 return -1; 1118 1119 kvm_debug("VCPU Register Dump:\n"); 1120 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); 1121 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); 1122 1123 for (i = 0; i < 32; i += 4) { 1124 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, 1125 vcpu->arch.gprs[i], 1126 vcpu->arch.gprs[i + 1], 1127 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 1128 } 1129 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); 1130 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); 1131 1132 cop0 = vcpu->arch.cop0; 1133 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n", 1134 kvm_read_c0_guest_status(cop0), 1135 kvm_read_c0_guest_cause(cop0)); 1136 1137 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); 1138 1139 return 0; 1140 } 1141 1142 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1143 { 1144 int i; 1145 1146 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1147 vcpu->arch.gprs[i] = regs->gpr[i]; 1148 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1149 vcpu->arch.hi = regs->hi; 1150 vcpu->arch.lo = regs->lo; 1151 vcpu->arch.pc = regs->pc; 1152 1153 return 0; 1154 } 1155 1156 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1157 { 1158 int i; 1159 1160 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1161 regs->gpr[i] = vcpu->arch.gprs[i]; 1162 1163 regs->hi = vcpu->arch.hi; 1164 regs->lo = vcpu->arch.lo; 1165 regs->pc = vcpu->arch.pc; 1166 1167 return 0; 1168 } 1169 1170 static void kvm_mips_comparecount_func(unsigned long data) 1171 { 1172 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; 1173 1174 kvm_mips_callbacks->queue_timer_int(vcpu); 1175 1176 vcpu->arch.wait = 0; 1177 if (swait_active(&vcpu->wq)) 1178 swake_up(&vcpu->wq); 1179 } 1180 1181 /* low level hrtimer wake routine */ 1182 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) 1183 { 1184 struct kvm_vcpu *vcpu; 1185 1186 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); 1187 kvm_mips_comparecount_func((unsigned long) vcpu); 1188 return kvm_mips_count_timeout(vcpu); 1189 } 1190 1191 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) 1192 { 1193 int err; 1194 1195 err = kvm_mips_callbacks->vcpu_init(vcpu); 1196 if (err) 1197 return err; 1198 1199 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1200 HRTIMER_MODE_REL); 1201 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1202 return 0; 1203 } 1204 1205 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) 1206 { 1207 kvm_mips_callbacks->vcpu_uninit(vcpu); 1208 } 1209 1210 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 1211 struct kvm_translation *tr) 1212 { 1213 return 0; 1214 } 1215 1216 /* Initial guest state */ 1217 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) 1218 { 1219 return kvm_mips_callbacks->vcpu_setup(vcpu); 1220 } 1221 1222 static void kvm_mips_set_c0_status(void) 1223 { 1224 u32 status = read_c0_status(); 1225 1226 if (cpu_has_dsp) 1227 status |= (ST0_MX); 1228 1229 write_c0_status(status); 1230 ehb(); 1231 } 1232 1233 /* 1234 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) 1235 */ 1236 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 1237 { 1238 u32 cause = vcpu->arch.host_cp0_cause; 1239 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; 1240 u32 __user *opc = (u32 __user *) vcpu->arch.pc; 1241 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; 1242 enum emulation_result er = EMULATE_DONE; 1243 u32 inst; 1244 int ret = RESUME_GUEST; 1245 1246 vcpu->mode = OUTSIDE_GUEST_MODE; 1247 1248 /* re-enable HTW before enabling interrupts */ 1249 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1250 htw_start(); 1251 1252 /* Set a default exit reason */ 1253 run->exit_reason = KVM_EXIT_UNKNOWN; 1254 run->ready_for_interrupt_injection = 1; 1255 1256 /* 1257 * Set the appropriate status bits based on host CPU features, 1258 * before we hit the scheduler 1259 */ 1260 kvm_mips_set_c0_status(); 1261 1262 local_irq_enable(); 1263 1264 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", 1265 cause, opc, run, vcpu); 1266 trace_kvm_exit(vcpu, exccode); 1267 1268 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1269 /* 1270 * Do a privilege check, if in UM most of these exit conditions 1271 * end up causing an exception to be delivered to the Guest 1272 * Kernel 1273 */ 1274 er = kvm_mips_check_privilege(cause, opc, run, vcpu); 1275 if (er == EMULATE_PRIV_FAIL) { 1276 goto skip_emul; 1277 } else if (er == EMULATE_FAIL) { 1278 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1279 ret = RESUME_HOST; 1280 goto skip_emul; 1281 } 1282 } 1283 1284 switch (exccode) { 1285 case EXCCODE_INT: 1286 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); 1287 1288 ++vcpu->stat.int_exits; 1289 1290 if (need_resched()) 1291 cond_resched(); 1292 1293 ret = RESUME_GUEST; 1294 break; 1295 1296 case EXCCODE_CPU: 1297 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); 1298 1299 ++vcpu->stat.cop_unusable_exits; 1300 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); 1301 /* XXXKYMA: Might need to return to user space */ 1302 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) 1303 ret = RESUME_HOST; 1304 break; 1305 1306 case EXCCODE_MOD: 1307 ++vcpu->stat.tlbmod_exits; 1308 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); 1309 break; 1310 1311 case EXCCODE_TLBS: 1312 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n", 1313 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, 1314 badvaddr); 1315 1316 ++vcpu->stat.tlbmiss_st_exits; 1317 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); 1318 break; 1319 1320 case EXCCODE_TLBL: 1321 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", 1322 cause, opc, badvaddr); 1323 1324 ++vcpu->stat.tlbmiss_ld_exits; 1325 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); 1326 break; 1327 1328 case EXCCODE_ADES: 1329 ++vcpu->stat.addrerr_st_exits; 1330 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); 1331 break; 1332 1333 case EXCCODE_ADEL: 1334 ++vcpu->stat.addrerr_ld_exits; 1335 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); 1336 break; 1337 1338 case EXCCODE_SYS: 1339 ++vcpu->stat.syscall_exits; 1340 ret = kvm_mips_callbacks->handle_syscall(vcpu); 1341 break; 1342 1343 case EXCCODE_RI: 1344 ++vcpu->stat.resvd_inst_exits; 1345 ret = kvm_mips_callbacks->handle_res_inst(vcpu); 1346 break; 1347 1348 case EXCCODE_BP: 1349 ++vcpu->stat.break_inst_exits; 1350 ret = kvm_mips_callbacks->handle_break(vcpu); 1351 break; 1352 1353 case EXCCODE_TR: 1354 ++vcpu->stat.trap_inst_exits; 1355 ret = kvm_mips_callbacks->handle_trap(vcpu); 1356 break; 1357 1358 case EXCCODE_MSAFPE: 1359 ++vcpu->stat.msa_fpe_exits; 1360 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); 1361 break; 1362 1363 case EXCCODE_FPE: 1364 ++vcpu->stat.fpe_exits; 1365 ret = kvm_mips_callbacks->handle_fpe(vcpu); 1366 break; 1367 1368 case EXCCODE_MSADIS: 1369 ++vcpu->stat.msa_disabled_exits; 1370 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); 1371 break; 1372 1373 case EXCCODE_GE: 1374 /* defer exit accounting to handler */ 1375 ret = kvm_mips_callbacks->handle_guest_exit(vcpu); 1376 break; 1377 1378 default: 1379 if (cause & CAUSEF_BD) 1380 opc += 1; 1381 inst = 0; 1382 kvm_get_badinstr(opc, vcpu, &inst); 1383 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n", 1384 exccode, opc, inst, badvaddr, 1385 kvm_read_c0_guest_status(vcpu->arch.cop0)); 1386 kvm_arch_vcpu_dump_regs(vcpu); 1387 run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 1388 ret = RESUME_HOST; 1389 break; 1390 1391 } 1392 1393 skip_emul: 1394 local_irq_disable(); 1395 1396 if (ret == RESUME_GUEST) 1397 kvm_vz_acquire_htimer(vcpu); 1398 1399 if (er == EMULATE_DONE && !(ret & RESUME_HOST)) 1400 kvm_mips_deliver_interrupts(vcpu, cause); 1401 1402 if (!(ret & RESUME_HOST)) { 1403 /* Only check for signals if not already exiting to userspace */ 1404 if (signal_pending(current)) { 1405 run->exit_reason = KVM_EXIT_INTR; 1406 ret = (-EINTR << 2) | RESUME_HOST; 1407 ++vcpu->stat.signal_exits; 1408 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); 1409 } 1410 } 1411 1412 if (ret == RESUME_GUEST) { 1413 trace_kvm_reenter(vcpu); 1414 1415 /* 1416 * Make sure the read of VCPU requests in vcpu_reenter() 1417 * callback is not reordered ahead of the write to vcpu->mode, 1418 * or we could miss a TLB flush request while the requester sees 1419 * the VCPU as outside of guest mode and not needing an IPI. 1420 */ 1421 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 1422 1423 kvm_mips_callbacks->vcpu_reenter(run, vcpu); 1424 1425 /* 1426 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context 1427 * is live), restore FCR31 / MSACSR. 1428 * 1429 * This should be before returning to the guest exception 1430 * vector, as it may well cause an [MSA] FP exception if there 1431 * are pending exception bits unmasked. (see 1432 * kvm_mips_csr_die_notifier() for how that is handled). 1433 */ 1434 if (kvm_mips_guest_has_fpu(&vcpu->arch) && 1435 read_c0_status() & ST0_CU1) 1436 __kvm_restore_fcsr(&vcpu->arch); 1437 1438 if (kvm_mips_guest_has_msa(&vcpu->arch) && 1439 read_c0_config5() & MIPS_CONF5_MSAEN) 1440 __kvm_restore_msacsr(&vcpu->arch); 1441 } 1442 1443 /* Disable HTW before returning to guest or host */ 1444 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) 1445 htw_stop(); 1446 1447 return ret; 1448 } 1449 1450 /* Enable FPU for guest and restore context */ 1451 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1452 { 1453 struct mips_coproc *cop0 = vcpu->arch.cop0; 1454 unsigned int sr, cfg5; 1455 1456 preempt_disable(); 1457 1458 sr = kvm_read_c0_guest_status(cop0); 1459 1460 /* 1461 * If MSA state is already live, it is undefined how it interacts with 1462 * FR=0 FPU state, and we don't want to hit reserved instruction 1463 * exceptions trying to save the MSA state later when CU=1 && FR=1, so 1464 * play it safe and save it first. 1465 * 1466 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should 1467 * get called when guest CU1 is set, however we can't trust the guest 1468 * not to clobber the status register directly via the commpage. 1469 */ 1470 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && 1471 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) 1472 kvm_lose_fpu(vcpu); 1473 1474 /* 1475 * Enable FPU for guest 1476 * We set FR and FRE according to guest context 1477 */ 1478 change_c0_status(ST0_CU1 | ST0_FR, sr); 1479 if (cpu_has_fre) { 1480 cfg5 = kvm_read_c0_guest_config5(cop0); 1481 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1482 } 1483 enable_fpu_hazard(); 1484 1485 /* If guest FPU state not active, restore it now */ 1486 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { 1487 __kvm_restore_fpu(&vcpu->arch); 1488 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1489 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1490 } else { 1491 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); 1492 } 1493 1494 preempt_enable(); 1495 } 1496 1497 #ifdef CONFIG_CPU_HAS_MSA 1498 /* Enable MSA for guest and restore context */ 1499 void kvm_own_msa(struct kvm_vcpu *vcpu) 1500 { 1501 struct mips_coproc *cop0 = vcpu->arch.cop0; 1502 unsigned int sr, cfg5; 1503 1504 preempt_disable(); 1505 1506 /* 1507 * Enable FPU if enabled in guest, since we're restoring FPU context 1508 * anyway. We set FR and FRE according to guest context. 1509 */ 1510 if (kvm_mips_guest_has_fpu(&vcpu->arch)) { 1511 sr = kvm_read_c0_guest_status(cop0); 1512 1513 /* 1514 * If FR=0 FPU state is already live, it is undefined how it 1515 * interacts with MSA state, so play it safe and save it first. 1516 */ 1517 if (!(sr & ST0_FR) && 1518 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | 1519 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) 1520 kvm_lose_fpu(vcpu); 1521 1522 change_c0_status(ST0_CU1 | ST0_FR, sr); 1523 if (sr & ST0_CU1 && cpu_has_fre) { 1524 cfg5 = kvm_read_c0_guest_config5(cop0); 1525 change_c0_config5(MIPS_CONF5_FRE, cfg5); 1526 } 1527 } 1528 1529 /* Enable MSA for guest */ 1530 set_c0_config5(MIPS_CONF5_MSAEN); 1531 enable_fpu_hazard(); 1532 1533 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { 1534 case KVM_MIPS_AUX_FPU: 1535 /* 1536 * Guest FPU state already loaded, only restore upper MSA state 1537 */ 1538 __kvm_restore_msa_upper(&vcpu->arch); 1539 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1540 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); 1541 break; 1542 case 0: 1543 /* Neither FPU or MSA already active, restore full MSA state */ 1544 __kvm_restore_msa(&vcpu->arch); 1545 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; 1546 if (kvm_mips_guest_has_fpu(&vcpu->arch)) 1547 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; 1548 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, 1549 KVM_TRACE_AUX_FPU_MSA); 1550 break; 1551 default: 1552 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); 1553 break; 1554 } 1555 1556 preempt_enable(); 1557 } 1558 #endif 1559 1560 /* Drop FPU & MSA without saving it */ 1561 void kvm_drop_fpu(struct kvm_vcpu *vcpu) 1562 { 1563 preempt_disable(); 1564 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1565 disable_msa(); 1566 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); 1567 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; 1568 } 1569 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1570 clear_c0_status(ST0_CU1 | ST0_FR); 1571 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); 1572 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1573 } 1574 preempt_enable(); 1575 } 1576 1577 /* Save and disable FPU & MSA */ 1578 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1579 { 1580 /* 1581 * With T&E, FPU & MSA get disabled in root context (hardware) when it 1582 * is disabled in guest context (software), but the register state in 1583 * the hardware may still be in use. 1584 * This is why we explicitly re-enable the hardware before saving. 1585 */ 1586 1587 preempt_disable(); 1588 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { 1589 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1590 set_c0_config5(MIPS_CONF5_MSAEN); 1591 enable_fpu_hazard(); 1592 } 1593 1594 __kvm_save_msa(&vcpu->arch); 1595 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); 1596 1597 /* Disable MSA & FPU */ 1598 disable_msa(); 1599 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1600 clear_c0_status(ST0_CU1 | ST0_FR); 1601 disable_fpu_hazard(); 1602 } 1603 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); 1604 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { 1605 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) { 1606 set_c0_status(ST0_CU1); 1607 enable_fpu_hazard(); 1608 } 1609 1610 __kvm_save_fpu(&vcpu->arch); 1611 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; 1612 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1613 1614 /* Disable FPU */ 1615 clear_c0_status(ST0_CU1 | ST0_FR); 1616 disable_fpu_hazard(); 1617 } 1618 preempt_enable(); 1619 } 1620 1621 /* 1622 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are 1623 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP 1624 * exception if cause bits are set in the value being written. 1625 */ 1626 static int kvm_mips_csr_die_notify(struct notifier_block *self, 1627 unsigned long cmd, void *ptr) 1628 { 1629 struct die_args *args = (struct die_args *)ptr; 1630 struct pt_regs *regs = args->regs; 1631 unsigned long pc; 1632 1633 /* Only interested in FPE and MSAFPE */ 1634 if (cmd != DIE_FP && cmd != DIE_MSAFP) 1635 return NOTIFY_DONE; 1636 1637 /* Return immediately if guest context isn't active */ 1638 if (!(current->flags & PF_VCPU)) 1639 return NOTIFY_DONE; 1640 1641 /* Should never get here from user mode */ 1642 BUG_ON(user_mode(regs)); 1643 1644 pc = instruction_pointer(regs); 1645 switch (cmd) { 1646 case DIE_FP: 1647 /* match 2nd instruction in __kvm_restore_fcsr */ 1648 if (pc != (unsigned long)&__kvm_restore_fcsr + 4) 1649 return NOTIFY_DONE; 1650 break; 1651 case DIE_MSAFP: 1652 /* match 2nd/3rd instruction in __kvm_restore_msacsr */ 1653 if (!cpu_has_msa || 1654 pc < (unsigned long)&__kvm_restore_msacsr + 4 || 1655 pc > (unsigned long)&__kvm_restore_msacsr + 8) 1656 return NOTIFY_DONE; 1657 break; 1658 } 1659 1660 /* Move PC forward a little and continue executing */ 1661 instruction_pointer(regs) += 4; 1662 1663 return NOTIFY_STOP; 1664 } 1665 1666 static struct notifier_block kvm_mips_csr_die_notifier = { 1667 .notifier_call = kvm_mips_csr_die_notify, 1668 }; 1669 1670 static int __init kvm_mips_init(void) 1671 { 1672 int ret; 1673 1674 ret = kvm_mips_entry_setup(); 1675 if (ret) 1676 return ret; 1677 1678 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); 1679 1680 if (ret) 1681 return ret; 1682 1683 register_die_notifier(&kvm_mips_csr_die_notifier); 1684 1685 return 0; 1686 } 1687 1688 static void __exit kvm_mips_exit(void) 1689 { 1690 kvm_exit(); 1691 1692 unregister_die_notifier(&kvm_mips_csr_die_notifier); 1693 } 1694 1695 module_init(kvm_mips_init); 1696 module_exit(kvm_mips_exit); 1697 1698 EXPORT_TRACEPOINT_SYMBOL(kvm_exit); 1699