1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 27 #include <asm/bootinfo.h> 28 #include <asm/branch.h> 29 #include <asm/break.h> 30 #include <asm/cpu.h> 31 #include <asm/dsp.h> 32 #include <asm/fpu.h> 33 #include <asm/mipsregs.h> 34 #include <asm/mipsmtregs.h> 35 #include <asm/module.h> 36 #include <asm/pgtable.h> 37 #include <asm/ptrace.h> 38 #include <asm/sections.h> 39 #include <asm/system.h> 40 #include <asm/tlbdebug.h> 41 #include <asm/traps.h> 42 #include <asm/uaccess.h> 43 #include <asm/mmu_context.h> 44 #include <asm/types.h> 45 #include <asm/stacktrace.h> 46 47 extern asmlinkage void handle_int(void); 48 extern asmlinkage void handle_tlbm(void); 49 extern asmlinkage void handle_tlbl(void); 50 extern asmlinkage void handle_tlbs(void); 51 extern asmlinkage void handle_adel(void); 52 extern asmlinkage void handle_ades(void); 53 extern asmlinkage void handle_ibe(void); 54 extern asmlinkage void handle_dbe(void); 55 extern asmlinkage void handle_sys(void); 56 extern asmlinkage void handle_bp(void); 57 extern asmlinkage void handle_ri(void); 58 extern asmlinkage void handle_ri_rdhwr_vivt(void); 59 extern asmlinkage void handle_ri_rdhwr(void); 60 extern asmlinkage void handle_cpu(void); 61 extern asmlinkage void handle_ov(void); 62 extern asmlinkage void handle_tr(void); 63 extern asmlinkage void handle_fpe(void); 64 extern asmlinkage void handle_mdmx(void); 65 extern asmlinkage void handle_watch(void); 66 extern asmlinkage void handle_mt(void); 67 extern asmlinkage void handle_dsp(void); 68 extern asmlinkage void handle_mcheck(void); 69 extern asmlinkage void handle_reserved(void); 70 71 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 72 struct mips_fpu_struct *ctx, int has_fpu); 73 74 void (*board_watchpoint_handler)(struct pt_regs *regs); 75 void (*board_be_init)(void); 76 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 77 void (*board_nmi_handler_setup)(void); 78 void (*board_ejtag_handler_setup)(void); 79 void (*board_bind_eic_interrupt)(int irq, int regset); 80 81 82 static void show_raw_backtrace(unsigned long reg29) 83 { 84 unsigned long *sp = (unsigned long *)(reg29 & ~3); 85 unsigned long addr; 86 87 printk("Call Trace:"); 88 #ifdef CONFIG_KALLSYMS 89 printk("\n"); 90 #endif 91 #define IS_KVA01(a) ((((unsigned int)a) & 0xc0000000) == 0x80000000) 92 if (IS_KVA01(sp)) { 93 while (!kstack_end(sp)) { 94 addr = *sp++; 95 if (__kernel_text_address(addr)) 96 print_ip_sym(addr); 97 } 98 printk("\n"); 99 } 100 } 101 102 #ifdef CONFIG_KALLSYMS 103 int raw_show_trace; 104 static int __init set_raw_show_trace(char *str) 105 { 106 raw_show_trace = 1; 107 return 1; 108 } 109 __setup("raw_show_trace", set_raw_show_trace); 110 #endif 111 112 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 113 { 114 unsigned long sp = regs->regs[29]; 115 unsigned long ra = regs->regs[31]; 116 unsigned long pc = regs->cp0_epc; 117 118 if (raw_show_trace || !__kernel_text_address(pc)) { 119 show_raw_backtrace(sp); 120 return; 121 } 122 printk("Call Trace:\n"); 123 do { 124 print_ip_sym(pc); 125 pc = unwind_stack(task, &sp, pc, &ra); 126 } while (pc); 127 printk("\n"); 128 } 129 130 /* 131 * This routine abuses get_user()/put_user() to reference pointers 132 * with at least a bit of error checking ... 133 */ 134 static void show_stacktrace(struct task_struct *task, 135 const struct pt_regs *regs) 136 { 137 const int field = 2 * sizeof(unsigned long); 138 long stackdata; 139 int i; 140 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 141 142 printk("Stack :"); 143 i = 0; 144 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 145 if (i && ((i % (64 / field)) == 0)) 146 printk("\n "); 147 if (i > 39) { 148 printk(" ..."); 149 break; 150 } 151 152 if (__get_user(stackdata, sp++)) { 153 printk(" (Bad stack address)"); 154 break; 155 } 156 157 printk(" %0*lx", field, stackdata); 158 i++; 159 } 160 printk("\n"); 161 show_backtrace(task, regs); 162 } 163 164 void show_stack(struct task_struct *task, unsigned long *sp) 165 { 166 struct pt_regs regs; 167 if (sp) { 168 regs.regs[29] = (unsigned long)sp; 169 regs.regs[31] = 0; 170 regs.cp0_epc = 0; 171 } else { 172 if (task && task != current) { 173 regs.regs[29] = task->thread.reg29; 174 regs.regs[31] = 0; 175 regs.cp0_epc = task->thread.reg31; 176 } else { 177 prepare_frametrace(®s); 178 } 179 } 180 show_stacktrace(task, ®s); 181 } 182 183 /* 184 * The architecture-independent dump_stack generator 185 */ 186 void dump_stack(void) 187 { 188 struct pt_regs regs; 189 190 prepare_frametrace(®s); 191 show_backtrace(current, ®s); 192 } 193 194 EXPORT_SYMBOL(dump_stack); 195 196 static void show_code(unsigned int __user *pc) 197 { 198 long i; 199 unsigned short __user *pc16 = NULL; 200 201 printk("\nCode:"); 202 203 if ((unsigned long)pc & 1) 204 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 205 for(i = -3 ; i < 6 ; i++) { 206 unsigned int insn; 207 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 208 printk(" (Bad address in epc)\n"); 209 break; 210 } 211 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 212 } 213 } 214 215 static void __show_regs(const struct pt_regs *regs) 216 { 217 const int field = 2 * sizeof(unsigned long); 218 unsigned int cause = regs->cp0_cause; 219 int i; 220 221 printk("Cpu %d\n", smp_processor_id()); 222 223 /* 224 * Saved main processor registers 225 */ 226 for (i = 0; i < 32; ) { 227 if ((i % 4) == 0) 228 printk("$%2d :", i); 229 if (i == 0) 230 printk(" %0*lx", field, 0UL); 231 else if (i == 26 || i == 27) 232 printk(" %*s", field, ""); 233 else 234 printk(" %0*lx", field, regs->regs[i]); 235 236 i++; 237 if ((i % 4) == 0) 238 printk("\n"); 239 } 240 241 #ifdef CONFIG_CPU_HAS_SMARTMIPS 242 printk("Acx : %0*lx\n", field, regs->acx); 243 #endif 244 printk("Hi : %0*lx\n", field, regs->hi); 245 printk("Lo : %0*lx\n", field, regs->lo); 246 247 /* 248 * Saved cp0 registers 249 */ 250 printk("epc : %0*lx ", field, regs->cp0_epc); 251 print_symbol("%s ", regs->cp0_epc); 252 printk(" %s\n", print_tainted()); 253 printk("ra : %0*lx ", field, regs->regs[31]); 254 print_symbol("%s\n", regs->regs[31]); 255 256 printk("Status: %08x ", (uint32_t) regs->cp0_status); 257 258 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 259 if (regs->cp0_status & ST0_KUO) 260 printk("KUo "); 261 if (regs->cp0_status & ST0_IEO) 262 printk("IEo "); 263 if (regs->cp0_status & ST0_KUP) 264 printk("KUp "); 265 if (regs->cp0_status & ST0_IEP) 266 printk("IEp "); 267 if (regs->cp0_status & ST0_KUC) 268 printk("KUc "); 269 if (regs->cp0_status & ST0_IEC) 270 printk("IEc "); 271 } else { 272 if (regs->cp0_status & ST0_KX) 273 printk("KX "); 274 if (regs->cp0_status & ST0_SX) 275 printk("SX "); 276 if (regs->cp0_status & ST0_UX) 277 printk("UX "); 278 switch (regs->cp0_status & ST0_KSU) { 279 case KSU_USER: 280 printk("USER "); 281 break; 282 case KSU_SUPERVISOR: 283 printk("SUPERVISOR "); 284 break; 285 case KSU_KERNEL: 286 printk("KERNEL "); 287 break; 288 default: 289 printk("BAD_MODE "); 290 break; 291 } 292 if (regs->cp0_status & ST0_ERL) 293 printk("ERL "); 294 if (regs->cp0_status & ST0_EXL) 295 printk("EXL "); 296 if (regs->cp0_status & ST0_IE) 297 printk("IE "); 298 } 299 printk("\n"); 300 301 printk("Cause : %08x\n", cause); 302 303 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 304 if (1 <= cause && cause <= 5) 305 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 306 307 printk("PrId : %08x (%s)\n", read_c0_prid(), 308 cpu_name_string()); 309 } 310 311 /* 312 * FIXME: really the generic show_regs should take a const pointer argument. 313 */ 314 void show_regs(struct pt_regs *regs) 315 { 316 __show_regs((struct pt_regs *)regs); 317 } 318 319 void show_registers(const struct pt_regs *regs) 320 { 321 const int field = 2 * sizeof(unsigned long); 322 323 __show_regs(regs); 324 print_modules(); 325 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 326 current->comm, current->pid, current_thread_info(), current, 327 field, current_thread_info()->tp_value); 328 if (cpu_has_userlocal) { 329 unsigned long tls; 330 331 tls = read_c0_userlocal(); 332 if (tls != current_thread_info()->tp_value) 333 printk("*HwTLS: %0*lx\n", field, tls); 334 } 335 336 show_stacktrace(current, regs); 337 show_code((unsigned int __user *) regs->cp0_epc); 338 printk("\n"); 339 } 340 341 static DEFINE_SPINLOCK(die_lock); 342 343 void __noreturn die(const char * str, const struct pt_regs * regs) 344 { 345 static int die_counter; 346 #ifdef CONFIG_MIPS_MT_SMTC 347 unsigned long dvpret = dvpe(); 348 #endif /* CONFIG_MIPS_MT_SMTC */ 349 350 console_verbose(); 351 spin_lock_irq(&die_lock); 352 bust_spinlocks(1); 353 #ifdef CONFIG_MIPS_MT_SMTC 354 mips_mt_regdump(dvpret); 355 #endif /* CONFIG_MIPS_MT_SMTC */ 356 printk("%s[#%d]:\n", str, ++die_counter); 357 show_registers(regs); 358 add_taint(TAINT_DIE); 359 spin_unlock_irq(&die_lock); 360 361 if (in_interrupt()) 362 panic("Fatal exception in interrupt"); 363 364 if (panic_on_oops) { 365 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 366 ssleep(5); 367 panic("Fatal exception"); 368 } 369 370 do_exit(SIGSEGV); 371 } 372 373 extern const struct exception_table_entry __start___dbe_table[]; 374 extern const struct exception_table_entry __stop___dbe_table[]; 375 376 __asm__( 377 " .section __dbe_table, \"a\"\n" 378 " .previous \n"); 379 380 /* Given an address, look for it in the exception tables. */ 381 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 382 { 383 const struct exception_table_entry *e; 384 385 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 386 if (!e) 387 e = search_module_dbetables(addr); 388 return e; 389 } 390 391 asmlinkage void do_be(struct pt_regs *regs) 392 { 393 const int field = 2 * sizeof(unsigned long); 394 const struct exception_table_entry *fixup = NULL; 395 int data = regs->cp0_cause & 4; 396 int action = MIPS_BE_FATAL; 397 398 /* XXX For now. Fixme, this searches the wrong table ... */ 399 if (data && !user_mode(regs)) 400 fixup = search_dbe_tables(exception_epc(regs)); 401 402 if (fixup) 403 action = MIPS_BE_FIXUP; 404 405 if (board_be_handler) 406 action = board_be_handler(regs, fixup != NULL); 407 408 switch (action) { 409 case MIPS_BE_DISCARD: 410 return; 411 case MIPS_BE_FIXUP: 412 if (fixup) { 413 regs->cp0_epc = fixup->nextinsn; 414 return; 415 } 416 break; 417 default: 418 break; 419 } 420 421 /* 422 * Assume it would be too dangerous to continue ... 423 */ 424 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 425 data ? "Data" : "Instruction", 426 field, regs->cp0_epc, field, regs->regs[31]); 427 die_if_kernel("Oops", regs); 428 force_sig(SIGBUS, current); 429 } 430 431 /* 432 * ll/sc, rdhwr, sync emulation 433 */ 434 435 #define OPCODE 0xfc000000 436 #define BASE 0x03e00000 437 #define RT 0x001f0000 438 #define OFFSET 0x0000ffff 439 #define LL 0xc0000000 440 #define SC 0xe0000000 441 #define SPEC0 0x00000000 442 #define SPEC3 0x7c000000 443 #define RD 0x0000f800 444 #define FUNC 0x0000003f 445 #define SYNC 0x0000000f 446 #define RDHWR 0x0000003b 447 448 /* 449 * The ll_bit is cleared by r*_switch.S 450 */ 451 452 unsigned long ll_bit; 453 454 static struct task_struct *ll_task = NULL; 455 456 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 457 { 458 unsigned long value, __user *vaddr; 459 long offset; 460 461 /* 462 * analyse the ll instruction that just caused a ri exception 463 * and put the referenced address to addr. 464 */ 465 466 /* sign extend offset */ 467 offset = opcode & OFFSET; 468 offset <<= 16; 469 offset >>= 16; 470 471 vaddr = (unsigned long __user *) 472 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 473 474 if ((unsigned long)vaddr & 3) 475 return SIGBUS; 476 if (get_user(value, vaddr)) 477 return SIGSEGV; 478 479 preempt_disable(); 480 481 if (ll_task == NULL || ll_task == current) { 482 ll_bit = 1; 483 } else { 484 ll_bit = 0; 485 } 486 ll_task = current; 487 488 preempt_enable(); 489 490 regs->regs[(opcode & RT) >> 16] = value; 491 492 return 0; 493 } 494 495 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 496 { 497 unsigned long __user *vaddr; 498 unsigned long reg; 499 long offset; 500 501 /* 502 * analyse the sc instruction that just caused a ri exception 503 * and put the referenced address to addr. 504 */ 505 506 /* sign extend offset */ 507 offset = opcode & OFFSET; 508 offset <<= 16; 509 offset >>= 16; 510 511 vaddr = (unsigned long __user *) 512 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 513 reg = (opcode & RT) >> 16; 514 515 if ((unsigned long)vaddr & 3) 516 return SIGBUS; 517 518 preempt_disable(); 519 520 if (ll_bit == 0 || ll_task != current) { 521 regs->regs[reg] = 0; 522 preempt_enable(); 523 return 0; 524 } 525 526 preempt_enable(); 527 528 if (put_user(regs->regs[reg], vaddr)) 529 return SIGSEGV; 530 531 regs->regs[reg] = 1; 532 533 return 0; 534 } 535 536 /* 537 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 538 * opcodes are supposed to result in coprocessor unusable exceptions if 539 * executed on ll/sc-less processors. That's the theory. In practice a 540 * few processors such as NEC's VR4100 throw reserved instruction exceptions 541 * instead, so we're doing the emulation thing in both exception handlers. 542 */ 543 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 544 { 545 if ((opcode & OPCODE) == LL) 546 return simulate_ll(regs, opcode); 547 if ((opcode & OPCODE) == SC) 548 return simulate_sc(regs, opcode); 549 550 return -1; /* Must be something else ... */ 551 } 552 553 /* 554 * Simulate trapping 'rdhwr' instructions to provide user accessible 555 * registers not implemented in hardware. 556 */ 557 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 558 { 559 struct thread_info *ti = task_thread_info(current); 560 561 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 562 int rd = (opcode & RD) >> 11; 563 int rt = (opcode & RT) >> 16; 564 switch (rd) { 565 case 0: /* CPU number */ 566 regs->regs[rt] = smp_processor_id(); 567 return 0; 568 case 1: /* SYNCI length */ 569 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 570 current_cpu_data.icache.linesz); 571 return 0; 572 case 2: /* Read count register */ 573 regs->regs[rt] = read_c0_count(); 574 return 0; 575 case 3: /* Count register resolution */ 576 switch (current_cpu_data.cputype) { 577 case CPU_20KC: 578 case CPU_25KF: 579 regs->regs[rt] = 1; 580 break; 581 default: 582 regs->regs[rt] = 2; 583 } 584 return 0; 585 case 29: 586 regs->regs[rt] = ti->tp_value; 587 return 0; 588 default: 589 return -1; 590 } 591 } 592 593 /* Not ours. */ 594 return -1; 595 } 596 597 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 598 { 599 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 600 return 0; 601 602 return -1; /* Must be something else ... */ 603 } 604 605 asmlinkage void do_ov(struct pt_regs *regs) 606 { 607 siginfo_t info; 608 609 die_if_kernel("Integer overflow", regs); 610 611 info.si_code = FPE_INTOVF; 612 info.si_signo = SIGFPE; 613 info.si_errno = 0; 614 info.si_addr = (void __user *) regs->cp0_epc; 615 force_sig_info(SIGFPE, &info, current); 616 } 617 618 /* 619 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 620 */ 621 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 622 { 623 siginfo_t info; 624 625 die_if_kernel("FP exception in kernel code", regs); 626 627 if (fcr31 & FPU_CSR_UNI_X) { 628 int sig; 629 630 /* 631 * Unimplemented operation exception. If we've got the full 632 * software emulator on-board, let's use it... 633 * 634 * Force FPU to dump state into task/thread context. We're 635 * moving a lot of data here for what is probably a single 636 * instruction, but the alternative is to pre-decode the FP 637 * register operands before invoking the emulator, which seems 638 * a bit extreme for what should be an infrequent event. 639 */ 640 /* Ensure 'resume' not overwrite saved fp context again. */ 641 lose_fpu(1); 642 643 /* Run the emulator */ 644 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 645 646 /* 647 * We can't allow the emulated instruction to leave any of 648 * the cause bit set in $fcr31. 649 */ 650 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 651 652 /* Restore the hardware register state */ 653 own_fpu(1); /* Using the FPU again. */ 654 655 /* If something went wrong, signal */ 656 if (sig) 657 force_sig(sig, current); 658 659 return; 660 } else if (fcr31 & FPU_CSR_INV_X) 661 info.si_code = FPE_FLTINV; 662 else if (fcr31 & FPU_CSR_DIV_X) 663 info.si_code = FPE_FLTDIV; 664 else if (fcr31 & FPU_CSR_OVF_X) 665 info.si_code = FPE_FLTOVF; 666 else if (fcr31 & FPU_CSR_UDF_X) 667 info.si_code = FPE_FLTUND; 668 else if (fcr31 & FPU_CSR_INE_X) 669 info.si_code = FPE_FLTRES; 670 else 671 info.si_code = __SI_FAULT; 672 info.si_signo = SIGFPE; 673 info.si_errno = 0; 674 info.si_addr = (void __user *) regs->cp0_epc; 675 force_sig_info(SIGFPE, &info, current); 676 } 677 678 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 679 const char *str) 680 { 681 siginfo_t info; 682 char b[40]; 683 684 /* 685 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 686 * insns, even for trap and break codes that indicate arithmetic 687 * failures. Weird ... 688 * But should we continue the brokenness??? --macro 689 */ 690 switch (code) { 691 case BRK_OVERFLOW: 692 case BRK_DIVZERO: 693 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 694 die_if_kernel(b, regs); 695 if (code == BRK_DIVZERO) 696 info.si_code = FPE_INTDIV; 697 else 698 info.si_code = FPE_INTOVF; 699 info.si_signo = SIGFPE; 700 info.si_errno = 0; 701 info.si_addr = (void __user *) regs->cp0_epc; 702 force_sig_info(SIGFPE, &info, current); 703 break; 704 case BRK_BUG: 705 die_if_kernel("Kernel bug detected", regs); 706 force_sig(SIGTRAP, current); 707 break; 708 default: 709 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 710 die_if_kernel(b, regs); 711 force_sig(SIGTRAP, current); 712 } 713 } 714 715 asmlinkage void do_bp(struct pt_regs *regs) 716 { 717 unsigned int opcode, bcode; 718 719 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 720 goto out_sigsegv; 721 722 /* 723 * There is the ancient bug in the MIPS assemblers that the break 724 * code starts left to bit 16 instead to bit 6 in the opcode. 725 * Gas is bug-compatible, but not always, grrr... 726 * We handle both cases with a simple heuristics. --macro 727 */ 728 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 729 if (bcode >= (1 << 10)) 730 bcode >>= 10; 731 732 do_trap_or_bp(regs, bcode, "Break"); 733 return; 734 735 out_sigsegv: 736 force_sig(SIGSEGV, current); 737 } 738 739 asmlinkage void do_tr(struct pt_regs *regs) 740 { 741 unsigned int opcode, tcode = 0; 742 743 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 744 goto out_sigsegv; 745 746 /* Immediate versions don't provide a code. */ 747 if (!(opcode & OPCODE)) 748 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 749 750 do_trap_or_bp(regs, tcode, "Trap"); 751 return; 752 753 out_sigsegv: 754 force_sig(SIGSEGV, current); 755 } 756 757 asmlinkage void do_ri(struct pt_regs *regs) 758 { 759 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 760 unsigned long old_epc = regs->cp0_epc; 761 unsigned int opcode = 0; 762 int status = -1; 763 764 die_if_kernel("Reserved instruction in kernel code", regs); 765 766 if (unlikely(compute_return_epc(regs) < 0)) 767 return; 768 769 if (unlikely(get_user(opcode, epc) < 0)) 770 status = SIGSEGV; 771 772 if (!cpu_has_llsc && status < 0) 773 status = simulate_llsc(regs, opcode); 774 775 if (status < 0) 776 status = simulate_rdhwr(regs, opcode); 777 778 if (status < 0) 779 status = simulate_sync(regs, opcode); 780 781 if (status < 0) 782 status = SIGILL; 783 784 if (unlikely(status > 0)) { 785 regs->cp0_epc = old_epc; /* Undo skip-over. */ 786 force_sig(status, current); 787 } 788 } 789 790 /* 791 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 792 * emulated more than some threshold number of instructions, force migration to 793 * a "CPU" that has FP support. 794 */ 795 static void mt_ase_fp_affinity(void) 796 { 797 #ifdef CONFIG_MIPS_MT_FPAFF 798 if (mt_fpemul_threshold > 0 && 799 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 800 /* 801 * If there's no FPU present, or if the application has already 802 * restricted the allowed set to exclude any CPUs with FPUs, 803 * we'll skip the procedure. 804 */ 805 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 806 cpumask_t tmask; 807 808 cpus_and(tmask, current->thread.user_cpus_allowed, 809 mt_fpu_cpumask); 810 set_cpus_allowed(current, tmask); 811 set_thread_flag(TIF_FPUBOUND); 812 } 813 } 814 #endif /* CONFIG_MIPS_MT_FPAFF */ 815 } 816 817 asmlinkage void do_cpu(struct pt_regs *regs) 818 { 819 unsigned int __user *epc; 820 unsigned long old_epc; 821 unsigned int opcode; 822 unsigned int cpid; 823 int status; 824 825 die_if_kernel("do_cpu invoked from kernel context!", regs); 826 827 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 828 829 switch (cpid) { 830 case 0: 831 epc = (unsigned int __user *)exception_epc(regs); 832 old_epc = regs->cp0_epc; 833 opcode = 0; 834 status = -1; 835 836 if (unlikely(compute_return_epc(regs) < 0)) 837 return; 838 839 if (unlikely(get_user(opcode, epc) < 0)) 840 status = SIGSEGV; 841 842 if (!cpu_has_llsc && status < 0) 843 status = simulate_llsc(regs, opcode); 844 845 if (status < 0) 846 status = simulate_rdhwr(regs, opcode); 847 848 if (status < 0) 849 status = SIGILL; 850 851 if (unlikely(status > 0)) { 852 regs->cp0_epc = old_epc; /* Undo skip-over. */ 853 force_sig(status, current); 854 } 855 856 return; 857 858 case 1: 859 if (used_math()) /* Using the FPU again. */ 860 own_fpu(1); 861 else { /* First time FPU user. */ 862 init_fpu(); 863 set_used_math(); 864 } 865 866 if (!raw_cpu_has_fpu) { 867 int sig; 868 sig = fpu_emulator_cop1Handler(regs, 869 ¤t->thread.fpu, 0); 870 if (sig) 871 force_sig(sig, current); 872 else 873 mt_ase_fp_affinity(); 874 } 875 876 return; 877 878 case 2: 879 case 3: 880 break; 881 } 882 883 force_sig(SIGILL, current); 884 } 885 886 asmlinkage void do_mdmx(struct pt_regs *regs) 887 { 888 force_sig(SIGILL, current); 889 } 890 891 asmlinkage void do_watch(struct pt_regs *regs) 892 { 893 if (board_watchpoint_handler) { 894 (*board_watchpoint_handler)(regs); 895 return; 896 } 897 898 /* 899 * We use the watch exception where available to detect stack 900 * overflows. 901 */ 902 dump_tlb_all(); 903 show_regs(regs); 904 panic("Caught WATCH exception - probably caused by stack overflow."); 905 } 906 907 asmlinkage void do_mcheck(struct pt_regs *regs) 908 { 909 const int field = 2 * sizeof(unsigned long); 910 int multi_match = regs->cp0_status & ST0_TS; 911 912 show_regs(regs); 913 914 if (multi_match) { 915 printk("Index : %0x\n", read_c0_index()); 916 printk("Pagemask: %0x\n", read_c0_pagemask()); 917 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 918 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 919 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 920 printk("\n"); 921 dump_tlb_all(); 922 } 923 924 show_code((unsigned int __user *) regs->cp0_epc); 925 926 /* 927 * Some chips may have other causes of machine check (e.g. SB1 928 * graduation timer) 929 */ 930 panic("Caught Machine Check exception - %scaused by multiple " 931 "matching entries in the TLB.", 932 (multi_match) ? "" : "not "); 933 } 934 935 asmlinkage void do_mt(struct pt_regs *regs) 936 { 937 int subcode; 938 939 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 940 >> VPECONTROL_EXCPT_SHIFT; 941 switch (subcode) { 942 case 0: 943 printk(KERN_DEBUG "Thread Underflow\n"); 944 break; 945 case 1: 946 printk(KERN_DEBUG "Thread Overflow\n"); 947 break; 948 case 2: 949 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 950 break; 951 case 3: 952 printk(KERN_DEBUG "Gating Storage Exception\n"); 953 break; 954 case 4: 955 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 956 break; 957 case 5: 958 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 959 break; 960 default: 961 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 962 subcode); 963 break; 964 } 965 die_if_kernel("MIPS MT Thread exception in kernel", regs); 966 967 force_sig(SIGILL, current); 968 } 969 970 971 asmlinkage void do_dsp(struct pt_regs *regs) 972 { 973 if (cpu_has_dsp) 974 panic("Unexpected DSP exception\n"); 975 976 force_sig(SIGILL, current); 977 } 978 979 asmlinkage void do_reserved(struct pt_regs *regs) 980 { 981 /* 982 * Game over - no way to handle this if it ever occurs. Most probably 983 * caused by a new unknown cpu type or after another deadly 984 * hard/software error. 985 */ 986 show_regs(regs); 987 panic("Caught reserved exception %ld - should not happen.", 988 (regs->cp0_cause & 0x7f) >> 2); 989 } 990 991 static int __initdata l1parity = 1; 992 static int __init nol1parity(char *s) 993 { 994 l1parity = 0; 995 return 1; 996 } 997 __setup("nol1par", nol1parity); 998 static int __initdata l2parity = 1; 999 static int __init nol2parity(char *s) 1000 { 1001 l2parity = 0; 1002 return 1; 1003 } 1004 __setup("nol2par", nol2parity); 1005 1006 /* 1007 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1008 * it different ways. 1009 */ 1010 static inline void parity_protection_init(void) 1011 { 1012 switch (current_cpu_type()) { 1013 case CPU_24K: 1014 case CPU_34K: 1015 case CPU_74K: 1016 case CPU_1004K: 1017 { 1018 #define ERRCTL_PE 0x80000000 1019 #define ERRCTL_L2P 0x00800000 1020 unsigned long errctl; 1021 unsigned int l1parity_present, l2parity_present; 1022 1023 errctl = read_c0_ecc(); 1024 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1025 1026 /* probe L1 parity support */ 1027 write_c0_ecc(errctl | ERRCTL_PE); 1028 back_to_back_c0_hazard(); 1029 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1030 1031 /* probe L2 parity support */ 1032 write_c0_ecc(errctl|ERRCTL_L2P); 1033 back_to_back_c0_hazard(); 1034 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1035 1036 if (l1parity_present && l2parity_present) { 1037 if (l1parity) 1038 errctl |= ERRCTL_PE; 1039 if (l1parity ^ l2parity) 1040 errctl |= ERRCTL_L2P; 1041 } else if (l1parity_present) { 1042 if (l1parity) 1043 errctl |= ERRCTL_PE; 1044 } else if (l2parity_present) { 1045 if (l2parity) 1046 errctl |= ERRCTL_L2P; 1047 } else { 1048 /* No parity available */ 1049 } 1050 1051 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1052 1053 write_c0_ecc(errctl); 1054 back_to_back_c0_hazard(); 1055 errctl = read_c0_ecc(); 1056 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1057 1058 if (l1parity_present) 1059 printk(KERN_INFO "Cache parity protection %sabled\n", 1060 (errctl & ERRCTL_PE) ? "en" : "dis"); 1061 1062 if (l2parity_present) { 1063 if (l1parity_present && l1parity) 1064 errctl ^= ERRCTL_L2P; 1065 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1066 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1067 } 1068 } 1069 break; 1070 1071 case CPU_5KC: 1072 write_c0_ecc(0x80000000); 1073 back_to_back_c0_hazard(); 1074 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1075 printk(KERN_INFO "Cache parity protection %sabled\n", 1076 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1077 break; 1078 case CPU_20KC: 1079 case CPU_25KF: 1080 /* Clear the DE bit (bit 16) in the c0_status register. */ 1081 printk(KERN_INFO "Enable cache parity protection for " 1082 "MIPS 20KC/25KF CPUs.\n"); 1083 clear_c0_status(ST0_DE); 1084 break; 1085 default: 1086 break; 1087 } 1088 } 1089 1090 asmlinkage void cache_parity_error(void) 1091 { 1092 const int field = 2 * sizeof(unsigned long); 1093 unsigned int reg_val; 1094 1095 /* For the moment, report the problem and hang. */ 1096 printk("Cache error exception:\n"); 1097 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1098 reg_val = read_c0_cacheerr(); 1099 printk("c0_cacheerr == %08x\n", reg_val); 1100 1101 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1102 reg_val & (1<<30) ? "secondary" : "primary", 1103 reg_val & (1<<31) ? "data" : "insn"); 1104 printk("Error bits: %s%s%s%s%s%s%s\n", 1105 reg_val & (1<<29) ? "ED " : "", 1106 reg_val & (1<<28) ? "ET " : "", 1107 reg_val & (1<<26) ? "EE " : "", 1108 reg_val & (1<<25) ? "EB " : "", 1109 reg_val & (1<<24) ? "EI " : "", 1110 reg_val & (1<<23) ? "E1 " : "", 1111 reg_val & (1<<22) ? "E0 " : ""); 1112 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1113 1114 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1115 if (reg_val & (1<<22)) 1116 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1117 1118 if (reg_val & (1<<23)) 1119 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1120 #endif 1121 1122 panic("Can't handle the cache error!"); 1123 } 1124 1125 /* 1126 * SDBBP EJTAG debug exception handler. 1127 * We skip the instruction and return to the next instruction. 1128 */ 1129 void ejtag_exception_handler(struct pt_regs *regs) 1130 { 1131 const int field = 2 * sizeof(unsigned long); 1132 unsigned long depc, old_epc; 1133 unsigned int debug; 1134 1135 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1136 depc = read_c0_depc(); 1137 debug = read_c0_debug(); 1138 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1139 if (debug & 0x80000000) { 1140 /* 1141 * In branch delay slot. 1142 * We cheat a little bit here and use EPC to calculate the 1143 * debug return address (DEPC). EPC is restored after the 1144 * calculation. 1145 */ 1146 old_epc = regs->cp0_epc; 1147 regs->cp0_epc = depc; 1148 __compute_return_epc(regs); 1149 depc = regs->cp0_epc; 1150 regs->cp0_epc = old_epc; 1151 } else 1152 depc += 4; 1153 write_c0_depc(depc); 1154 1155 #if 0 1156 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1157 write_c0_debug(debug | 0x100); 1158 #endif 1159 } 1160 1161 /* 1162 * NMI exception handler. 1163 */ 1164 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1165 { 1166 bust_spinlocks(1); 1167 printk("NMI taken!!!!\n"); 1168 die("NMI", regs); 1169 } 1170 1171 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1172 1173 unsigned long ebase; 1174 unsigned long exception_handlers[32]; 1175 unsigned long vi_handlers[64]; 1176 1177 /* 1178 * As a side effect of the way this is implemented we're limited 1179 * to interrupt handlers in the address range from 1180 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1181 */ 1182 void *set_except_vector(int n, void *addr) 1183 { 1184 unsigned long handler = (unsigned long) addr; 1185 unsigned long old_handler = exception_handlers[n]; 1186 1187 exception_handlers[n] = handler; 1188 if (n == 0 && cpu_has_divec) { 1189 *(u32 *)(ebase + 0x200) = 0x08000000 | 1190 (0x03ffffff & (handler >> 2)); 1191 flush_icache_range(ebase + 0x200, ebase + 0x204); 1192 } 1193 return (void *)old_handler; 1194 } 1195 1196 static asmlinkage void do_default_vi(void) 1197 { 1198 show_regs(get_irq_regs()); 1199 panic("Caught unexpected vectored interrupt."); 1200 } 1201 1202 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1203 { 1204 unsigned long handler; 1205 unsigned long old_handler = vi_handlers[n]; 1206 int srssets = current_cpu_data.srsets; 1207 u32 *w; 1208 unsigned char *b; 1209 1210 if (!cpu_has_veic && !cpu_has_vint) 1211 BUG(); 1212 1213 if (addr == NULL) { 1214 handler = (unsigned long) do_default_vi; 1215 srs = 0; 1216 } else 1217 handler = (unsigned long) addr; 1218 vi_handlers[n] = (unsigned long) addr; 1219 1220 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1221 1222 if (srs >= srssets) 1223 panic("Shadow register set %d not supported", srs); 1224 1225 if (cpu_has_veic) { 1226 if (board_bind_eic_interrupt) 1227 board_bind_eic_interrupt(n, srs); 1228 } else if (cpu_has_vint) { 1229 /* SRSMap is only defined if shadow sets are implemented */ 1230 if (srssets > 1) 1231 change_c0_srsmap(0xf << n*4, srs << n*4); 1232 } 1233 1234 if (srs == 0) { 1235 /* 1236 * If no shadow set is selected then use the default handler 1237 * that does normal register saving and a standard interrupt exit 1238 */ 1239 1240 extern char except_vec_vi, except_vec_vi_lui; 1241 extern char except_vec_vi_ori, except_vec_vi_end; 1242 #ifdef CONFIG_MIPS_MT_SMTC 1243 /* 1244 * We need to provide the SMTC vectored interrupt handler 1245 * not only with the address of the handler, but with the 1246 * Status.IM bit to be masked before going there. 1247 */ 1248 extern char except_vec_vi_mori; 1249 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1250 #endif /* CONFIG_MIPS_MT_SMTC */ 1251 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1252 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1253 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1254 1255 if (handler_len > VECTORSPACING) { 1256 /* 1257 * Sigh... panicing won't help as the console 1258 * is probably not configured :( 1259 */ 1260 panic("VECTORSPACING too small"); 1261 } 1262 1263 memcpy(b, &except_vec_vi, handler_len); 1264 #ifdef CONFIG_MIPS_MT_SMTC 1265 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1266 1267 w = (u32 *)(b + mori_offset); 1268 *w = (*w & 0xffff0000) | (0x100 << n); 1269 #endif /* CONFIG_MIPS_MT_SMTC */ 1270 w = (u32 *)(b + lui_offset); 1271 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1272 w = (u32 *)(b + ori_offset); 1273 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1274 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1275 } 1276 else { 1277 /* 1278 * In other cases jump directly to the interrupt handler 1279 * 1280 * It is the handlers responsibility to save registers if required 1281 * (eg hi/lo) and return from the exception using "eret" 1282 */ 1283 w = (u32 *)b; 1284 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1285 *w = 0; 1286 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1287 } 1288 1289 return (void *)old_handler; 1290 } 1291 1292 void *set_vi_handler(int n, vi_handler_t addr) 1293 { 1294 return set_vi_srs_handler(n, addr, 0); 1295 } 1296 1297 /* 1298 * This is used by native signal handling 1299 */ 1300 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1301 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1302 1303 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1304 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1305 1306 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1307 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1308 1309 #ifdef CONFIG_SMP 1310 static int smp_save_fp_context(struct sigcontext __user *sc) 1311 { 1312 return raw_cpu_has_fpu 1313 ? _save_fp_context(sc) 1314 : fpu_emulator_save_context(sc); 1315 } 1316 1317 static int smp_restore_fp_context(struct sigcontext __user *sc) 1318 { 1319 return raw_cpu_has_fpu 1320 ? _restore_fp_context(sc) 1321 : fpu_emulator_restore_context(sc); 1322 } 1323 #endif 1324 1325 static inline void signal_init(void) 1326 { 1327 #ifdef CONFIG_SMP 1328 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1329 save_fp_context = smp_save_fp_context; 1330 restore_fp_context = smp_restore_fp_context; 1331 #else 1332 if (cpu_has_fpu) { 1333 save_fp_context = _save_fp_context; 1334 restore_fp_context = _restore_fp_context; 1335 } else { 1336 save_fp_context = fpu_emulator_save_context; 1337 restore_fp_context = fpu_emulator_restore_context; 1338 } 1339 #endif 1340 } 1341 1342 #ifdef CONFIG_MIPS32_COMPAT 1343 1344 /* 1345 * This is used by 32-bit signal stuff on the 64-bit kernel 1346 */ 1347 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1348 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1349 1350 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1351 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1352 1353 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1354 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1355 1356 static inline void signal32_init(void) 1357 { 1358 if (cpu_has_fpu) { 1359 save_fp_context32 = _save_fp_context32; 1360 restore_fp_context32 = _restore_fp_context32; 1361 } else { 1362 save_fp_context32 = fpu_emulator_save_context32; 1363 restore_fp_context32 = fpu_emulator_restore_context32; 1364 } 1365 } 1366 #endif 1367 1368 extern void cpu_cache_init(void); 1369 extern void tlb_init(void); 1370 extern void flush_tlb_handlers(void); 1371 1372 /* 1373 * Timer interrupt 1374 */ 1375 int cp0_compare_irq; 1376 1377 /* 1378 * Performance counter IRQ or -1 if shared with timer 1379 */ 1380 int cp0_perfcount_irq; 1381 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1382 1383 static int __cpuinitdata noulri; 1384 1385 static int __init ulri_disable(char *s) 1386 { 1387 pr_info("Disabling ulri\n"); 1388 noulri = 1; 1389 1390 return 1; 1391 } 1392 __setup("noulri", ulri_disable); 1393 1394 void __cpuinit per_cpu_trap_init(void) 1395 { 1396 unsigned int cpu = smp_processor_id(); 1397 unsigned int status_set = ST0_CU0; 1398 #ifdef CONFIG_MIPS_MT_SMTC 1399 int secondaryTC = 0; 1400 int bootTC = (cpu == 0); 1401 1402 /* 1403 * Only do per_cpu_trap_init() for first TC of Each VPE. 1404 * Note that this hack assumes that the SMTC init code 1405 * assigns TCs consecutively and in ascending order. 1406 */ 1407 1408 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1409 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1410 secondaryTC = 1; 1411 #endif /* CONFIG_MIPS_MT_SMTC */ 1412 1413 /* 1414 * Disable coprocessors and select 32-bit or 64-bit addressing 1415 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1416 * flag that some firmware may have left set and the TS bit (for 1417 * IP27). Set XX for ISA IV code to work. 1418 */ 1419 #ifdef CONFIG_64BIT 1420 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1421 #endif 1422 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1423 status_set |= ST0_XX; 1424 if (cpu_has_dsp) 1425 status_set |= ST0_MX; 1426 1427 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1428 status_set); 1429 1430 if (cpu_has_mips_r2) { 1431 unsigned int enable = 0x0000000f; 1432 1433 if (!noulri && cpu_has_userlocal) 1434 enable |= (1 << 29); 1435 1436 write_c0_hwrena(enable); 1437 } 1438 1439 #ifdef CONFIG_MIPS_MT_SMTC 1440 if (!secondaryTC) { 1441 #endif /* CONFIG_MIPS_MT_SMTC */ 1442 1443 if (cpu_has_veic || cpu_has_vint) { 1444 write_c0_ebase(ebase); 1445 /* Setting vector spacing enables EI/VI mode */ 1446 change_c0_intctl(0x3e0, VECTORSPACING); 1447 } 1448 if (cpu_has_divec) { 1449 if (cpu_has_mipsmt) { 1450 unsigned int vpflags = dvpe(); 1451 set_c0_cause(CAUSEF_IV); 1452 evpe(vpflags); 1453 } else 1454 set_c0_cause(CAUSEF_IV); 1455 } 1456 1457 /* 1458 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1459 * 1460 * o read IntCtl.IPTI to determine the timer interrupt 1461 * o read IntCtl.IPPCI to determine the performance counter interrupt 1462 */ 1463 if (cpu_has_mips_r2) { 1464 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1465 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1466 if (cp0_perfcount_irq == cp0_compare_irq) 1467 cp0_perfcount_irq = -1; 1468 } else { 1469 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1470 cp0_perfcount_irq = -1; 1471 } 1472 1473 #ifdef CONFIG_MIPS_MT_SMTC 1474 } 1475 #endif /* CONFIG_MIPS_MT_SMTC */ 1476 1477 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1478 TLBMISS_HANDLER_SETUP(); 1479 1480 atomic_inc(&init_mm.mm_count); 1481 current->active_mm = &init_mm; 1482 BUG_ON(current->mm); 1483 enter_lazy_tlb(&init_mm, current); 1484 1485 #ifdef CONFIG_MIPS_MT_SMTC 1486 if (bootTC) { 1487 #endif /* CONFIG_MIPS_MT_SMTC */ 1488 cpu_cache_init(); 1489 tlb_init(); 1490 #ifdef CONFIG_MIPS_MT_SMTC 1491 } else if (!secondaryTC) { 1492 /* 1493 * First TC in non-boot VPE must do subset of tlb_init() 1494 * for MMU countrol registers. 1495 */ 1496 write_c0_pagemask(PM_DEFAULT_MASK); 1497 write_c0_wired(0); 1498 } 1499 #endif /* CONFIG_MIPS_MT_SMTC */ 1500 } 1501 1502 /* Install CPU exception handler */ 1503 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1504 { 1505 memcpy((void *)(ebase + offset), addr, size); 1506 flush_icache_range(ebase + offset, ebase + offset + size); 1507 } 1508 1509 static char panic_null_cerr[] __cpuinitdata = 1510 "Trying to set NULL cache error exception handler"; 1511 1512 /* Install uncached CPU exception handler */ 1513 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1514 unsigned long size) 1515 { 1516 #ifdef CONFIG_32BIT 1517 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1518 #endif 1519 #ifdef CONFIG_64BIT 1520 unsigned long uncached_ebase = TO_UNCAC(ebase); 1521 #endif 1522 1523 if (!addr) 1524 panic(panic_null_cerr); 1525 1526 memcpy((void *)(uncached_ebase + offset), addr, size); 1527 } 1528 1529 static int __initdata rdhwr_noopt; 1530 static int __init set_rdhwr_noopt(char *str) 1531 { 1532 rdhwr_noopt = 1; 1533 return 1; 1534 } 1535 1536 __setup("rdhwr_noopt", set_rdhwr_noopt); 1537 1538 void __init trap_init(void) 1539 { 1540 extern char except_vec3_generic, except_vec3_r4000; 1541 extern char except_vec4; 1542 unsigned long i; 1543 1544 if (cpu_has_veic || cpu_has_vint) 1545 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1546 else 1547 ebase = CAC_BASE; 1548 1549 per_cpu_trap_init(); 1550 1551 /* 1552 * Copy the generic exception handlers to their final destination. 1553 * This will be overriden later as suitable for a particular 1554 * configuration. 1555 */ 1556 set_handler(0x180, &except_vec3_generic, 0x80); 1557 1558 /* 1559 * Setup default vectors 1560 */ 1561 for (i = 0; i <= 31; i++) 1562 set_except_vector(i, handle_reserved); 1563 1564 /* 1565 * Copy the EJTAG debug exception vector handler code to it's final 1566 * destination. 1567 */ 1568 if (cpu_has_ejtag && board_ejtag_handler_setup) 1569 board_ejtag_handler_setup(); 1570 1571 /* 1572 * Only some CPUs have the watch exceptions. 1573 */ 1574 if (cpu_has_watch) 1575 set_except_vector(23, handle_watch); 1576 1577 /* 1578 * Initialise interrupt handlers 1579 */ 1580 if (cpu_has_veic || cpu_has_vint) { 1581 int nvec = cpu_has_veic ? 64 : 8; 1582 for (i = 0; i < nvec; i++) 1583 set_vi_handler(i, NULL); 1584 } 1585 else if (cpu_has_divec) 1586 set_handler(0x200, &except_vec4, 0x8); 1587 1588 /* 1589 * Some CPUs can enable/disable for cache parity detection, but does 1590 * it different ways. 1591 */ 1592 parity_protection_init(); 1593 1594 /* 1595 * The Data Bus Errors / Instruction Bus Errors are signaled 1596 * by external hardware. Therefore these two exceptions 1597 * may have board specific handlers. 1598 */ 1599 if (board_be_init) 1600 board_be_init(); 1601 1602 set_except_vector(0, handle_int); 1603 set_except_vector(1, handle_tlbm); 1604 set_except_vector(2, handle_tlbl); 1605 set_except_vector(3, handle_tlbs); 1606 1607 set_except_vector(4, handle_adel); 1608 set_except_vector(5, handle_ades); 1609 1610 set_except_vector(6, handle_ibe); 1611 set_except_vector(7, handle_dbe); 1612 1613 set_except_vector(8, handle_sys); 1614 set_except_vector(9, handle_bp); 1615 set_except_vector(10, rdhwr_noopt ? handle_ri : 1616 (cpu_has_vtag_icache ? 1617 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1618 set_except_vector(11, handle_cpu); 1619 set_except_vector(12, handle_ov); 1620 set_except_vector(13, handle_tr); 1621 1622 if (current_cpu_type() == CPU_R6000 || 1623 current_cpu_type() == CPU_R6000A) { 1624 /* 1625 * The R6000 is the only R-series CPU that features a machine 1626 * check exception (similar to the R4000 cache error) and 1627 * unaligned ldc1/sdc1 exception. The handlers have not been 1628 * written yet. Well, anyway there is no R6000 machine on the 1629 * current list of targets for Linux/MIPS. 1630 * (Duh, crap, there is someone with a triple R6k machine) 1631 */ 1632 //set_except_vector(14, handle_mc); 1633 //set_except_vector(15, handle_ndc); 1634 } 1635 1636 1637 if (board_nmi_handler_setup) 1638 board_nmi_handler_setup(); 1639 1640 if (cpu_has_fpu && !cpu_has_nofpuex) 1641 set_except_vector(15, handle_fpe); 1642 1643 set_except_vector(22, handle_mdmx); 1644 1645 if (cpu_has_mcheck) 1646 set_except_vector(24, handle_mcheck); 1647 1648 if (cpu_has_mipsmt) 1649 set_except_vector(25, handle_mt); 1650 1651 set_except_vector(26, handle_dsp); 1652 1653 if (cpu_has_vce) 1654 /* Special exception: R4[04]00 uses also the divec space. */ 1655 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1656 else if (cpu_has_4kex) 1657 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1658 else 1659 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1660 1661 signal_init(); 1662 #ifdef CONFIG_MIPS32_COMPAT 1663 signal32_init(); 1664 #endif 1665 1666 flush_icache_range(ebase, ebase + 0x400); 1667 flush_tlb_handlers(); 1668 } 1669