1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/kexec.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/mm.h> 21 #include <linux/sched.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/kallsyms.h> 25 #include <linux/bootmem.h> 26 #include <linux/interrupt.h> 27 #include <linux/ptrace.h> 28 #include <linux/kgdb.h> 29 #include <linux/kdebug.h> 30 #include <linux/kprobes.h> 31 #include <linux/notifier.h> 32 #include <linux/kdb.h> 33 #include <linux/irq.h> 34 #include <linux/perf_event.h> 35 36 #include <asm/bootinfo.h> 37 #include <asm/branch.h> 38 #include <asm/break.h> 39 #include <asm/cop2.h> 40 #include <asm/cpu.h> 41 #include <asm/dsp.h> 42 #include <asm/fpu.h> 43 #include <asm/fpu_emulator.h> 44 #include <asm/mipsregs.h> 45 #include <asm/mipsmtregs.h> 46 #include <asm/module.h> 47 #include <asm/pgtable.h> 48 #include <asm/ptrace.h> 49 #include <asm/sections.h> 50 #include <asm/tlbdebug.h> 51 #include <asm/traps.h> 52 #include <asm/uaccess.h> 53 #include <asm/watch.h> 54 #include <asm/mmu_context.h> 55 #include <asm/types.h> 56 #include <asm/stacktrace.h> 57 #include <asm/uasm.h> 58 59 extern void check_wait(void); 60 extern asmlinkage void r4k_wait(void); 61 extern asmlinkage void rollback_handle_int(void); 62 extern asmlinkage void handle_int(void); 63 extern asmlinkage void handle_tlbm(void); 64 extern asmlinkage void handle_tlbl(void); 65 extern asmlinkage void handle_tlbs(void); 66 extern asmlinkage void handle_adel(void); 67 extern asmlinkage void handle_ades(void); 68 extern asmlinkage void handle_ibe(void); 69 extern asmlinkage void handle_dbe(void); 70 extern asmlinkage void handle_sys(void); 71 extern asmlinkage void handle_bp(void); 72 extern asmlinkage void handle_ri(void); 73 extern asmlinkage void handle_ri_rdhwr_vivt(void); 74 extern asmlinkage void handle_ri_rdhwr(void); 75 extern asmlinkage void handle_cpu(void); 76 extern asmlinkage void handle_ov(void); 77 extern asmlinkage void handle_tr(void); 78 extern asmlinkage void handle_fpe(void); 79 extern asmlinkage void handle_mdmx(void); 80 extern asmlinkage void handle_watch(void); 81 extern asmlinkage void handle_mt(void); 82 extern asmlinkage void handle_dsp(void); 83 extern asmlinkage void handle_mcheck(void); 84 extern asmlinkage void handle_reserved(void); 85 86 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 87 struct mips_fpu_struct *ctx, int has_fpu, 88 void *__user *fault_addr); 89 90 void (*board_be_init)(void); 91 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 92 void (*board_nmi_handler_setup)(void); 93 void (*board_ejtag_handler_setup)(void); 94 void (*board_bind_eic_interrupt)(int irq, int regset); 95 void (*board_ebase_setup)(void); 96 void __cpuinitdata(*board_cache_error_setup)(void); 97 98 static void show_raw_backtrace(unsigned long reg29) 99 { 100 unsigned long *sp = (unsigned long *)(reg29 & ~3); 101 unsigned long addr; 102 103 printk("Call Trace:"); 104 #ifdef CONFIG_KALLSYMS 105 printk("\n"); 106 #endif 107 while (!kstack_end(sp)) { 108 unsigned long __user *p = 109 (unsigned long __user *)(unsigned long)sp++; 110 if (__get_user(addr, p)) { 111 printk(" (Bad stack address)"); 112 break; 113 } 114 if (__kernel_text_address(addr)) 115 print_ip_sym(addr); 116 } 117 printk("\n"); 118 } 119 120 #ifdef CONFIG_KALLSYMS 121 int raw_show_trace; 122 static int __init set_raw_show_trace(char *str) 123 { 124 raw_show_trace = 1; 125 return 1; 126 } 127 __setup("raw_show_trace", set_raw_show_trace); 128 #endif 129 130 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 131 { 132 unsigned long sp = regs->regs[29]; 133 unsigned long ra = regs->regs[31]; 134 unsigned long pc = regs->cp0_epc; 135 136 if (!task) 137 task = current; 138 139 if (raw_show_trace || !__kernel_text_address(pc)) { 140 show_raw_backtrace(sp); 141 return; 142 } 143 printk("Call Trace:\n"); 144 do { 145 print_ip_sym(pc); 146 pc = unwind_stack(task, &sp, pc, &ra); 147 } while (pc); 148 printk("\n"); 149 } 150 151 /* 152 * This routine abuses get_user()/put_user() to reference pointers 153 * with at least a bit of error checking ... 154 */ 155 static void show_stacktrace(struct task_struct *task, 156 const struct pt_regs *regs) 157 { 158 const int field = 2 * sizeof(unsigned long); 159 long stackdata; 160 int i; 161 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 162 163 printk("Stack :"); 164 i = 0; 165 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 166 if (i && ((i % (64 / field)) == 0)) 167 printk("\n "); 168 if (i > 39) { 169 printk(" ..."); 170 break; 171 } 172 173 if (__get_user(stackdata, sp++)) { 174 printk(" (Bad stack address)"); 175 break; 176 } 177 178 printk(" %0*lx", field, stackdata); 179 i++; 180 } 181 printk("\n"); 182 show_backtrace(task, regs); 183 } 184 185 void show_stack(struct task_struct *task, unsigned long *sp) 186 { 187 struct pt_regs regs; 188 if (sp) { 189 regs.regs[29] = (unsigned long)sp; 190 regs.regs[31] = 0; 191 regs.cp0_epc = 0; 192 } else { 193 if (task && task != current) { 194 regs.regs[29] = task->thread.reg29; 195 regs.regs[31] = 0; 196 regs.cp0_epc = task->thread.reg31; 197 #ifdef CONFIG_KGDB_KDB 198 } else if (atomic_read(&kgdb_active) != -1 && 199 kdb_current_regs) { 200 memcpy(®s, kdb_current_regs, sizeof(regs)); 201 #endif /* CONFIG_KGDB_KDB */ 202 } else { 203 prepare_frametrace(®s); 204 } 205 } 206 show_stacktrace(task, ®s); 207 } 208 209 static void show_code(unsigned int __user *pc) 210 { 211 long i; 212 unsigned short __user *pc16 = NULL; 213 214 printk("\nCode:"); 215 216 if ((unsigned long)pc & 1) 217 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 218 for(i = -3 ; i < 6 ; i++) { 219 unsigned int insn; 220 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 221 printk(" (Bad address in epc)\n"); 222 break; 223 } 224 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 225 } 226 } 227 228 static void __show_regs(const struct pt_regs *regs) 229 { 230 const int field = 2 * sizeof(unsigned long); 231 unsigned int cause = regs->cp0_cause; 232 int i; 233 234 show_regs_print_info(KERN_DEFAULT); 235 236 /* 237 * Saved main processor registers 238 */ 239 for (i = 0; i < 32; ) { 240 if ((i % 4) == 0) 241 printk("$%2d :", i); 242 if (i == 0) 243 printk(" %0*lx", field, 0UL); 244 else if (i == 26 || i == 27) 245 printk(" %*s", field, ""); 246 else 247 printk(" %0*lx", field, regs->regs[i]); 248 249 i++; 250 if ((i % 4) == 0) 251 printk("\n"); 252 } 253 254 #ifdef CONFIG_CPU_HAS_SMARTMIPS 255 printk("Acx : %0*lx\n", field, regs->acx); 256 #endif 257 printk("Hi : %0*lx\n", field, regs->hi); 258 printk("Lo : %0*lx\n", field, regs->lo); 259 260 /* 261 * Saved cp0 registers 262 */ 263 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 264 (void *) regs->cp0_epc); 265 printk(" %s\n", print_tainted()); 266 printk("ra : %0*lx %pS\n", field, regs->regs[31], 267 (void *) regs->regs[31]); 268 269 printk("Status: %08x ", (uint32_t) regs->cp0_status); 270 271 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 272 if (regs->cp0_status & ST0_KUO) 273 printk("KUo "); 274 if (regs->cp0_status & ST0_IEO) 275 printk("IEo "); 276 if (regs->cp0_status & ST0_KUP) 277 printk("KUp "); 278 if (regs->cp0_status & ST0_IEP) 279 printk("IEp "); 280 if (regs->cp0_status & ST0_KUC) 281 printk("KUc "); 282 if (regs->cp0_status & ST0_IEC) 283 printk("IEc "); 284 } else { 285 if (regs->cp0_status & ST0_KX) 286 printk("KX "); 287 if (regs->cp0_status & ST0_SX) 288 printk("SX "); 289 if (regs->cp0_status & ST0_UX) 290 printk("UX "); 291 switch (regs->cp0_status & ST0_KSU) { 292 case KSU_USER: 293 printk("USER "); 294 break; 295 case KSU_SUPERVISOR: 296 printk("SUPERVISOR "); 297 break; 298 case KSU_KERNEL: 299 printk("KERNEL "); 300 break; 301 default: 302 printk("BAD_MODE "); 303 break; 304 } 305 if (regs->cp0_status & ST0_ERL) 306 printk("ERL "); 307 if (regs->cp0_status & ST0_EXL) 308 printk("EXL "); 309 if (regs->cp0_status & ST0_IE) 310 printk("IE "); 311 } 312 printk("\n"); 313 314 printk("Cause : %08x\n", cause); 315 316 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 317 if (1 <= cause && cause <= 5) 318 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 319 320 printk("PrId : %08x (%s)\n", read_c0_prid(), 321 cpu_name_string()); 322 } 323 324 /* 325 * FIXME: really the generic show_regs should take a const pointer argument. 326 */ 327 void show_regs(struct pt_regs *regs) 328 { 329 __show_regs((struct pt_regs *)regs); 330 } 331 332 void show_registers(struct pt_regs *regs) 333 { 334 const int field = 2 * sizeof(unsigned long); 335 336 __show_regs(regs); 337 print_modules(); 338 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 339 current->comm, current->pid, current_thread_info(), current, 340 field, current_thread_info()->tp_value); 341 if (cpu_has_userlocal) { 342 unsigned long tls; 343 344 tls = read_c0_userlocal(); 345 if (tls != current_thread_info()->tp_value) 346 printk("*HwTLS: %0*lx\n", field, tls); 347 } 348 349 show_stacktrace(current, regs); 350 show_code((unsigned int __user *) regs->cp0_epc); 351 printk("\n"); 352 } 353 354 static int regs_to_trapnr(struct pt_regs *regs) 355 { 356 return (regs->cp0_cause >> 2) & 0x1f; 357 } 358 359 static DEFINE_RAW_SPINLOCK(die_lock); 360 361 void __noreturn die(const char *str, struct pt_regs *regs) 362 { 363 static int die_counter; 364 int sig = SIGSEGV; 365 #ifdef CONFIG_MIPS_MT_SMTC 366 unsigned long dvpret; 367 #endif /* CONFIG_MIPS_MT_SMTC */ 368 369 oops_enter(); 370 371 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) 372 sig = 0; 373 374 console_verbose(); 375 raw_spin_lock_irq(&die_lock); 376 #ifdef CONFIG_MIPS_MT_SMTC 377 dvpret = dvpe(); 378 #endif /* CONFIG_MIPS_MT_SMTC */ 379 bust_spinlocks(1); 380 #ifdef CONFIG_MIPS_MT_SMTC 381 mips_mt_regdump(dvpret); 382 #endif /* CONFIG_MIPS_MT_SMTC */ 383 384 printk("%s[#%d]:\n", str, ++die_counter); 385 show_registers(regs); 386 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 387 raw_spin_unlock_irq(&die_lock); 388 389 oops_exit(); 390 391 if (in_interrupt()) 392 panic("Fatal exception in interrupt"); 393 394 if (panic_on_oops) { 395 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 396 ssleep(5); 397 panic("Fatal exception"); 398 } 399 400 if (regs && kexec_should_crash(current)) 401 crash_kexec(regs); 402 403 do_exit(sig); 404 } 405 406 extern struct exception_table_entry __start___dbe_table[]; 407 extern struct exception_table_entry __stop___dbe_table[]; 408 409 __asm__( 410 " .section __dbe_table, \"a\"\n" 411 " .previous \n"); 412 413 /* Given an address, look for it in the exception tables. */ 414 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 415 { 416 const struct exception_table_entry *e; 417 418 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 419 if (!e) 420 e = search_module_dbetables(addr); 421 return e; 422 } 423 424 asmlinkage void do_be(struct pt_regs *regs) 425 { 426 const int field = 2 * sizeof(unsigned long); 427 const struct exception_table_entry *fixup = NULL; 428 int data = regs->cp0_cause & 4; 429 int action = MIPS_BE_FATAL; 430 431 /* XXX For now. Fixme, this searches the wrong table ... */ 432 if (data && !user_mode(regs)) 433 fixup = search_dbe_tables(exception_epc(regs)); 434 435 if (fixup) 436 action = MIPS_BE_FIXUP; 437 438 if (board_be_handler) 439 action = board_be_handler(regs, fixup != NULL); 440 441 switch (action) { 442 case MIPS_BE_DISCARD: 443 return; 444 case MIPS_BE_FIXUP: 445 if (fixup) { 446 regs->cp0_epc = fixup->nextinsn; 447 return; 448 } 449 break; 450 default: 451 break; 452 } 453 454 /* 455 * Assume it would be too dangerous to continue ... 456 */ 457 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 458 data ? "Data" : "Instruction", 459 field, regs->cp0_epc, field, regs->regs[31]); 460 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) 461 == NOTIFY_STOP) 462 return; 463 464 die_if_kernel("Oops", regs); 465 force_sig(SIGBUS, current); 466 } 467 468 /* 469 * ll/sc, rdhwr, sync emulation 470 */ 471 472 #define OPCODE 0xfc000000 473 #define BASE 0x03e00000 474 #define RT 0x001f0000 475 #define OFFSET 0x0000ffff 476 #define LL 0xc0000000 477 #define SC 0xe0000000 478 #define SPEC0 0x00000000 479 #define SPEC3 0x7c000000 480 #define RD 0x0000f800 481 #define FUNC 0x0000003f 482 #define SYNC 0x0000000f 483 #define RDHWR 0x0000003b 484 485 /* 486 * The ll_bit is cleared by r*_switch.S 487 */ 488 489 unsigned int ll_bit; 490 struct task_struct *ll_task; 491 492 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 493 { 494 unsigned long value, __user *vaddr; 495 long offset; 496 497 /* 498 * analyse the ll instruction that just caused a ri exception 499 * and put the referenced address to addr. 500 */ 501 502 /* sign extend offset */ 503 offset = opcode & OFFSET; 504 offset <<= 16; 505 offset >>= 16; 506 507 vaddr = (unsigned long __user *) 508 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 509 510 if ((unsigned long)vaddr & 3) 511 return SIGBUS; 512 if (get_user(value, vaddr)) 513 return SIGSEGV; 514 515 preempt_disable(); 516 517 if (ll_task == NULL || ll_task == current) { 518 ll_bit = 1; 519 } else { 520 ll_bit = 0; 521 } 522 ll_task = current; 523 524 preempt_enable(); 525 526 regs->regs[(opcode & RT) >> 16] = value; 527 528 return 0; 529 } 530 531 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 532 { 533 unsigned long __user *vaddr; 534 unsigned long reg; 535 long offset; 536 537 /* 538 * analyse the sc instruction that just caused a ri exception 539 * and put the referenced address to addr. 540 */ 541 542 /* sign extend offset */ 543 offset = opcode & OFFSET; 544 offset <<= 16; 545 offset >>= 16; 546 547 vaddr = (unsigned long __user *) 548 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 549 reg = (opcode & RT) >> 16; 550 551 if ((unsigned long)vaddr & 3) 552 return SIGBUS; 553 554 preempt_disable(); 555 556 if (ll_bit == 0 || ll_task != current) { 557 regs->regs[reg] = 0; 558 preempt_enable(); 559 return 0; 560 } 561 562 preempt_enable(); 563 564 if (put_user(regs->regs[reg], vaddr)) 565 return SIGSEGV; 566 567 regs->regs[reg] = 1; 568 569 return 0; 570 } 571 572 /* 573 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 574 * opcodes are supposed to result in coprocessor unusable exceptions if 575 * executed on ll/sc-less processors. That's the theory. In practice a 576 * few processors such as NEC's VR4100 throw reserved instruction exceptions 577 * instead, so we're doing the emulation thing in both exception handlers. 578 */ 579 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 580 { 581 if ((opcode & OPCODE) == LL) { 582 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 583 1, regs, 0); 584 return simulate_ll(regs, opcode); 585 } 586 if ((opcode & OPCODE) == SC) { 587 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 588 1, regs, 0); 589 return simulate_sc(regs, opcode); 590 } 591 592 return -1; /* Must be something else ... */ 593 } 594 595 /* 596 * Simulate trapping 'rdhwr' instructions to provide user accessible 597 * registers not implemented in hardware. 598 */ 599 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 600 { 601 struct thread_info *ti = task_thread_info(current); 602 603 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 604 int rd = (opcode & RD) >> 11; 605 int rt = (opcode & RT) >> 16; 606 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 607 1, regs, 0); 608 switch (rd) { 609 case 0: /* CPU number */ 610 regs->regs[rt] = smp_processor_id(); 611 return 0; 612 case 1: /* SYNCI length */ 613 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 614 current_cpu_data.icache.linesz); 615 return 0; 616 case 2: /* Read count register */ 617 regs->regs[rt] = read_c0_count(); 618 return 0; 619 case 3: /* Count register resolution */ 620 switch (current_cpu_data.cputype) { 621 case CPU_20KC: 622 case CPU_25KF: 623 regs->regs[rt] = 1; 624 break; 625 default: 626 regs->regs[rt] = 2; 627 } 628 return 0; 629 case 29: 630 regs->regs[rt] = ti->tp_value; 631 return 0; 632 default: 633 return -1; 634 } 635 } 636 637 /* Not ours. */ 638 return -1; 639 } 640 641 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 642 { 643 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 644 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 645 1, regs, 0); 646 return 0; 647 } 648 649 return -1; /* Must be something else ... */ 650 } 651 652 asmlinkage void do_ov(struct pt_regs *regs) 653 { 654 siginfo_t info; 655 656 die_if_kernel("Integer overflow", regs); 657 658 info.si_code = FPE_INTOVF; 659 info.si_signo = SIGFPE; 660 info.si_errno = 0; 661 info.si_addr = (void __user *) regs->cp0_epc; 662 force_sig_info(SIGFPE, &info, current); 663 } 664 665 static int process_fpemu_return(int sig, void __user *fault_addr) 666 { 667 if (sig == SIGSEGV || sig == SIGBUS) { 668 struct siginfo si = {0}; 669 si.si_addr = fault_addr; 670 si.si_signo = sig; 671 if (sig == SIGSEGV) { 672 if (find_vma(current->mm, (unsigned long)fault_addr)) 673 si.si_code = SEGV_ACCERR; 674 else 675 si.si_code = SEGV_MAPERR; 676 } else { 677 si.si_code = BUS_ADRERR; 678 } 679 force_sig_info(sig, &si, current); 680 return 1; 681 } else if (sig) { 682 force_sig(sig, current); 683 return 1; 684 } else { 685 return 0; 686 } 687 } 688 689 /* 690 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 691 */ 692 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 693 { 694 siginfo_t info = {0}; 695 696 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 697 == NOTIFY_STOP) 698 return; 699 die_if_kernel("FP exception in kernel code", regs); 700 701 if (fcr31 & FPU_CSR_UNI_X) { 702 int sig; 703 void __user *fault_addr = NULL; 704 705 /* 706 * Unimplemented operation exception. If we've got the full 707 * software emulator on-board, let's use it... 708 * 709 * Force FPU to dump state into task/thread context. We're 710 * moving a lot of data here for what is probably a single 711 * instruction, but the alternative is to pre-decode the FP 712 * register operands before invoking the emulator, which seems 713 * a bit extreme for what should be an infrequent event. 714 */ 715 /* Ensure 'resume' not overwrite saved fp context again. */ 716 lose_fpu(1); 717 718 /* Run the emulator */ 719 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 720 &fault_addr); 721 722 /* 723 * We can't allow the emulated instruction to leave any of 724 * the cause bit set in $fcr31. 725 */ 726 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 727 728 /* Restore the hardware register state */ 729 own_fpu(1); /* Using the FPU again. */ 730 731 /* If something went wrong, signal */ 732 process_fpemu_return(sig, fault_addr); 733 734 return; 735 } else if (fcr31 & FPU_CSR_INV_X) 736 info.si_code = FPE_FLTINV; 737 else if (fcr31 & FPU_CSR_DIV_X) 738 info.si_code = FPE_FLTDIV; 739 else if (fcr31 & FPU_CSR_OVF_X) 740 info.si_code = FPE_FLTOVF; 741 else if (fcr31 & FPU_CSR_UDF_X) 742 info.si_code = FPE_FLTUND; 743 else if (fcr31 & FPU_CSR_INE_X) 744 info.si_code = FPE_FLTRES; 745 else 746 info.si_code = __SI_FAULT; 747 info.si_signo = SIGFPE; 748 info.si_errno = 0; 749 info.si_addr = (void __user *) regs->cp0_epc; 750 force_sig_info(SIGFPE, &info, current); 751 } 752 753 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 754 const char *str) 755 { 756 siginfo_t info; 757 char b[40]; 758 759 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 760 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 761 return; 762 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 763 764 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 765 return; 766 767 /* 768 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 769 * insns, even for trap and break codes that indicate arithmetic 770 * failures. Weird ... 771 * But should we continue the brokenness??? --macro 772 */ 773 switch (code) { 774 case BRK_OVERFLOW: 775 case BRK_DIVZERO: 776 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 777 die_if_kernel(b, regs); 778 if (code == BRK_DIVZERO) 779 info.si_code = FPE_INTDIV; 780 else 781 info.si_code = FPE_INTOVF; 782 info.si_signo = SIGFPE; 783 info.si_errno = 0; 784 info.si_addr = (void __user *) regs->cp0_epc; 785 force_sig_info(SIGFPE, &info, current); 786 break; 787 case BRK_BUG: 788 die_if_kernel("Kernel bug detected", regs); 789 force_sig(SIGTRAP, current); 790 break; 791 case BRK_MEMU: 792 /* 793 * Address errors may be deliberately induced by the FPU 794 * emulator to retake control of the CPU after executing the 795 * instruction in the delay slot of an emulated branch. 796 * 797 * Terminate if exception was recognized as a delay slot return 798 * otherwise handle as normal. 799 */ 800 if (do_dsemulret(regs)) 801 return; 802 803 die_if_kernel("Math emu break/trap", regs); 804 force_sig(SIGTRAP, current); 805 break; 806 default: 807 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 808 die_if_kernel(b, regs); 809 force_sig(SIGTRAP, current); 810 } 811 } 812 813 asmlinkage void do_bp(struct pt_regs *regs) 814 { 815 unsigned int opcode, bcode; 816 817 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 818 goto out_sigsegv; 819 820 /* 821 * There is the ancient bug in the MIPS assemblers that the break 822 * code starts left to bit 16 instead to bit 6 in the opcode. 823 * Gas is bug-compatible, but not always, grrr... 824 * We handle both cases with a simple heuristics. --macro 825 */ 826 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 827 if (bcode >= (1 << 10)) 828 bcode >>= 10; 829 830 /* 831 * notify the kprobe handlers, if instruction is likely to 832 * pertain to them. 833 */ 834 switch (bcode) { 835 case BRK_KPROBE_BP: 836 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 837 return; 838 else 839 break; 840 case BRK_KPROBE_SSTEPBP: 841 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 842 return; 843 else 844 break; 845 default: 846 break; 847 } 848 849 do_trap_or_bp(regs, bcode, "Break"); 850 return; 851 852 out_sigsegv: 853 force_sig(SIGSEGV, current); 854 } 855 856 asmlinkage void do_tr(struct pt_regs *regs) 857 { 858 unsigned int opcode, tcode = 0; 859 860 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 861 goto out_sigsegv; 862 863 /* Immediate versions don't provide a code. */ 864 if (!(opcode & OPCODE)) 865 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 866 867 do_trap_or_bp(regs, tcode, "Trap"); 868 return; 869 870 out_sigsegv: 871 force_sig(SIGSEGV, current); 872 } 873 874 asmlinkage void do_ri(struct pt_regs *regs) 875 { 876 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 877 unsigned long old_epc = regs->cp0_epc; 878 unsigned int opcode = 0; 879 int status = -1; 880 881 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) 882 == NOTIFY_STOP) 883 return; 884 885 die_if_kernel("Reserved instruction in kernel code", regs); 886 887 if (unlikely(compute_return_epc(regs) < 0)) 888 return; 889 890 if (unlikely(get_user(opcode, epc) < 0)) 891 status = SIGSEGV; 892 893 if (!cpu_has_llsc && status < 0) 894 status = simulate_llsc(regs, opcode); 895 896 if (status < 0) 897 status = simulate_rdhwr(regs, opcode); 898 899 if (status < 0) 900 status = simulate_sync(regs, opcode); 901 902 if (status < 0) 903 status = SIGILL; 904 905 if (unlikely(status > 0)) { 906 regs->cp0_epc = old_epc; /* Undo skip-over. */ 907 force_sig(status, current); 908 } 909 } 910 911 /* 912 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 913 * emulated more than some threshold number of instructions, force migration to 914 * a "CPU" that has FP support. 915 */ 916 static void mt_ase_fp_affinity(void) 917 { 918 #ifdef CONFIG_MIPS_MT_FPAFF 919 if (mt_fpemul_threshold > 0 && 920 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 921 /* 922 * If there's no FPU present, or if the application has already 923 * restricted the allowed set to exclude any CPUs with FPUs, 924 * we'll skip the procedure. 925 */ 926 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 927 cpumask_t tmask; 928 929 current->thread.user_cpus_allowed 930 = current->cpus_allowed; 931 cpus_and(tmask, current->cpus_allowed, 932 mt_fpu_cpumask); 933 set_cpus_allowed_ptr(current, &tmask); 934 set_thread_flag(TIF_FPUBOUND); 935 } 936 } 937 #endif /* CONFIG_MIPS_MT_FPAFF */ 938 } 939 940 /* 941 * No lock; only written during early bootup by CPU 0. 942 */ 943 static RAW_NOTIFIER_HEAD(cu2_chain); 944 945 int __ref register_cu2_notifier(struct notifier_block *nb) 946 { 947 return raw_notifier_chain_register(&cu2_chain, nb); 948 } 949 950 int cu2_notifier_call_chain(unsigned long val, void *v) 951 { 952 return raw_notifier_call_chain(&cu2_chain, val, v); 953 } 954 955 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 956 void *data) 957 { 958 struct pt_regs *regs = data; 959 960 switch (action) { 961 default: 962 die_if_kernel("Unhandled kernel unaligned access or invalid " 963 "instruction", regs); 964 /* Fall through */ 965 966 case CU2_EXCEPTION: 967 force_sig(SIGILL, current); 968 } 969 970 return NOTIFY_OK; 971 } 972 973 asmlinkage void do_cpu(struct pt_regs *regs) 974 { 975 unsigned int __user *epc; 976 unsigned long old_epc; 977 unsigned int opcode; 978 unsigned int cpid; 979 int status; 980 unsigned long __maybe_unused flags; 981 982 die_if_kernel("do_cpu invoked from kernel context!", regs); 983 984 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 985 986 switch (cpid) { 987 case 0: 988 epc = (unsigned int __user *)exception_epc(regs); 989 old_epc = regs->cp0_epc; 990 opcode = 0; 991 status = -1; 992 993 if (unlikely(compute_return_epc(regs) < 0)) 994 return; 995 996 if (unlikely(get_user(opcode, epc) < 0)) 997 status = SIGSEGV; 998 999 if (!cpu_has_llsc && status < 0) 1000 status = simulate_llsc(regs, opcode); 1001 1002 if (status < 0) 1003 status = simulate_rdhwr(regs, opcode); 1004 1005 if (status < 0) 1006 status = SIGILL; 1007 1008 if (unlikely(status > 0)) { 1009 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1010 force_sig(status, current); 1011 } 1012 1013 return; 1014 1015 case 3: 1016 /* 1017 * Old (MIPS I and MIPS II) processors will set this code 1018 * for COP1X opcode instructions that replaced the original 1019 * COP3 space. We don't limit COP1 space instructions in 1020 * the emulator according to the CPU ISA, so we want to 1021 * treat COP1X instructions consistently regardless of which 1022 * code the CPU chose. Therefore we redirect this trap to 1023 * the FP emulator too. 1024 * 1025 * Then some newer FPU-less processors use this code 1026 * erroneously too, so they are covered by this choice 1027 * as well. 1028 */ 1029 if (raw_cpu_has_fpu) 1030 break; 1031 /* Fall through. */ 1032 1033 case 1: 1034 if (used_math()) /* Using the FPU again. */ 1035 own_fpu(1); 1036 else { /* First time FPU user. */ 1037 init_fpu(); 1038 set_used_math(); 1039 } 1040 1041 if (!raw_cpu_has_fpu) { 1042 int sig; 1043 void __user *fault_addr = NULL; 1044 sig = fpu_emulator_cop1Handler(regs, 1045 ¤t->thread.fpu, 1046 0, &fault_addr); 1047 if (!process_fpemu_return(sig, fault_addr)) 1048 mt_ase_fp_affinity(); 1049 } 1050 1051 return; 1052 1053 case 2: 1054 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1055 return; 1056 } 1057 1058 force_sig(SIGILL, current); 1059 } 1060 1061 asmlinkage void do_mdmx(struct pt_regs *regs) 1062 { 1063 force_sig(SIGILL, current); 1064 } 1065 1066 /* 1067 * Called with interrupts disabled. 1068 */ 1069 asmlinkage void do_watch(struct pt_regs *regs) 1070 { 1071 u32 cause; 1072 1073 /* 1074 * Clear WP (bit 22) bit of cause register so we don't loop 1075 * forever. 1076 */ 1077 cause = read_c0_cause(); 1078 cause &= ~(1 << 22); 1079 write_c0_cause(cause); 1080 1081 /* 1082 * If the current thread has the watch registers loaded, save 1083 * their values and send SIGTRAP. Otherwise another thread 1084 * left the registers set, clear them and continue. 1085 */ 1086 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1087 mips_read_watch_registers(); 1088 local_irq_enable(); 1089 force_sig(SIGTRAP, current); 1090 } else { 1091 mips_clear_watch_registers(); 1092 local_irq_enable(); 1093 } 1094 } 1095 1096 asmlinkage void do_mcheck(struct pt_regs *regs) 1097 { 1098 const int field = 2 * sizeof(unsigned long); 1099 int multi_match = regs->cp0_status & ST0_TS; 1100 1101 show_regs(regs); 1102 1103 if (multi_match) { 1104 printk("Index : %0x\n", read_c0_index()); 1105 printk("Pagemask: %0x\n", read_c0_pagemask()); 1106 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1107 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1108 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1109 printk("\n"); 1110 dump_tlb_all(); 1111 } 1112 1113 show_code((unsigned int __user *) regs->cp0_epc); 1114 1115 /* 1116 * Some chips may have other causes of machine check (e.g. SB1 1117 * graduation timer) 1118 */ 1119 panic("Caught Machine Check exception - %scaused by multiple " 1120 "matching entries in the TLB.", 1121 (multi_match) ? "" : "not "); 1122 } 1123 1124 asmlinkage void do_mt(struct pt_regs *regs) 1125 { 1126 int subcode; 1127 1128 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1129 >> VPECONTROL_EXCPT_SHIFT; 1130 switch (subcode) { 1131 case 0: 1132 printk(KERN_DEBUG "Thread Underflow\n"); 1133 break; 1134 case 1: 1135 printk(KERN_DEBUG "Thread Overflow\n"); 1136 break; 1137 case 2: 1138 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1139 break; 1140 case 3: 1141 printk(KERN_DEBUG "Gating Storage Exception\n"); 1142 break; 1143 case 4: 1144 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1145 break; 1146 case 5: 1147 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1148 break; 1149 default: 1150 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1151 subcode); 1152 break; 1153 } 1154 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1155 1156 force_sig(SIGILL, current); 1157 } 1158 1159 1160 asmlinkage void do_dsp(struct pt_regs *regs) 1161 { 1162 if (cpu_has_dsp) 1163 panic("Unexpected DSP exception"); 1164 1165 force_sig(SIGILL, current); 1166 } 1167 1168 asmlinkage void do_reserved(struct pt_regs *regs) 1169 { 1170 /* 1171 * Game over - no way to handle this if it ever occurs. Most probably 1172 * caused by a new unknown cpu type or after another deadly 1173 * hard/software error. 1174 */ 1175 show_regs(regs); 1176 panic("Caught reserved exception %ld - should not happen.", 1177 (regs->cp0_cause & 0x7f) >> 2); 1178 } 1179 1180 static int __initdata l1parity = 1; 1181 static int __init nol1parity(char *s) 1182 { 1183 l1parity = 0; 1184 return 1; 1185 } 1186 __setup("nol1par", nol1parity); 1187 static int __initdata l2parity = 1; 1188 static int __init nol2parity(char *s) 1189 { 1190 l2parity = 0; 1191 return 1; 1192 } 1193 __setup("nol2par", nol2parity); 1194 1195 /* 1196 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1197 * it different ways. 1198 */ 1199 static inline void parity_protection_init(void) 1200 { 1201 switch (current_cpu_type()) { 1202 case CPU_24K: 1203 case CPU_34K: 1204 case CPU_74K: 1205 case CPU_1004K: 1206 { 1207 #define ERRCTL_PE 0x80000000 1208 #define ERRCTL_L2P 0x00800000 1209 unsigned long errctl; 1210 unsigned int l1parity_present, l2parity_present; 1211 1212 errctl = read_c0_ecc(); 1213 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1214 1215 /* probe L1 parity support */ 1216 write_c0_ecc(errctl | ERRCTL_PE); 1217 back_to_back_c0_hazard(); 1218 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1219 1220 /* probe L2 parity support */ 1221 write_c0_ecc(errctl|ERRCTL_L2P); 1222 back_to_back_c0_hazard(); 1223 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1224 1225 if (l1parity_present && l2parity_present) { 1226 if (l1parity) 1227 errctl |= ERRCTL_PE; 1228 if (l1parity ^ l2parity) 1229 errctl |= ERRCTL_L2P; 1230 } else if (l1parity_present) { 1231 if (l1parity) 1232 errctl |= ERRCTL_PE; 1233 } else if (l2parity_present) { 1234 if (l2parity) 1235 errctl |= ERRCTL_L2P; 1236 } else { 1237 /* No parity available */ 1238 } 1239 1240 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1241 1242 write_c0_ecc(errctl); 1243 back_to_back_c0_hazard(); 1244 errctl = read_c0_ecc(); 1245 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1246 1247 if (l1parity_present) 1248 printk(KERN_INFO "Cache parity protection %sabled\n", 1249 (errctl & ERRCTL_PE) ? "en" : "dis"); 1250 1251 if (l2parity_present) { 1252 if (l1parity_present && l1parity) 1253 errctl ^= ERRCTL_L2P; 1254 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1255 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1256 } 1257 } 1258 break; 1259 1260 case CPU_5KC: 1261 case CPU_5KE: 1262 case CPU_LOONGSON1: 1263 write_c0_ecc(0x80000000); 1264 back_to_back_c0_hazard(); 1265 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1266 printk(KERN_INFO "Cache parity protection %sabled\n", 1267 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1268 break; 1269 case CPU_20KC: 1270 case CPU_25KF: 1271 /* Clear the DE bit (bit 16) in the c0_status register. */ 1272 printk(KERN_INFO "Enable cache parity protection for " 1273 "MIPS 20KC/25KF CPUs.\n"); 1274 clear_c0_status(ST0_DE); 1275 break; 1276 default: 1277 break; 1278 } 1279 } 1280 1281 asmlinkage void cache_parity_error(void) 1282 { 1283 const int field = 2 * sizeof(unsigned long); 1284 unsigned int reg_val; 1285 1286 /* For the moment, report the problem and hang. */ 1287 printk("Cache error exception:\n"); 1288 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1289 reg_val = read_c0_cacheerr(); 1290 printk("c0_cacheerr == %08x\n", reg_val); 1291 1292 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1293 reg_val & (1<<30) ? "secondary" : "primary", 1294 reg_val & (1<<31) ? "data" : "insn"); 1295 printk("Error bits: %s%s%s%s%s%s%s\n", 1296 reg_val & (1<<29) ? "ED " : "", 1297 reg_val & (1<<28) ? "ET " : "", 1298 reg_val & (1<<26) ? "EE " : "", 1299 reg_val & (1<<25) ? "EB " : "", 1300 reg_val & (1<<24) ? "EI " : "", 1301 reg_val & (1<<23) ? "E1 " : "", 1302 reg_val & (1<<22) ? "E0 " : ""); 1303 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1304 1305 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1306 if (reg_val & (1<<22)) 1307 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1308 1309 if (reg_val & (1<<23)) 1310 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1311 #endif 1312 1313 panic("Can't handle the cache error!"); 1314 } 1315 1316 /* 1317 * SDBBP EJTAG debug exception handler. 1318 * We skip the instruction and return to the next instruction. 1319 */ 1320 void ejtag_exception_handler(struct pt_regs *regs) 1321 { 1322 const int field = 2 * sizeof(unsigned long); 1323 unsigned long depc, old_epc; 1324 unsigned int debug; 1325 1326 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1327 depc = read_c0_depc(); 1328 debug = read_c0_debug(); 1329 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1330 if (debug & 0x80000000) { 1331 /* 1332 * In branch delay slot. 1333 * We cheat a little bit here and use EPC to calculate the 1334 * debug return address (DEPC). EPC is restored after the 1335 * calculation. 1336 */ 1337 old_epc = regs->cp0_epc; 1338 regs->cp0_epc = depc; 1339 __compute_return_epc(regs); 1340 depc = regs->cp0_epc; 1341 regs->cp0_epc = old_epc; 1342 } else 1343 depc += 4; 1344 write_c0_depc(depc); 1345 1346 #if 0 1347 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1348 write_c0_debug(debug | 0x100); 1349 #endif 1350 } 1351 1352 /* 1353 * NMI exception handler. 1354 * No lock; only written during early bootup by CPU 0. 1355 */ 1356 static RAW_NOTIFIER_HEAD(nmi_chain); 1357 1358 int register_nmi_notifier(struct notifier_block *nb) 1359 { 1360 return raw_notifier_chain_register(&nmi_chain, nb); 1361 } 1362 1363 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1364 { 1365 raw_notifier_call_chain(&nmi_chain, 0, regs); 1366 bust_spinlocks(1); 1367 printk("NMI taken!!!!\n"); 1368 die("NMI", regs); 1369 } 1370 1371 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1372 1373 unsigned long ebase; 1374 unsigned long exception_handlers[32]; 1375 unsigned long vi_handlers[64]; 1376 1377 void __init *set_except_vector(int n, void *addr) 1378 { 1379 unsigned long handler = (unsigned long) addr; 1380 unsigned long old_handler = exception_handlers[n]; 1381 1382 exception_handlers[n] = handler; 1383 if (n == 0 && cpu_has_divec) { 1384 unsigned long jump_mask = ~((1 << 28) - 1); 1385 u32 *buf = (u32 *)(ebase + 0x200); 1386 unsigned int k0 = 26; 1387 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1388 uasm_i_j(&buf, handler & ~jump_mask); 1389 uasm_i_nop(&buf); 1390 } else { 1391 UASM_i_LA(&buf, k0, handler); 1392 uasm_i_jr(&buf, k0); 1393 uasm_i_nop(&buf); 1394 } 1395 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1396 } 1397 return (void *)old_handler; 1398 } 1399 1400 static asmlinkage void do_default_vi(void) 1401 { 1402 show_regs(get_irq_regs()); 1403 panic("Caught unexpected vectored interrupt."); 1404 } 1405 1406 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1407 { 1408 unsigned long handler; 1409 unsigned long old_handler = vi_handlers[n]; 1410 int srssets = current_cpu_data.srsets; 1411 u32 *w; 1412 unsigned char *b; 1413 1414 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1415 1416 if (addr == NULL) { 1417 handler = (unsigned long) do_default_vi; 1418 srs = 0; 1419 } else 1420 handler = (unsigned long) addr; 1421 vi_handlers[n] = (unsigned long) addr; 1422 1423 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1424 1425 if (srs >= srssets) 1426 panic("Shadow register set %d not supported", srs); 1427 1428 if (cpu_has_veic) { 1429 if (board_bind_eic_interrupt) 1430 board_bind_eic_interrupt(n, srs); 1431 } else if (cpu_has_vint) { 1432 /* SRSMap is only defined if shadow sets are implemented */ 1433 if (srssets > 1) 1434 change_c0_srsmap(0xf << n*4, srs << n*4); 1435 } 1436 1437 if (srs == 0) { 1438 /* 1439 * If no shadow set is selected then use the default handler 1440 * that does normal register saving and a standard interrupt exit 1441 */ 1442 1443 extern char except_vec_vi, except_vec_vi_lui; 1444 extern char except_vec_vi_ori, except_vec_vi_end; 1445 extern char rollback_except_vec_vi; 1446 char *vec_start = (cpu_wait == r4k_wait) ? 1447 &rollback_except_vec_vi : &except_vec_vi; 1448 #ifdef CONFIG_MIPS_MT_SMTC 1449 /* 1450 * We need to provide the SMTC vectored interrupt handler 1451 * not only with the address of the handler, but with the 1452 * Status.IM bit to be masked before going there. 1453 */ 1454 extern char except_vec_vi_mori; 1455 const int mori_offset = &except_vec_vi_mori - vec_start; 1456 #endif /* CONFIG_MIPS_MT_SMTC */ 1457 const int handler_len = &except_vec_vi_end - vec_start; 1458 const int lui_offset = &except_vec_vi_lui - vec_start; 1459 const int ori_offset = &except_vec_vi_ori - vec_start; 1460 1461 if (handler_len > VECTORSPACING) { 1462 /* 1463 * Sigh... panicing won't help as the console 1464 * is probably not configured :( 1465 */ 1466 panic("VECTORSPACING too small"); 1467 } 1468 1469 memcpy(b, vec_start, handler_len); 1470 #ifdef CONFIG_MIPS_MT_SMTC 1471 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1472 1473 w = (u32 *)(b + mori_offset); 1474 *w = (*w & 0xffff0000) | (0x100 << n); 1475 #endif /* CONFIG_MIPS_MT_SMTC */ 1476 w = (u32 *)(b + lui_offset); 1477 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1478 w = (u32 *)(b + ori_offset); 1479 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1480 local_flush_icache_range((unsigned long)b, 1481 (unsigned long)(b+handler_len)); 1482 } 1483 else { 1484 /* 1485 * In other cases jump directly to the interrupt handler 1486 * 1487 * It is the handlers responsibility to save registers if required 1488 * (eg hi/lo) and return from the exception using "eret" 1489 */ 1490 w = (u32 *)b; 1491 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1492 *w = 0; 1493 local_flush_icache_range((unsigned long)b, 1494 (unsigned long)(b+8)); 1495 } 1496 1497 return (void *)old_handler; 1498 } 1499 1500 void *set_vi_handler(int n, vi_handler_t addr) 1501 { 1502 return set_vi_srs_handler(n, addr, 0); 1503 } 1504 1505 extern void tlb_init(void); 1506 extern void flush_tlb_handlers(void); 1507 1508 /* 1509 * Timer interrupt 1510 */ 1511 int cp0_compare_irq; 1512 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1513 int cp0_compare_irq_shift; 1514 1515 /* 1516 * Performance counter IRQ or -1 if shared with timer 1517 */ 1518 int cp0_perfcount_irq; 1519 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1520 1521 static int __cpuinitdata noulri; 1522 1523 static int __init ulri_disable(char *s) 1524 { 1525 pr_info("Disabling ulri\n"); 1526 noulri = 1; 1527 1528 return 1; 1529 } 1530 __setup("noulri", ulri_disable); 1531 1532 void __cpuinit per_cpu_trap_init(bool is_boot_cpu) 1533 { 1534 unsigned int cpu = smp_processor_id(); 1535 unsigned int status_set = ST0_CU0; 1536 unsigned int hwrena = cpu_hwrena_impl_bits; 1537 #ifdef CONFIG_MIPS_MT_SMTC 1538 int secondaryTC = 0; 1539 int bootTC = (cpu == 0); 1540 1541 /* 1542 * Only do per_cpu_trap_init() for first TC of Each VPE. 1543 * Note that this hack assumes that the SMTC init code 1544 * assigns TCs consecutively and in ascending order. 1545 */ 1546 1547 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1548 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1549 secondaryTC = 1; 1550 #endif /* CONFIG_MIPS_MT_SMTC */ 1551 1552 /* 1553 * Disable coprocessors and select 32-bit or 64-bit addressing 1554 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1555 * flag that some firmware may have left set and the TS bit (for 1556 * IP27). Set XX for ISA IV code to work. 1557 */ 1558 #ifdef CONFIG_64BIT 1559 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1560 #endif 1561 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 1562 status_set |= ST0_XX; 1563 if (cpu_has_dsp) 1564 status_set |= ST0_MX; 1565 1566 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1567 status_set); 1568 1569 if (cpu_has_mips_r2) 1570 hwrena |= 0x0000000f; 1571 1572 if (!noulri && cpu_has_userlocal) 1573 hwrena |= (1 << 29); 1574 1575 if (hwrena) 1576 write_c0_hwrena(hwrena); 1577 1578 #ifdef CONFIG_MIPS_MT_SMTC 1579 if (!secondaryTC) { 1580 #endif /* CONFIG_MIPS_MT_SMTC */ 1581 1582 if (cpu_has_veic || cpu_has_vint) { 1583 unsigned long sr = set_c0_status(ST0_BEV); 1584 write_c0_ebase(ebase); 1585 write_c0_status(sr); 1586 /* Setting vector spacing enables EI/VI mode */ 1587 change_c0_intctl(0x3e0, VECTORSPACING); 1588 } 1589 if (cpu_has_divec) { 1590 if (cpu_has_mipsmt) { 1591 unsigned int vpflags = dvpe(); 1592 set_c0_cause(CAUSEF_IV); 1593 evpe(vpflags); 1594 } else 1595 set_c0_cause(CAUSEF_IV); 1596 } 1597 1598 /* 1599 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1600 * 1601 * o read IntCtl.IPTI to determine the timer interrupt 1602 * o read IntCtl.IPPCI to determine the performance counter interrupt 1603 */ 1604 if (cpu_has_mips_r2) { 1605 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1606 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1607 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1608 if (cp0_perfcount_irq == cp0_compare_irq) 1609 cp0_perfcount_irq = -1; 1610 } else { 1611 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1612 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 1613 cp0_perfcount_irq = -1; 1614 } 1615 1616 #ifdef CONFIG_MIPS_MT_SMTC 1617 } 1618 #endif /* CONFIG_MIPS_MT_SMTC */ 1619 1620 if (!cpu_data[cpu].asid_cache) 1621 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1622 1623 atomic_inc(&init_mm.mm_count); 1624 current->active_mm = &init_mm; 1625 BUG_ON(current->mm); 1626 enter_lazy_tlb(&init_mm, current); 1627 1628 #ifdef CONFIG_MIPS_MT_SMTC 1629 if (bootTC) { 1630 #endif /* CONFIG_MIPS_MT_SMTC */ 1631 /* Boot CPU's cache setup in setup_arch(). */ 1632 if (!is_boot_cpu) 1633 cpu_cache_init(); 1634 tlb_init(); 1635 #ifdef CONFIG_MIPS_MT_SMTC 1636 } else if (!secondaryTC) { 1637 /* 1638 * First TC in non-boot VPE must do subset of tlb_init() 1639 * for MMU countrol registers. 1640 */ 1641 write_c0_pagemask(PM_DEFAULT_MASK); 1642 write_c0_wired(0); 1643 } 1644 #endif /* CONFIG_MIPS_MT_SMTC */ 1645 TLBMISS_HANDLER_SETUP(); 1646 } 1647 1648 /* Install CPU exception handler */ 1649 void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) 1650 { 1651 memcpy((void *)(ebase + offset), addr, size); 1652 local_flush_icache_range(ebase + offset, ebase + offset + size); 1653 } 1654 1655 static char panic_null_cerr[] __cpuinitdata = 1656 "Trying to set NULL cache error exception handler"; 1657 1658 /* 1659 * Install uncached CPU exception handler. 1660 * This is suitable only for the cache error exception which is the only 1661 * exception handler that is being run uncached. 1662 */ 1663 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1664 unsigned long size) 1665 { 1666 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1667 1668 if (!addr) 1669 panic(panic_null_cerr); 1670 1671 memcpy((void *)(uncached_ebase + offset), addr, size); 1672 } 1673 1674 static int __initdata rdhwr_noopt; 1675 static int __init set_rdhwr_noopt(char *str) 1676 { 1677 rdhwr_noopt = 1; 1678 return 1; 1679 } 1680 1681 __setup("rdhwr_noopt", set_rdhwr_noopt); 1682 1683 void __init trap_init(void) 1684 { 1685 extern char except_vec3_generic, except_vec3_r4000; 1686 extern char except_vec4; 1687 unsigned long i; 1688 int rollback; 1689 1690 check_wait(); 1691 rollback = (cpu_wait == r4k_wait); 1692 1693 #if defined(CONFIG_KGDB) 1694 if (kgdb_early_setup) 1695 return; /* Already done */ 1696 #endif 1697 1698 if (cpu_has_veic || cpu_has_vint) { 1699 unsigned long size = 0x200 + VECTORSPACING*64; 1700 ebase = (unsigned long) 1701 __alloc_bootmem(size, 1 << fls(size), 0); 1702 } else { 1703 ebase = CKSEG0; 1704 if (cpu_has_mips_r2) 1705 ebase += (read_c0_ebase() & 0x3ffff000); 1706 } 1707 1708 if (board_ebase_setup) 1709 board_ebase_setup(); 1710 per_cpu_trap_init(true); 1711 1712 /* 1713 * Copy the generic exception handlers to their final destination. 1714 * This will be overriden later as suitable for a particular 1715 * configuration. 1716 */ 1717 set_handler(0x180, &except_vec3_generic, 0x80); 1718 1719 /* 1720 * Setup default vectors 1721 */ 1722 for (i = 0; i <= 31; i++) 1723 set_except_vector(i, handle_reserved); 1724 1725 /* 1726 * Copy the EJTAG debug exception vector handler code to it's final 1727 * destination. 1728 */ 1729 if (cpu_has_ejtag && board_ejtag_handler_setup) 1730 board_ejtag_handler_setup(); 1731 1732 /* 1733 * Only some CPUs have the watch exceptions. 1734 */ 1735 if (cpu_has_watch) 1736 set_except_vector(23, handle_watch); 1737 1738 /* 1739 * Initialise interrupt handlers 1740 */ 1741 if (cpu_has_veic || cpu_has_vint) { 1742 int nvec = cpu_has_veic ? 64 : 8; 1743 for (i = 0; i < nvec; i++) 1744 set_vi_handler(i, NULL); 1745 } 1746 else if (cpu_has_divec) 1747 set_handler(0x200, &except_vec4, 0x8); 1748 1749 /* 1750 * Some CPUs can enable/disable for cache parity detection, but does 1751 * it different ways. 1752 */ 1753 parity_protection_init(); 1754 1755 /* 1756 * The Data Bus Errors / Instruction Bus Errors are signaled 1757 * by external hardware. Therefore these two exceptions 1758 * may have board specific handlers. 1759 */ 1760 if (board_be_init) 1761 board_be_init(); 1762 1763 set_except_vector(0, rollback ? rollback_handle_int : handle_int); 1764 set_except_vector(1, handle_tlbm); 1765 set_except_vector(2, handle_tlbl); 1766 set_except_vector(3, handle_tlbs); 1767 1768 set_except_vector(4, handle_adel); 1769 set_except_vector(5, handle_ades); 1770 1771 set_except_vector(6, handle_ibe); 1772 set_except_vector(7, handle_dbe); 1773 1774 set_except_vector(8, handle_sys); 1775 set_except_vector(9, handle_bp); 1776 set_except_vector(10, rdhwr_noopt ? handle_ri : 1777 (cpu_has_vtag_icache ? 1778 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1779 set_except_vector(11, handle_cpu); 1780 set_except_vector(12, handle_ov); 1781 set_except_vector(13, handle_tr); 1782 1783 if (current_cpu_type() == CPU_R6000 || 1784 current_cpu_type() == CPU_R6000A) { 1785 /* 1786 * The R6000 is the only R-series CPU that features a machine 1787 * check exception (similar to the R4000 cache error) and 1788 * unaligned ldc1/sdc1 exception. The handlers have not been 1789 * written yet. Well, anyway there is no R6000 machine on the 1790 * current list of targets for Linux/MIPS. 1791 * (Duh, crap, there is someone with a triple R6k machine) 1792 */ 1793 //set_except_vector(14, handle_mc); 1794 //set_except_vector(15, handle_ndc); 1795 } 1796 1797 1798 if (board_nmi_handler_setup) 1799 board_nmi_handler_setup(); 1800 1801 if (cpu_has_fpu && !cpu_has_nofpuex) 1802 set_except_vector(15, handle_fpe); 1803 1804 set_except_vector(22, handle_mdmx); 1805 1806 if (cpu_has_mcheck) 1807 set_except_vector(24, handle_mcheck); 1808 1809 if (cpu_has_mipsmt) 1810 set_except_vector(25, handle_mt); 1811 1812 set_except_vector(26, handle_dsp); 1813 1814 if (board_cache_error_setup) 1815 board_cache_error_setup(); 1816 1817 if (cpu_has_vce) 1818 /* Special exception: R4[04]00 uses also the divec space. */ 1819 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1820 else if (cpu_has_4kex) 1821 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); 1822 else 1823 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1824 1825 local_flush_icache_range(ebase, ebase + 0x400); 1826 flush_tlb_handlers(); 1827 1828 sort_extable(__start___dbe_table, __stop___dbe_table); 1829 1830 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 1831 } 1832