1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 #include <linux/kgdb.h> 27 #include <linux/kdebug.h> 28 #include <linux/notifier.h> 29 30 #include <asm/bootinfo.h> 31 #include <asm/branch.h> 32 #include <asm/break.h> 33 #include <asm/cop2.h> 34 #include <asm/cpu.h> 35 #include <asm/dsp.h> 36 #include <asm/fpu.h> 37 #include <asm/fpu_emulator.h> 38 #include <asm/mipsregs.h> 39 #include <asm/mipsmtregs.h> 40 #include <asm/module.h> 41 #include <asm/pgtable.h> 42 #include <asm/ptrace.h> 43 #include <asm/sections.h> 44 #include <asm/system.h> 45 #include <asm/tlbdebug.h> 46 #include <asm/traps.h> 47 #include <asm/uaccess.h> 48 #include <asm/watch.h> 49 #include <asm/mmu_context.h> 50 #include <asm/types.h> 51 #include <asm/stacktrace.h> 52 #include <asm/irq.h> 53 #include <asm/uasm.h> 54 55 extern void check_wait(void); 56 extern asmlinkage void r4k_wait(void); 57 extern asmlinkage void rollback_handle_int(void); 58 extern asmlinkage void handle_int(void); 59 extern asmlinkage void handle_tlbm(void); 60 extern asmlinkage void handle_tlbl(void); 61 extern asmlinkage void handle_tlbs(void); 62 extern asmlinkage void handle_adel(void); 63 extern asmlinkage void handle_ades(void); 64 extern asmlinkage void handle_ibe(void); 65 extern asmlinkage void handle_dbe(void); 66 extern asmlinkage void handle_sys(void); 67 extern asmlinkage void handle_bp(void); 68 extern asmlinkage void handle_ri(void); 69 extern asmlinkage void handle_ri_rdhwr_vivt(void); 70 extern asmlinkage void handle_ri_rdhwr(void); 71 extern asmlinkage void handle_cpu(void); 72 extern asmlinkage void handle_ov(void); 73 extern asmlinkage void handle_tr(void); 74 extern asmlinkage void handle_fpe(void); 75 extern asmlinkage void handle_mdmx(void); 76 extern asmlinkage void handle_watch(void); 77 extern asmlinkage void handle_mt(void); 78 extern asmlinkage void handle_dsp(void); 79 extern asmlinkage void handle_mcheck(void); 80 extern asmlinkage void handle_reserved(void); 81 82 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 83 struct mips_fpu_struct *ctx, int has_fpu); 84 85 void (*board_be_init)(void); 86 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 87 void (*board_nmi_handler_setup)(void); 88 void (*board_ejtag_handler_setup)(void); 89 void (*board_bind_eic_interrupt)(int irq, int regset); 90 91 92 static void show_raw_backtrace(unsigned long reg29) 93 { 94 unsigned long *sp = (unsigned long *)(reg29 & ~3); 95 unsigned long addr; 96 97 printk("Call Trace:"); 98 #ifdef CONFIG_KALLSYMS 99 printk("\n"); 100 #endif 101 while (!kstack_end(sp)) { 102 unsigned long __user *p = 103 (unsigned long __user *)(unsigned long)sp++; 104 if (__get_user(addr, p)) { 105 printk(" (Bad stack address)"); 106 break; 107 } 108 if (__kernel_text_address(addr)) 109 print_ip_sym(addr); 110 } 111 printk("\n"); 112 } 113 114 #ifdef CONFIG_KALLSYMS 115 int raw_show_trace; 116 static int __init set_raw_show_trace(char *str) 117 { 118 raw_show_trace = 1; 119 return 1; 120 } 121 __setup("raw_show_trace", set_raw_show_trace); 122 #endif 123 124 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 125 { 126 unsigned long sp = regs->regs[29]; 127 unsigned long ra = regs->regs[31]; 128 unsigned long pc = regs->cp0_epc; 129 130 if (raw_show_trace || !__kernel_text_address(pc)) { 131 show_raw_backtrace(sp); 132 return; 133 } 134 printk("Call Trace:\n"); 135 do { 136 print_ip_sym(pc); 137 pc = unwind_stack(task, &sp, pc, &ra); 138 } while (pc); 139 printk("\n"); 140 } 141 142 /* 143 * This routine abuses get_user()/put_user() to reference pointers 144 * with at least a bit of error checking ... 145 */ 146 static void show_stacktrace(struct task_struct *task, 147 const struct pt_regs *regs) 148 { 149 const int field = 2 * sizeof(unsigned long); 150 long stackdata; 151 int i; 152 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 153 154 printk("Stack :"); 155 i = 0; 156 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 157 if (i && ((i % (64 / field)) == 0)) 158 printk("\n "); 159 if (i > 39) { 160 printk(" ..."); 161 break; 162 } 163 164 if (__get_user(stackdata, sp++)) { 165 printk(" (Bad stack address)"); 166 break; 167 } 168 169 printk(" %0*lx", field, stackdata); 170 i++; 171 } 172 printk("\n"); 173 show_backtrace(task, regs); 174 } 175 176 void show_stack(struct task_struct *task, unsigned long *sp) 177 { 178 struct pt_regs regs; 179 if (sp) { 180 regs.regs[29] = (unsigned long)sp; 181 regs.regs[31] = 0; 182 regs.cp0_epc = 0; 183 } else { 184 if (task && task != current) { 185 regs.regs[29] = task->thread.reg29; 186 regs.regs[31] = 0; 187 regs.cp0_epc = task->thread.reg31; 188 } else { 189 prepare_frametrace(®s); 190 } 191 } 192 show_stacktrace(task, ®s); 193 } 194 195 /* 196 * The architecture-independent dump_stack generator 197 */ 198 void dump_stack(void) 199 { 200 struct pt_regs regs; 201 202 prepare_frametrace(®s); 203 show_backtrace(current, ®s); 204 } 205 206 EXPORT_SYMBOL(dump_stack); 207 208 static void show_code(unsigned int __user *pc) 209 { 210 long i; 211 unsigned short __user *pc16 = NULL; 212 213 printk("\nCode:"); 214 215 if ((unsigned long)pc & 1) 216 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 217 for(i = -3 ; i < 6 ; i++) { 218 unsigned int insn; 219 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 220 printk(" (Bad address in epc)\n"); 221 break; 222 } 223 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 224 } 225 } 226 227 static void __show_regs(const struct pt_regs *regs) 228 { 229 const int field = 2 * sizeof(unsigned long); 230 unsigned int cause = regs->cp0_cause; 231 int i; 232 233 printk("Cpu %d\n", smp_processor_id()); 234 235 /* 236 * Saved main processor registers 237 */ 238 for (i = 0; i < 32; ) { 239 if ((i % 4) == 0) 240 printk("$%2d :", i); 241 if (i == 0) 242 printk(" %0*lx", field, 0UL); 243 else if (i == 26 || i == 27) 244 printk(" %*s", field, ""); 245 else 246 printk(" %0*lx", field, regs->regs[i]); 247 248 i++; 249 if ((i % 4) == 0) 250 printk("\n"); 251 } 252 253 #ifdef CONFIG_CPU_HAS_SMARTMIPS 254 printk("Acx : %0*lx\n", field, regs->acx); 255 #endif 256 printk("Hi : %0*lx\n", field, regs->hi); 257 printk("Lo : %0*lx\n", field, regs->lo); 258 259 /* 260 * Saved cp0 registers 261 */ 262 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 263 (void *) regs->cp0_epc); 264 printk(" %s\n", print_tainted()); 265 printk("ra : %0*lx %pS\n", field, regs->regs[31], 266 (void *) regs->regs[31]); 267 268 printk("Status: %08x ", (uint32_t) regs->cp0_status); 269 270 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 271 if (regs->cp0_status & ST0_KUO) 272 printk("KUo "); 273 if (regs->cp0_status & ST0_IEO) 274 printk("IEo "); 275 if (regs->cp0_status & ST0_KUP) 276 printk("KUp "); 277 if (regs->cp0_status & ST0_IEP) 278 printk("IEp "); 279 if (regs->cp0_status & ST0_KUC) 280 printk("KUc "); 281 if (regs->cp0_status & ST0_IEC) 282 printk("IEc "); 283 } else { 284 if (regs->cp0_status & ST0_KX) 285 printk("KX "); 286 if (regs->cp0_status & ST0_SX) 287 printk("SX "); 288 if (regs->cp0_status & ST0_UX) 289 printk("UX "); 290 switch (regs->cp0_status & ST0_KSU) { 291 case KSU_USER: 292 printk("USER "); 293 break; 294 case KSU_SUPERVISOR: 295 printk("SUPERVISOR "); 296 break; 297 case KSU_KERNEL: 298 printk("KERNEL "); 299 break; 300 default: 301 printk("BAD_MODE "); 302 break; 303 } 304 if (regs->cp0_status & ST0_ERL) 305 printk("ERL "); 306 if (regs->cp0_status & ST0_EXL) 307 printk("EXL "); 308 if (regs->cp0_status & ST0_IE) 309 printk("IE "); 310 } 311 printk("\n"); 312 313 printk("Cause : %08x\n", cause); 314 315 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 316 if (1 <= cause && cause <= 5) 317 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 318 319 printk("PrId : %08x (%s)\n", read_c0_prid(), 320 cpu_name_string()); 321 } 322 323 /* 324 * FIXME: really the generic show_regs should take a const pointer argument. 325 */ 326 void show_regs(struct pt_regs *regs) 327 { 328 __show_regs((struct pt_regs *)regs); 329 } 330 331 void show_registers(const struct pt_regs *regs) 332 { 333 const int field = 2 * sizeof(unsigned long); 334 335 __show_regs(regs); 336 print_modules(); 337 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 338 current->comm, current->pid, current_thread_info(), current, 339 field, current_thread_info()->tp_value); 340 if (cpu_has_userlocal) { 341 unsigned long tls; 342 343 tls = read_c0_userlocal(); 344 if (tls != current_thread_info()->tp_value) 345 printk("*HwTLS: %0*lx\n", field, tls); 346 } 347 348 show_stacktrace(current, regs); 349 show_code((unsigned int __user *) regs->cp0_epc); 350 printk("\n"); 351 } 352 353 static DEFINE_SPINLOCK(die_lock); 354 355 void __noreturn die(const char * str, struct pt_regs * regs) 356 { 357 static int die_counter; 358 int sig = SIGSEGV; 359 #ifdef CONFIG_MIPS_MT_SMTC 360 unsigned long dvpret = dvpe(); 361 #endif /* CONFIG_MIPS_MT_SMTC */ 362 363 console_verbose(); 364 spin_lock_irq(&die_lock); 365 bust_spinlocks(1); 366 #ifdef CONFIG_MIPS_MT_SMTC 367 mips_mt_regdump(dvpret); 368 #endif /* CONFIG_MIPS_MT_SMTC */ 369 370 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) 371 sig = 0; 372 373 printk("%s[#%d]:\n", str, ++die_counter); 374 show_registers(regs); 375 add_taint(TAINT_DIE); 376 spin_unlock_irq(&die_lock); 377 378 if (in_interrupt()) 379 panic("Fatal exception in interrupt"); 380 381 if (panic_on_oops) { 382 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 383 ssleep(5); 384 panic("Fatal exception"); 385 } 386 387 do_exit(sig); 388 } 389 390 extern struct exception_table_entry __start___dbe_table[]; 391 extern struct exception_table_entry __stop___dbe_table[]; 392 393 __asm__( 394 " .section __dbe_table, \"a\"\n" 395 " .previous \n"); 396 397 /* Given an address, look for it in the exception tables. */ 398 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 399 { 400 const struct exception_table_entry *e; 401 402 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 403 if (!e) 404 e = search_module_dbetables(addr); 405 return e; 406 } 407 408 asmlinkage void do_be(struct pt_regs *regs) 409 { 410 const int field = 2 * sizeof(unsigned long); 411 const struct exception_table_entry *fixup = NULL; 412 int data = regs->cp0_cause & 4; 413 int action = MIPS_BE_FATAL; 414 415 /* XXX For now. Fixme, this searches the wrong table ... */ 416 if (data && !user_mode(regs)) 417 fixup = search_dbe_tables(exception_epc(regs)); 418 419 if (fixup) 420 action = MIPS_BE_FIXUP; 421 422 if (board_be_handler) 423 action = board_be_handler(regs, fixup != NULL); 424 425 switch (action) { 426 case MIPS_BE_DISCARD: 427 return; 428 case MIPS_BE_FIXUP: 429 if (fixup) { 430 regs->cp0_epc = fixup->nextinsn; 431 return; 432 } 433 break; 434 default: 435 break; 436 } 437 438 /* 439 * Assume it would be too dangerous to continue ... 440 */ 441 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 442 data ? "Data" : "Instruction", 443 field, regs->cp0_epc, field, regs->regs[31]); 444 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) 445 == NOTIFY_STOP) 446 return; 447 448 die_if_kernel("Oops", regs); 449 force_sig(SIGBUS, current); 450 } 451 452 /* 453 * ll/sc, rdhwr, sync emulation 454 */ 455 456 #define OPCODE 0xfc000000 457 #define BASE 0x03e00000 458 #define RT 0x001f0000 459 #define OFFSET 0x0000ffff 460 #define LL 0xc0000000 461 #define SC 0xe0000000 462 #define SPEC0 0x00000000 463 #define SPEC3 0x7c000000 464 #define RD 0x0000f800 465 #define FUNC 0x0000003f 466 #define SYNC 0x0000000f 467 #define RDHWR 0x0000003b 468 469 /* 470 * The ll_bit is cleared by r*_switch.S 471 */ 472 473 unsigned int ll_bit; 474 struct task_struct *ll_task; 475 476 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 477 { 478 unsigned long value, __user *vaddr; 479 long offset; 480 481 /* 482 * analyse the ll instruction that just caused a ri exception 483 * and put the referenced address to addr. 484 */ 485 486 /* sign extend offset */ 487 offset = opcode & OFFSET; 488 offset <<= 16; 489 offset >>= 16; 490 491 vaddr = (unsigned long __user *) 492 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 493 494 if ((unsigned long)vaddr & 3) 495 return SIGBUS; 496 if (get_user(value, vaddr)) 497 return SIGSEGV; 498 499 preempt_disable(); 500 501 if (ll_task == NULL || ll_task == current) { 502 ll_bit = 1; 503 } else { 504 ll_bit = 0; 505 } 506 ll_task = current; 507 508 preempt_enable(); 509 510 regs->regs[(opcode & RT) >> 16] = value; 511 512 return 0; 513 } 514 515 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 516 { 517 unsigned long __user *vaddr; 518 unsigned long reg; 519 long offset; 520 521 /* 522 * analyse the sc instruction that just caused a ri exception 523 * and put the referenced address to addr. 524 */ 525 526 /* sign extend offset */ 527 offset = opcode & OFFSET; 528 offset <<= 16; 529 offset >>= 16; 530 531 vaddr = (unsigned long __user *) 532 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 533 reg = (opcode & RT) >> 16; 534 535 if ((unsigned long)vaddr & 3) 536 return SIGBUS; 537 538 preempt_disable(); 539 540 if (ll_bit == 0 || ll_task != current) { 541 regs->regs[reg] = 0; 542 preempt_enable(); 543 return 0; 544 } 545 546 preempt_enable(); 547 548 if (put_user(regs->regs[reg], vaddr)) 549 return SIGSEGV; 550 551 regs->regs[reg] = 1; 552 553 return 0; 554 } 555 556 /* 557 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 558 * opcodes are supposed to result in coprocessor unusable exceptions if 559 * executed on ll/sc-less processors. That's the theory. In practice a 560 * few processors such as NEC's VR4100 throw reserved instruction exceptions 561 * instead, so we're doing the emulation thing in both exception handlers. 562 */ 563 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 564 { 565 if ((opcode & OPCODE) == LL) 566 return simulate_ll(regs, opcode); 567 if ((opcode & OPCODE) == SC) 568 return simulate_sc(regs, opcode); 569 570 return -1; /* Must be something else ... */ 571 } 572 573 /* 574 * Simulate trapping 'rdhwr' instructions to provide user accessible 575 * registers not implemented in hardware. 576 */ 577 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 578 { 579 struct thread_info *ti = task_thread_info(current); 580 581 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 582 int rd = (opcode & RD) >> 11; 583 int rt = (opcode & RT) >> 16; 584 switch (rd) { 585 case 0: /* CPU number */ 586 regs->regs[rt] = smp_processor_id(); 587 return 0; 588 case 1: /* SYNCI length */ 589 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 590 current_cpu_data.icache.linesz); 591 return 0; 592 case 2: /* Read count register */ 593 regs->regs[rt] = read_c0_count(); 594 return 0; 595 case 3: /* Count register resolution */ 596 switch (current_cpu_data.cputype) { 597 case CPU_20KC: 598 case CPU_25KF: 599 regs->regs[rt] = 1; 600 break; 601 default: 602 regs->regs[rt] = 2; 603 } 604 return 0; 605 case 29: 606 regs->regs[rt] = ti->tp_value; 607 return 0; 608 default: 609 return -1; 610 } 611 } 612 613 /* Not ours. */ 614 return -1; 615 } 616 617 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 618 { 619 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 620 return 0; 621 622 return -1; /* Must be something else ... */ 623 } 624 625 asmlinkage void do_ov(struct pt_regs *regs) 626 { 627 siginfo_t info; 628 629 die_if_kernel("Integer overflow", regs); 630 631 info.si_code = FPE_INTOVF; 632 info.si_signo = SIGFPE; 633 info.si_errno = 0; 634 info.si_addr = (void __user *) regs->cp0_epc; 635 force_sig_info(SIGFPE, &info, current); 636 } 637 638 /* 639 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 640 */ 641 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 642 { 643 siginfo_t info; 644 645 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) 646 == NOTIFY_STOP) 647 return; 648 die_if_kernel("FP exception in kernel code", regs); 649 650 if (fcr31 & FPU_CSR_UNI_X) { 651 int sig; 652 653 /* 654 * Unimplemented operation exception. If we've got the full 655 * software emulator on-board, let's use it... 656 * 657 * Force FPU to dump state into task/thread context. We're 658 * moving a lot of data here for what is probably a single 659 * instruction, but the alternative is to pre-decode the FP 660 * register operands before invoking the emulator, which seems 661 * a bit extreme for what should be an infrequent event. 662 */ 663 /* Ensure 'resume' not overwrite saved fp context again. */ 664 lose_fpu(1); 665 666 /* Run the emulator */ 667 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 668 669 /* 670 * We can't allow the emulated instruction to leave any of 671 * the cause bit set in $fcr31. 672 */ 673 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 674 675 /* Restore the hardware register state */ 676 own_fpu(1); /* Using the FPU again. */ 677 678 /* If something went wrong, signal */ 679 if (sig) 680 force_sig(sig, current); 681 682 return; 683 } else if (fcr31 & FPU_CSR_INV_X) 684 info.si_code = FPE_FLTINV; 685 else if (fcr31 & FPU_CSR_DIV_X) 686 info.si_code = FPE_FLTDIV; 687 else if (fcr31 & FPU_CSR_OVF_X) 688 info.si_code = FPE_FLTOVF; 689 else if (fcr31 & FPU_CSR_UDF_X) 690 info.si_code = FPE_FLTUND; 691 else if (fcr31 & FPU_CSR_INE_X) 692 info.si_code = FPE_FLTRES; 693 else 694 info.si_code = __SI_FAULT; 695 info.si_signo = SIGFPE; 696 info.si_errno = 0; 697 info.si_addr = (void __user *) regs->cp0_epc; 698 force_sig_info(SIGFPE, &info, current); 699 } 700 701 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 702 const char *str) 703 { 704 siginfo_t info; 705 char b[40]; 706 707 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 708 return; 709 710 /* 711 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 712 * insns, even for trap and break codes that indicate arithmetic 713 * failures. Weird ... 714 * But should we continue the brokenness??? --macro 715 */ 716 switch (code) { 717 case BRK_OVERFLOW: 718 case BRK_DIVZERO: 719 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 720 die_if_kernel(b, regs); 721 if (code == BRK_DIVZERO) 722 info.si_code = FPE_INTDIV; 723 else 724 info.si_code = FPE_INTOVF; 725 info.si_signo = SIGFPE; 726 info.si_errno = 0; 727 info.si_addr = (void __user *) regs->cp0_epc; 728 force_sig_info(SIGFPE, &info, current); 729 break; 730 case BRK_BUG: 731 die_if_kernel("Kernel bug detected", regs); 732 force_sig(SIGTRAP, current); 733 break; 734 case BRK_MEMU: 735 /* 736 * Address errors may be deliberately induced by the FPU 737 * emulator to retake control of the CPU after executing the 738 * instruction in the delay slot of an emulated branch. 739 * 740 * Terminate if exception was recognized as a delay slot return 741 * otherwise handle as normal. 742 */ 743 if (do_dsemulret(regs)) 744 return; 745 746 die_if_kernel("Math emu break/trap", regs); 747 force_sig(SIGTRAP, current); 748 break; 749 default: 750 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 751 die_if_kernel(b, regs); 752 force_sig(SIGTRAP, current); 753 } 754 } 755 756 asmlinkage void do_bp(struct pt_regs *regs) 757 { 758 unsigned int opcode, bcode; 759 760 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 761 goto out_sigsegv; 762 763 /* 764 * There is the ancient bug in the MIPS assemblers that the break 765 * code starts left to bit 16 instead to bit 6 in the opcode. 766 * Gas is bug-compatible, but not always, grrr... 767 * We handle both cases with a simple heuristics. --macro 768 */ 769 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 770 if (bcode >= (1 << 10)) 771 bcode >>= 10; 772 773 do_trap_or_bp(regs, bcode, "Break"); 774 return; 775 776 out_sigsegv: 777 force_sig(SIGSEGV, current); 778 } 779 780 asmlinkage void do_tr(struct pt_regs *regs) 781 { 782 unsigned int opcode, tcode = 0; 783 784 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 785 goto out_sigsegv; 786 787 /* Immediate versions don't provide a code. */ 788 if (!(opcode & OPCODE)) 789 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 790 791 do_trap_or_bp(regs, tcode, "Trap"); 792 return; 793 794 out_sigsegv: 795 force_sig(SIGSEGV, current); 796 } 797 798 asmlinkage void do_ri(struct pt_regs *regs) 799 { 800 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 801 unsigned long old_epc = regs->cp0_epc; 802 unsigned int opcode = 0; 803 int status = -1; 804 805 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) 806 == NOTIFY_STOP) 807 return; 808 809 die_if_kernel("Reserved instruction in kernel code", regs); 810 811 if (unlikely(compute_return_epc(regs) < 0)) 812 return; 813 814 if (unlikely(get_user(opcode, epc) < 0)) 815 status = SIGSEGV; 816 817 if (!cpu_has_llsc && status < 0) 818 status = simulate_llsc(regs, opcode); 819 820 if (status < 0) 821 status = simulate_rdhwr(regs, opcode); 822 823 if (status < 0) 824 status = simulate_sync(regs, opcode); 825 826 if (status < 0) 827 status = SIGILL; 828 829 if (unlikely(status > 0)) { 830 regs->cp0_epc = old_epc; /* Undo skip-over. */ 831 force_sig(status, current); 832 } 833 } 834 835 /* 836 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 837 * emulated more than some threshold number of instructions, force migration to 838 * a "CPU" that has FP support. 839 */ 840 static void mt_ase_fp_affinity(void) 841 { 842 #ifdef CONFIG_MIPS_MT_FPAFF 843 if (mt_fpemul_threshold > 0 && 844 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 845 /* 846 * If there's no FPU present, or if the application has already 847 * restricted the allowed set to exclude any CPUs with FPUs, 848 * we'll skip the procedure. 849 */ 850 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 851 cpumask_t tmask; 852 853 current->thread.user_cpus_allowed 854 = current->cpus_allowed; 855 cpus_and(tmask, current->cpus_allowed, 856 mt_fpu_cpumask); 857 set_cpus_allowed(current, tmask); 858 set_thread_flag(TIF_FPUBOUND); 859 } 860 } 861 #endif /* CONFIG_MIPS_MT_FPAFF */ 862 } 863 864 /* 865 * No lock; only written during early bootup by CPU 0. 866 */ 867 static RAW_NOTIFIER_HEAD(cu2_chain); 868 869 int __ref register_cu2_notifier(struct notifier_block *nb) 870 { 871 return raw_notifier_chain_register(&cu2_chain, nb); 872 } 873 874 int cu2_notifier_call_chain(unsigned long val, void *v) 875 { 876 return raw_notifier_call_chain(&cu2_chain, val, v); 877 } 878 879 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 880 void *data) 881 { 882 struct pt_regs *regs = data; 883 884 switch (action) { 885 default: 886 die_if_kernel("Unhandled kernel unaligned access or invalid " 887 "instruction", regs); 888 /* Fall through */ 889 890 case CU2_EXCEPTION: 891 force_sig(SIGILL, current); 892 } 893 894 return NOTIFY_OK; 895 } 896 897 static struct notifier_block default_cu2_notifier = { 898 .notifier_call = default_cu2_call, 899 .priority = 0x80000000, /* Run last */ 900 }; 901 902 asmlinkage void do_cpu(struct pt_regs *regs) 903 { 904 unsigned int __user *epc; 905 unsigned long old_epc; 906 unsigned int opcode; 907 unsigned int cpid; 908 int status; 909 unsigned long __maybe_unused flags; 910 911 die_if_kernel("do_cpu invoked from kernel context!", regs); 912 913 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 914 915 switch (cpid) { 916 case 0: 917 epc = (unsigned int __user *)exception_epc(regs); 918 old_epc = regs->cp0_epc; 919 opcode = 0; 920 status = -1; 921 922 if (unlikely(compute_return_epc(regs) < 0)) 923 return; 924 925 if (unlikely(get_user(opcode, epc) < 0)) 926 status = SIGSEGV; 927 928 if (!cpu_has_llsc && status < 0) 929 status = simulate_llsc(regs, opcode); 930 931 if (status < 0) 932 status = simulate_rdhwr(regs, opcode); 933 934 if (status < 0) 935 status = SIGILL; 936 937 if (unlikely(status > 0)) { 938 regs->cp0_epc = old_epc; /* Undo skip-over. */ 939 force_sig(status, current); 940 } 941 942 return; 943 944 case 1: 945 if (used_math()) /* Using the FPU again. */ 946 own_fpu(1); 947 else { /* First time FPU user. */ 948 init_fpu(); 949 set_used_math(); 950 } 951 952 if (!raw_cpu_has_fpu) { 953 int sig; 954 sig = fpu_emulator_cop1Handler(regs, 955 ¤t->thread.fpu, 0); 956 if (sig) 957 force_sig(sig, current); 958 else 959 mt_ase_fp_affinity(); 960 } 961 962 return; 963 964 case 2: 965 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 966 break; 967 968 case 3: 969 break; 970 } 971 972 force_sig(SIGILL, current); 973 } 974 975 asmlinkage void do_mdmx(struct pt_regs *regs) 976 { 977 force_sig(SIGILL, current); 978 } 979 980 /* 981 * Called with interrupts disabled. 982 */ 983 asmlinkage void do_watch(struct pt_regs *regs) 984 { 985 u32 cause; 986 987 /* 988 * Clear WP (bit 22) bit of cause register so we don't loop 989 * forever. 990 */ 991 cause = read_c0_cause(); 992 cause &= ~(1 << 22); 993 write_c0_cause(cause); 994 995 /* 996 * If the current thread has the watch registers loaded, save 997 * their values and send SIGTRAP. Otherwise another thread 998 * left the registers set, clear them and continue. 999 */ 1000 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1001 mips_read_watch_registers(); 1002 local_irq_enable(); 1003 force_sig(SIGTRAP, current); 1004 } else { 1005 mips_clear_watch_registers(); 1006 local_irq_enable(); 1007 } 1008 } 1009 1010 asmlinkage void do_mcheck(struct pt_regs *regs) 1011 { 1012 const int field = 2 * sizeof(unsigned long); 1013 int multi_match = regs->cp0_status & ST0_TS; 1014 1015 show_regs(regs); 1016 1017 if (multi_match) { 1018 printk("Index : %0x\n", read_c0_index()); 1019 printk("Pagemask: %0x\n", read_c0_pagemask()); 1020 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1021 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1022 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1023 printk("\n"); 1024 dump_tlb_all(); 1025 } 1026 1027 show_code((unsigned int __user *) regs->cp0_epc); 1028 1029 /* 1030 * Some chips may have other causes of machine check (e.g. SB1 1031 * graduation timer) 1032 */ 1033 panic("Caught Machine Check exception - %scaused by multiple " 1034 "matching entries in the TLB.", 1035 (multi_match) ? "" : "not "); 1036 } 1037 1038 asmlinkage void do_mt(struct pt_regs *regs) 1039 { 1040 int subcode; 1041 1042 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1043 >> VPECONTROL_EXCPT_SHIFT; 1044 switch (subcode) { 1045 case 0: 1046 printk(KERN_DEBUG "Thread Underflow\n"); 1047 break; 1048 case 1: 1049 printk(KERN_DEBUG "Thread Overflow\n"); 1050 break; 1051 case 2: 1052 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1053 break; 1054 case 3: 1055 printk(KERN_DEBUG "Gating Storage Exception\n"); 1056 break; 1057 case 4: 1058 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1059 break; 1060 case 5: 1061 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 1062 break; 1063 default: 1064 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1065 subcode); 1066 break; 1067 } 1068 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1069 1070 force_sig(SIGILL, current); 1071 } 1072 1073 1074 asmlinkage void do_dsp(struct pt_regs *regs) 1075 { 1076 if (cpu_has_dsp) 1077 panic("Unexpected DSP exception\n"); 1078 1079 force_sig(SIGILL, current); 1080 } 1081 1082 asmlinkage void do_reserved(struct pt_regs *regs) 1083 { 1084 /* 1085 * Game over - no way to handle this if it ever occurs. Most probably 1086 * caused by a new unknown cpu type or after another deadly 1087 * hard/software error. 1088 */ 1089 show_regs(regs); 1090 panic("Caught reserved exception %ld - should not happen.", 1091 (regs->cp0_cause & 0x7f) >> 2); 1092 } 1093 1094 static int __initdata l1parity = 1; 1095 static int __init nol1parity(char *s) 1096 { 1097 l1parity = 0; 1098 return 1; 1099 } 1100 __setup("nol1par", nol1parity); 1101 static int __initdata l2parity = 1; 1102 static int __init nol2parity(char *s) 1103 { 1104 l2parity = 0; 1105 return 1; 1106 } 1107 __setup("nol2par", nol2parity); 1108 1109 /* 1110 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1111 * it different ways. 1112 */ 1113 static inline void parity_protection_init(void) 1114 { 1115 switch (current_cpu_type()) { 1116 case CPU_24K: 1117 case CPU_34K: 1118 case CPU_74K: 1119 case CPU_1004K: 1120 { 1121 #define ERRCTL_PE 0x80000000 1122 #define ERRCTL_L2P 0x00800000 1123 unsigned long errctl; 1124 unsigned int l1parity_present, l2parity_present; 1125 1126 errctl = read_c0_ecc(); 1127 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1128 1129 /* probe L1 parity support */ 1130 write_c0_ecc(errctl | ERRCTL_PE); 1131 back_to_back_c0_hazard(); 1132 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1133 1134 /* probe L2 parity support */ 1135 write_c0_ecc(errctl|ERRCTL_L2P); 1136 back_to_back_c0_hazard(); 1137 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1138 1139 if (l1parity_present && l2parity_present) { 1140 if (l1parity) 1141 errctl |= ERRCTL_PE; 1142 if (l1parity ^ l2parity) 1143 errctl |= ERRCTL_L2P; 1144 } else if (l1parity_present) { 1145 if (l1parity) 1146 errctl |= ERRCTL_PE; 1147 } else if (l2parity_present) { 1148 if (l2parity) 1149 errctl |= ERRCTL_L2P; 1150 } else { 1151 /* No parity available */ 1152 } 1153 1154 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1155 1156 write_c0_ecc(errctl); 1157 back_to_back_c0_hazard(); 1158 errctl = read_c0_ecc(); 1159 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1160 1161 if (l1parity_present) 1162 printk(KERN_INFO "Cache parity protection %sabled\n", 1163 (errctl & ERRCTL_PE) ? "en" : "dis"); 1164 1165 if (l2parity_present) { 1166 if (l1parity_present && l1parity) 1167 errctl ^= ERRCTL_L2P; 1168 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1169 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1170 } 1171 } 1172 break; 1173 1174 case CPU_5KC: 1175 write_c0_ecc(0x80000000); 1176 back_to_back_c0_hazard(); 1177 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1178 printk(KERN_INFO "Cache parity protection %sabled\n", 1179 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1180 break; 1181 case CPU_20KC: 1182 case CPU_25KF: 1183 /* Clear the DE bit (bit 16) in the c0_status register. */ 1184 printk(KERN_INFO "Enable cache parity protection for " 1185 "MIPS 20KC/25KF CPUs.\n"); 1186 clear_c0_status(ST0_DE); 1187 break; 1188 default: 1189 break; 1190 } 1191 } 1192 1193 asmlinkage void cache_parity_error(void) 1194 { 1195 const int field = 2 * sizeof(unsigned long); 1196 unsigned int reg_val; 1197 1198 /* For the moment, report the problem and hang. */ 1199 printk("Cache error exception:\n"); 1200 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1201 reg_val = read_c0_cacheerr(); 1202 printk("c0_cacheerr == %08x\n", reg_val); 1203 1204 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1205 reg_val & (1<<30) ? "secondary" : "primary", 1206 reg_val & (1<<31) ? "data" : "insn"); 1207 printk("Error bits: %s%s%s%s%s%s%s\n", 1208 reg_val & (1<<29) ? "ED " : "", 1209 reg_val & (1<<28) ? "ET " : "", 1210 reg_val & (1<<26) ? "EE " : "", 1211 reg_val & (1<<25) ? "EB " : "", 1212 reg_val & (1<<24) ? "EI " : "", 1213 reg_val & (1<<23) ? "E1 " : "", 1214 reg_val & (1<<22) ? "E0 " : ""); 1215 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1216 1217 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1218 if (reg_val & (1<<22)) 1219 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1220 1221 if (reg_val & (1<<23)) 1222 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1223 #endif 1224 1225 panic("Can't handle the cache error!"); 1226 } 1227 1228 /* 1229 * SDBBP EJTAG debug exception handler. 1230 * We skip the instruction and return to the next instruction. 1231 */ 1232 void ejtag_exception_handler(struct pt_regs *regs) 1233 { 1234 const int field = 2 * sizeof(unsigned long); 1235 unsigned long depc, old_epc; 1236 unsigned int debug; 1237 1238 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1239 depc = read_c0_depc(); 1240 debug = read_c0_debug(); 1241 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1242 if (debug & 0x80000000) { 1243 /* 1244 * In branch delay slot. 1245 * We cheat a little bit here and use EPC to calculate the 1246 * debug return address (DEPC). EPC is restored after the 1247 * calculation. 1248 */ 1249 old_epc = regs->cp0_epc; 1250 regs->cp0_epc = depc; 1251 __compute_return_epc(regs); 1252 depc = regs->cp0_epc; 1253 regs->cp0_epc = old_epc; 1254 } else 1255 depc += 4; 1256 write_c0_depc(depc); 1257 1258 #if 0 1259 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1260 write_c0_debug(debug | 0x100); 1261 #endif 1262 } 1263 1264 /* 1265 * NMI exception handler. 1266 */ 1267 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1268 { 1269 bust_spinlocks(1); 1270 printk("NMI taken!!!!\n"); 1271 die("NMI", regs); 1272 } 1273 1274 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1275 1276 unsigned long ebase; 1277 unsigned long exception_handlers[32]; 1278 unsigned long vi_handlers[64]; 1279 1280 void __init *set_except_vector(int n, void *addr) 1281 { 1282 unsigned long handler = (unsigned long) addr; 1283 unsigned long old_handler = exception_handlers[n]; 1284 1285 exception_handlers[n] = handler; 1286 if (n == 0 && cpu_has_divec) { 1287 unsigned long jump_mask = ~((1 << 28) - 1); 1288 u32 *buf = (u32 *)(ebase + 0x200); 1289 unsigned int k0 = 26; 1290 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1291 uasm_i_j(&buf, handler & ~jump_mask); 1292 uasm_i_nop(&buf); 1293 } else { 1294 UASM_i_LA(&buf, k0, handler); 1295 uasm_i_jr(&buf, k0); 1296 uasm_i_nop(&buf); 1297 } 1298 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1299 } 1300 return (void *)old_handler; 1301 } 1302 1303 static asmlinkage void do_default_vi(void) 1304 { 1305 show_regs(get_irq_regs()); 1306 panic("Caught unexpected vectored interrupt."); 1307 } 1308 1309 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1310 { 1311 unsigned long handler; 1312 unsigned long old_handler = vi_handlers[n]; 1313 int srssets = current_cpu_data.srsets; 1314 u32 *w; 1315 unsigned char *b; 1316 1317 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1318 1319 if (addr == NULL) { 1320 handler = (unsigned long) do_default_vi; 1321 srs = 0; 1322 } else 1323 handler = (unsigned long) addr; 1324 vi_handlers[n] = (unsigned long) addr; 1325 1326 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1327 1328 if (srs >= srssets) 1329 panic("Shadow register set %d not supported", srs); 1330 1331 if (cpu_has_veic) { 1332 if (board_bind_eic_interrupt) 1333 board_bind_eic_interrupt(n, srs); 1334 } else if (cpu_has_vint) { 1335 /* SRSMap is only defined if shadow sets are implemented */ 1336 if (srssets > 1) 1337 change_c0_srsmap(0xf << n*4, srs << n*4); 1338 } 1339 1340 if (srs == 0) { 1341 /* 1342 * If no shadow set is selected then use the default handler 1343 * that does normal register saving and a standard interrupt exit 1344 */ 1345 1346 extern char except_vec_vi, except_vec_vi_lui; 1347 extern char except_vec_vi_ori, except_vec_vi_end; 1348 extern char rollback_except_vec_vi; 1349 char *vec_start = (cpu_wait == r4k_wait) ? 1350 &rollback_except_vec_vi : &except_vec_vi; 1351 #ifdef CONFIG_MIPS_MT_SMTC 1352 /* 1353 * We need to provide the SMTC vectored interrupt handler 1354 * not only with the address of the handler, but with the 1355 * Status.IM bit to be masked before going there. 1356 */ 1357 extern char except_vec_vi_mori; 1358 const int mori_offset = &except_vec_vi_mori - vec_start; 1359 #endif /* CONFIG_MIPS_MT_SMTC */ 1360 const int handler_len = &except_vec_vi_end - vec_start; 1361 const int lui_offset = &except_vec_vi_lui - vec_start; 1362 const int ori_offset = &except_vec_vi_ori - vec_start; 1363 1364 if (handler_len > VECTORSPACING) { 1365 /* 1366 * Sigh... panicing won't help as the console 1367 * is probably not configured :( 1368 */ 1369 panic("VECTORSPACING too small"); 1370 } 1371 1372 memcpy(b, vec_start, handler_len); 1373 #ifdef CONFIG_MIPS_MT_SMTC 1374 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1375 1376 w = (u32 *)(b + mori_offset); 1377 *w = (*w & 0xffff0000) | (0x100 << n); 1378 #endif /* CONFIG_MIPS_MT_SMTC */ 1379 w = (u32 *)(b + lui_offset); 1380 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1381 w = (u32 *)(b + ori_offset); 1382 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1383 local_flush_icache_range((unsigned long)b, 1384 (unsigned long)(b+handler_len)); 1385 } 1386 else { 1387 /* 1388 * In other cases jump directly to the interrupt handler 1389 * 1390 * It is the handlers responsibility to save registers if required 1391 * (eg hi/lo) and return from the exception using "eret" 1392 */ 1393 w = (u32 *)b; 1394 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1395 *w = 0; 1396 local_flush_icache_range((unsigned long)b, 1397 (unsigned long)(b+8)); 1398 } 1399 1400 return (void *)old_handler; 1401 } 1402 1403 void *set_vi_handler(int n, vi_handler_t addr) 1404 { 1405 return set_vi_srs_handler(n, addr, 0); 1406 } 1407 1408 extern void cpu_cache_init(void); 1409 extern void tlb_init(void); 1410 extern void flush_tlb_handlers(void); 1411 1412 /* 1413 * Timer interrupt 1414 */ 1415 int cp0_compare_irq; 1416 int cp0_compare_irq_shift; 1417 1418 /* 1419 * Performance counter IRQ or -1 if shared with timer 1420 */ 1421 int cp0_perfcount_irq; 1422 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1423 1424 static int __cpuinitdata noulri; 1425 1426 static int __init ulri_disable(char *s) 1427 { 1428 pr_info("Disabling ulri\n"); 1429 noulri = 1; 1430 1431 return 1; 1432 } 1433 __setup("noulri", ulri_disable); 1434 1435 void __cpuinit per_cpu_trap_init(void) 1436 { 1437 unsigned int cpu = smp_processor_id(); 1438 unsigned int status_set = ST0_CU0; 1439 #ifdef CONFIG_MIPS_MT_SMTC 1440 int secondaryTC = 0; 1441 int bootTC = (cpu == 0); 1442 1443 /* 1444 * Only do per_cpu_trap_init() for first TC of Each VPE. 1445 * Note that this hack assumes that the SMTC init code 1446 * assigns TCs consecutively and in ascending order. 1447 */ 1448 1449 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1450 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1451 secondaryTC = 1; 1452 #endif /* CONFIG_MIPS_MT_SMTC */ 1453 1454 /* 1455 * Disable coprocessors and select 32-bit or 64-bit addressing 1456 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1457 * flag that some firmware may have left set and the TS bit (for 1458 * IP27). Set XX for ISA IV code to work. 1459 */ 1460 #ifdef CONFIG_64BIT 1461 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1462 #endif 1463 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1464 status_set |= ST0_XX; 1465 if (cpu_has_dsp) 1466 status_set |= ST0_MX; 1467 1468 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1469 status_set); 1470 1471 if (cpu_has_mips_r2) { 1472 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits; 1473 1474 if (!noulri && cpu_has_userlocal) 1475 enable |= (1 << 29); 1476 1477 write_c0_hwrena(enable); 1478 } 1479 1480 #ifdef CONFIG_MIPS_MT_SMTC 1481 if (!secondaryTC) { 1482 #endif /* CONFIG_MIPS_MT_SMTC */ 1483 1484 if (cpu_has_veic || cpu_has_vint) { 1485 unsigned long sr = set_c0_status(ST0_BEV); 1486 write_c0_ebase(ebase); 1487 write_c0_status(sr); 1488 /* Setting vector spacing enables EI/VI mode */ 1489 change_c0_intctl(0x3e0, VECTORSPACING); 1490 } 1491 if (cpu_has_divec) { 1492 if (cpu_has_mipsmt) { 1493 unsigned int vpflags = dvpe(); 1494 set_c0_cause(CAUSEF_IV); 1495 evpe(vpflags); 1496 } else 1497 set_c0_cause(CAUSEF_IV); 1498 } 1499 1500 /* 1501 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1502 * 1503 * o read IntCtl.IPTI to determine the timer interrupt 1504 * o read IntCtl.IPPCI to determine the performance counter interrupt 1505 */ 1506 if (cpu_has_mips_r2) { 1507 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1508 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1509 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1510 if (cp0_perfcount_irq == cp0_compare_irq) 1511 cp0_perfcount_irq = -1; 1512 } else { 1513 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1514 cp0_compare_irq_shift = cp0_compare_irq; 1515 cp0_perfcount_irq = -1; 1516 } 1517 1518 #ifdef CONFIG_MIPS_MT_SMTC 1519 } 1520 #endif /* CONFIG_MIPS_MT_SMTC */ 1521 1522 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1523 TLBMISS_HANDLER_SETUP(); 1524 1525 atomic_inc(&init_mm.mm_count); 1526 current->active_mm = &init_mm; 1527 BUG_ON(current->mm); 1528 enter_lazy_tlb(&init_mm, current); 1529 1530 #ifdef CONFIG_MIPS_MT_SMTC 1531 if (bootTC) { 1532 #endif /* CONFIG_MIPS_MT_SMTC */ 1533 cpu_cache_init(); 1534 tlb_init(); 1535 #ifdef CONFIG_MIPS_MT_SMTC 1536 } else if (!secondaryTC) { 1537 /* 1538 * First TC in non-boot VPE must do subset of tlb_init() 1539 * for MMU countrol registers. 1540 */ 1541 write_c0_pagemask(PM_DEFAULT_MASK); 1542 write_c0_wired(0); 1543 } 1544 #endif /* CONFIG_MIPS_MT_SMTC */ 1545 } 1546 1547 /* Install CPU exception handler */ 1548 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1549 { 1550 memcpy((void *)(ebase + offset), addr, size); 1551 local_flush_icache_range(ebase + offset, ebase + offset + size); 1552 } 1553 1554 static char panic_null_cerr[] __cpuinitdata = 1555 "Trying to set NULL cache error exception handler"; 1556 1557 /* 1558 * Install uncached CPU exception handler. 1559 * This is suitable only for the cache error exception which is the only 1560 * exception handler that is being run uncached. 1561 */ 1562 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1563 unsigned long size) 1564 { 1565 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1566 1567 if (!addr) 1568 panic(panic_null_cerr); 1569 1570 memcpy((void *)(uncached_ebase + offset), addr, size); 1571 } 1572 1573 static int __initdata rdhwr_noopt; 1574 static int __init set_rdhwr_noopt(char *str) 1575 { 1576 rdhwr_noopt = 1; 1577 return 1; 1578 } 1579 1580 __setup("rdhwr_noopt", set_rdhwr_noopt); 1581 1582 void __init trap_init(void) 1583 { 1584 extern char except_vec3_generic, except_vec3_r4000; 1585 extern char except_vec4; 1586 unsigned long i; 1587 int rollback; 1588 1589 check_wait(); 1590 rollback = (cpu_wait == r4k_wait); 1591 1592 #if defined(CONFIG_KGDB) 1593 if (kgdb_early_setup) 1594 return; /* Already done */ 1595 #endif 1596 1597 if (cpu_has_veic || cpu_has_vint) { 1598 unsigned long size = 0x200 + VECTORSPACING*64; 1599 ebase = (unsigned long) 1600 __alloc_bootmem(size, 1 << fls(size), 0); 1601 } else { 1602 ebase = CKSEG0; 1603 if (cpu_has_mips_r2) 1604 ebase += (read_c0_ebase() & 0x3ffff000); 1605 } 1606 1607 per_cpu_trap_init(); 1608 1609 /* 1610 * Copy the generic exception handlers to their final destination. 1611 * This will be overriden later as suitable for a particular 1612 * configuration. 1613 */ 1614 set_handler(0x180, &except_vec3_generic, 0x80); 1615 1616 /* 1617 * Setup default vectors 1618 */ 1619 for (i = 0; i <= 31; i++) 1620 set_except_vector(i, handle_reserved); 1621 1622 /* 1623 * Copy the EJTAG debug exception vector handler code to it's final 1624 * destination. 1625 */ 1626 if (cpu_has_ejtag && board_ejtag_handler_setup) 1627 board_ejtag_handler_setup(); 1628 1629 /* 1630 * Only some CPUs have the watch exceptions. 1631 */ 1632 if (cpu_has_watch) 1633 set_except_vector(23, handle_watch); 1634 1635 /* 1636 * Initialise interrupt handlers 1637 */ 1638 if (cpu_has_veic || cpu_has_vint) { 1639 int nvec = cpu_has_veic ? 64 : 8; 1640 for (i = 0; i < nvec; i++) 1641 set_vi_handler(i, NULL); 1642 } 1643 else if (cpu_has_divec) 1644 set_handler(0x200, &except_vec4, 0x8); 1645 1646 /* 1647 * Some CPUs can enable/disable for cache parity detection, but does 1648 * it different ways. 1649 */ 1650 parity_protection_init(); 1651 1652 /* 1653 * The Data Bus Errors / Instruction Bus Errors are signaled 1654 * by external hardware. Therefore these two exceptions 1655 * may have board specific handlers. 1656 */ 1657 if (board_be_init) 1658 board_be_init(); 1659 1660 set_except_vector(0, rollback ? rollback_handle_int : handle_int); 1661 set_except_vector(1, handle_tlbm); 1662 set_except_vector(2, handle_tlbl); 1663 set_except_vector(3, handle_tlbs); 1664 1665 set_except_vector(4, handle_adel); 1666 set_except_vector(5, handle_ades); 1667 1668 set_except_vector(6, handle_ibe); 1669 set_except_vector(7, handle_dbe); 1670 1671 set_except_vector(8, handle_sys); 1672 set_except_vector(9, handle_bp); 1673 set_except_vector(10, rdhwr_noopt ? handle_ri : 1674 (cpu_has_vtag_icache ? 1675 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1676 set_except_vector(11, handle_cpu); 1677 set_except_vector(12, handle_ov); 1678 set_except_vector(13, handle_tr); 1679 1680 if (current_cpu_type() == CPU_R6000 || 1681 current_cpu_type() == CPU_R6000A) { 1682 /* 1683 * The R6000 is the only R-series CPU that features a machine 1684 * check exception (similar to the R4000 cache error) and 1685 * unaligned ldc1/sdc1 exception. The handlers have not been 1686 * written yet. Well, anyway there is no R6000 machine on the 1687 * current list of targets for Linux/MIPS. 1688 * (Duh, crap, there is someone with a triple R6k machine) 1689 */ 1690 //set_except_vector(14, handle_mc); 1691 //set_except_vector(15, handle_ndc); 1692 } 1693 1694 1695 if (board_nmi_handler_setup) 1696 board_nmi_handler_setup(); 1697 1698 if (cpu_has_fpu && !cpu_has_nofpuex) 1699 set_except_vector(15, handle_fpe); 1700 1701 set_except_vector(22, handle_mdmx); 1702 1703 if (cpu_has_mcheck) 1704 set_except_vector(24, handle_mcheck); 1705 1706 if (cpu_has_mipsmt) 1707 set_except_vector(25, handle_mt); 1708 1709 set_except_vector(26, handle_dsp); 1710 1711 if (cpu_has_vce) 1712 /* Special exception: R4[04]00 uses also the divec space. */ 1713 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1714 else if (cpu_has_4kex) 1715 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); 1716 else 1717 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1718 1719 local_flush_icache_range(ebase, ebase + 0x400); 1720 flush_tlb_handlers(); 1721 1722 sort_extable(__start___dbe_table, __stop___dbe_table); 1723 1724 register_cu2_notifier(&default_cu2_notifier); 1725 } 1726