1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/extable.h> 25 #include <linux/mm.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/debug.h> 28 #include <linux/smp.h> 29 #include <linux/spinlock.h> 30 #include <linux/kallsyms.h> 31 #include <linux/bootmem.h> 32 #include <linux/interrupt.h> 33 #include <linux/ptrace.h> 34 #include <linux/kgdb.h> 35 #include <linux/kdebug.h> 36 #include <linux/kprobes.h> 37 #include <linux/notifier.h> 38 #include <linux/kdb.h> 39 #include <linux/irq.h> 40 #include <linux/perf_event.h> 41 42 #include <asm/addrspace.h> 43 #include <asm/bootinfo.h> 44 #include <asm/branch.h> 45 #include <asm/break.h> 46 #include <asm/cop2.h> 47 #include <asm/cpu.h> 48 #include <asm/cpu-type.h> 49 #include <asm/dsp.h> 50 #include <asm/fpu.h> 51 #include <asm/fpu_emulator.h> 52 #include <asm/idle.h> 53 #include <asm/mips-cps.h> 54 #include <asm/mips-r2-to-r6-emul.h> 55 #include <asm/mipsregs.h> 56 #include <asm/mipsmtregs.h> 57 #include <asm/module.h> 58 #include <asm/msa.h> 59 #include <asm/pgtable.h> 60 #include <asm/ptrace.h> 61 #include <asm/sections.h> 62 #include <asm/siginfo.h> 63 #include <asm/tlbdebug.h> 64 #include <asm/traps.h> 65 #include <linux/uaccess.h> 66 #include <asm/watch.h> 67 #include <asm/mmu_context.h> 68 #include <asm/types.h> 69 #include <asm/stacktrace.h> 70 #include <asm/uasm.h> 71 72 extern void check_wait(void); 73 extern asmlinkage void rollback_handle_int(void); 74 extern asmlinkage void handle_int(void); 75 extern u32 handle_tlbl[]; 76 extern u32 handle_tlbs[]; 77 extern u32 handle_tlbm[]; 78 extern asmlinkage void handle_adel(void); 79 extern asmlinkage void handle_ades(void); 80 extern asmlinkage void handle_ibe(void); 81 extern asmlinkage void handle_dbe(void); 82 extern asmlinkage void handle_sys(void); 83 extern asmlinkage void handle_bp(void); 84 extern asmlinkage void handle_ri(void); 85 extern asmlinkage void handle_ri_rdhwr_tlbp(void); 86 extern asmlinkage void handle_ri_rdhwr(void); 87 extern asmlinkage void handle_cpu(void); 88 extern asmlinkage void handle_ov(void); 89 extern asmlinkage void handle_tr(void); 90 extern asmlinkage void handle_msa_fpe(void); 91 extern asmlinkage void handle_fpe(void); 92 extern asmlinkage void handle_ftlb(void); 93 extern asmlinkage void handle_msa(void); 94 extern asmlinkage void handle_mdmx(void); 95 extern asmlinkage void handle_watch(void); 96 extern asmlinkage void handle_mt(void); 97 extern asmlinkage void handle_dsp(void); 98 extern asmlinkage void handle_mcheck(void); 99 extern asmlinkage void handle_reserved(void); 100 extern void tlb_do_page_fault_0(void); 101 102 void (*board_be_init)(void); 103 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 104 void (*board_nmi_handler_setup)(void); 105 void (*board_ejtag_handler_setup)(void); 106 void (*board_bind_eic_interrupt)(int irq, int regset); 107 void (*board_ebase_setup)(void); 108 void(*board_cache_error_setup)(void); 109 110 static void show_raw_backtrace(unsigned long reg29) 111 { 112 unsigned long *sp = (unsigned long *)(reg29 & ~3); 113 unsigned long addr; 114 115 printk("Call Trace:"); 116 #ifdef CONFIG_KALLSYMS 117 printk("\n"); 118 #endif 119 while (!kstack_end(sp)) { 120 unsigned long __user *p = 121 (unsigned long __user *)(unsigned long)sp++; 122 if (__get_user(addr, p)) { 123 printk(" (Bad stack address)"); 124 break; 125 } 126 if (__kernel_text_address(addr)) 127 print_ip_sym(addr); 128 } 129 printk("\n"); 130 } 131 132 #ifdef CONFIG_KALLSYMS 133 int raw_show_trace; 134 static int __init set_raw_show_trace(char *str) 135 { 136 raw_show_trace = 1; 137 return 1; 138 } 139 __setup("raw_show_trace", set_raw_show_trace); 140 #endif 141 142 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 143 { 144 unsigned long sp = regs->regs[29]; 145 unsigned long ra = regs->regs[31]; 146 unsigned long pc = regs->cp0_epc; 147 148 if (!task) 149 task = current; 150 151 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 152 show_raw_backtrace(sp); 153 return; 154 } 155 printk("Call Trace:\n"); 156 do { 157 print_ip_sym(pc); 158 pc = unwind_stack(task, &sp, pc, &ra); 159 } while (pc); 160 pr_cont("\n"); 161 } 162 163 /* 164 * This routine abuses get_user()/put_user() to reference pointers 165 * with at least a bit of error checking ... 166 */ 167 static void show_stacktrace(struct task_struct *task, 168 const struct pt_regs *regs) 169 { 170 const int field = 2 * sizeof(unsigned long); 171 long stackdata; 172 int i; 173 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 174 175 printk("Stack :"); 176 i = 0; 177 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 178 if (i && ((i % (64 / field)) == 0)) { 179 pr_cont("\n"); 180 printk(" "); 181 } 182 if (i > 39) { 183 pr_cont(" ..."); 184 break; 185 } 186 187 if (__get_user(stackdata, sp++)) { 188 pr_cont(" (Bad stack address)"); 189 break; 190 } 191 192 pr_cont(" %0*lx", field, stackdata); 193 i++; 194 } 195 pr_cont("\n"); 196 show_backtrace(task, regs); 197 } 198 199 void show_stack(struct task_struct *task, unsigned long *sp) 200 { 201 struct pt_regs regs; 202 mm_segment_t old_fs = get_fs(); 203 204 regs.cp0_status = KSU_KERNEL; 205 if (sp) { 206 regs.regs[29] = (unsigned long)sp; 207 regs.regs[31] = 0; 208 regs.cp0_epc = 0; 209 } else { 210 if (task && task != current) { 211 regs.regs[29] = task->thread.reg29; 212 regs.regs[31] = 0; 213 regs.cp0_epc = task->thread.reg31; 214 #ifdef CONFIG_KGDB_KDB 215 } else if (atomic_read(&kgdb_active) != -1 && 216 kdb_current_regs) { 217 memcpy(®s, kdb_current_regs, sizeof(regs)); 218 #endif /* CONFIG_KGDB_KDB */ 219 } else { 220 prepare_frametrace(®s); 221 } 222 } 223 /* 224 * show_stack() deals exclusively with kernel mode, so be sure to access 225 * the stack in the kernel (not user) address space. 226 */ 227 set_fs(KERNEL_DS); 228 show_stacktrace(task, ®s); 229 set_fs(old_fs); 230 } 231 232 static void show_code(unsigned int __user *pc) 233 { 234 long i; 235 unsigned short __user *pc16 = NULL; 236 237 printk("Code:"); 238 239 if ((unsigned long)pc & 1) 240 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 241 for(i = -3 ; i < 6 ; i++) { 242 unsigned int insn; 243 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 244 pr_cont(" (Bad address in epc)\n"); 245 break; 246 } 247 pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 248 } 249 pr_cont("\n"); 250 } 251 252 static void __show_regs(const struct pt_regs *regs) 253 { 254 const int field = 2 * sizeof(unsigned long); 255 unsigned int cause = regs->cp0_cause; 256 unsigned int exccode; 257 int i; 258 259 show_regs_print_info(KERN_DEFAULT); 260 261 /* 262 * Saved main processor registers 263 */ 264 for (i = 0; i < 32; ) { 265 if ((i % 4) == 0) 266 printk("$%2d :", i); 267 if (i == 0) 268 pr_cont(" %0*lx", field, 0UL); 269 else if (i == 26 || i == 27) 270 pr_cont(" %*s", field, ""); 271 else 272 pr_cont(" %0*lx", field, regs->regs[i]); 273 274 i++; 275 if ((i % 4) == 0) 276 pr_cont("\n"); 277 } 278 279 #ifdef CONFIG_CPU_HAS_SMARTMIPS 280 printk("Acx : %0*lx\n", field, regs->acx); 281 #endif 282 printk("Hi : %0*lx\n", field, regs->hi); 283 printk("Lo : %0*lx\n", field, regs->lo); 284 285 /* 286 * Saved cp0 registers 287 */ 288 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 289 (void *) regs->cp0_epc); 290 printk("ra : %0*lx %pS\n", field, regs->regs[31], 291 (void *) regs->regs[31]); 292 293 printk("Status: %08x ", (uint32_t) regs->cp0_status); 294 295 if (cpu_has_3kex) { 296 if (regs->cp0_status & ST0_KUO) 297 pr_cont("KUo "); 298 if (regs->cp0_status & ST0_IEO) 299 pr_cont("IEo "); 300 if (regs->cp0_status & ST0_KUP) 301 pr_cont("KUp "); 302 if (regs->cp0_status & ST0_IEP) 303 pr_cont("IEp "); 304 if (regs->cp0_status & ST0_KUC) 305 pr_cont("KUc "); 306 if (regs->cp0_status & ST0_IEC) 307 pr_cont("IEc "); 308 } else if (cpu_has_4kex) { 309 if (regs->cp0_status & ST0_KX) 310 pr_cont("KX "); 311 if (regs->cp0_status & ST0_SX) 312 pr_cont("SX "); 313 if (regs->cp0_status & ST0_UX) 314 pr_cont("UX "); 315 switch (regs->cp0_status & ST0_KSU) { 316 case KSU_USER: 317 pr_cont("USER "); 318 break; 319 case KSU_SUPERVISOR: 320 pr_cont("SUPERVISOR "); 321 break; 322 case KSU_KERNEL: 323 pr_cont("KERNEL "); 324 break; 325 default: 326 pr_cont("BAD_MODE "); 327 break; 328 } 329 if (regs->cp0_status & ST0_ERL) 330 pr_cont("ERL "); 331 if (regs->cp0_status & ST0_EXL) 332 pr_cont("EXL "); 333 if (regs->cp0_status & ST0_IE) 334 pr_cont("IE "); 335 } 336 pr_cont("\n"); 337 338 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 339 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode); 340 341 if (1 <= exccode && exccode <= 5) 342 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 343 344 printk("PrId : %08x (%s)\n", read_c0_prid(), 345 cpu_name_string()); 346 } 347 348 /* 349 * FIXME: really the generic show_regs should take a const pointer argument. 350 */ 351 void show_regs(struct pt_regs *regs) 352 { 353 __show_regs((struct pt_regs *)regs); 354 } 355 356 void show_registers(struct pt_regs *regs) 357 { 358 const int field = 2 * sizeof(unsigned long); 359 mm_segment_t old_fs = get_fs(); 360 361 __show_regs(regs); 362 print_modules(); 363 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 364 current->comm, current->pid, current_thread_info(), current, 365 field, current_thread_info()->tp_value); 366 if (cpu_has_userlocal) { 367 unsigned long tls; 368 369 tls = read_c0_userlocal(); 370 if (tls != current_thread_info()->tp_value) 371 printk("*HwTLS: %0*lx\n", field, tls); 372 } 373 374 if (!user_mode(regs)) 375 /* Necessary for getting the correct stack content */ 376 set_fs(KERNEL_DS); 377 show_stacktrace(current, regs); 378 show_code((unsigned int __user *) regs->cp0_epc); 379 printk("\n"); 380 set_fs(old_fs); 381 } 382 383 static DEFINE_RAW_SPINLOCK(die_lock); 384 385 void __noreturn die(const char *str, struct pt_regs *regs) 386 { 387 static int die_counter; 388 int sig = SIGSEGV; 389 390 oops_enter(); 391 392 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr, 393 SIGSEGV) == NOTIFY_STOP) 394 sig = 0; 395 396 console_verbose(); 397 raw_spin_lock_irq(&die_lock); 398 bust_spinlocks(1); 399 400 printk("%s[#%d]:\n", str, ++die_counter); 401 show_registers(regs); 402 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 403 raw_spin_unlock_irq(&die_lock); 404 405 oops_exit(); 406 407 if (in_interrupt()) 408 panic("Fatal exception in interrupt"); 409 410 if (panic_on_oops) 411 panic("Fatal exception"); 412 413 if (regs && kexec_should_crash(current)) 414 crash_kexec(regs); 415 416 do_exit(sig); 417 } 418 419 extern struct exception_table_entry __start___dbe_table[]; 420 extern struct exception_table_entry __stop___dbe_table[]; 421 422 __asm__( 423 " .section __dbe_table, \"a\"\n" 424 " .previous \n"); 425 426 /* Given an address, look for it in the exception tables. */ 427 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 428 { 429 const struct exception_table_entry *e; 430 431 e = search_extable(__start___dbe_table, 432 __stop___dbe_table - __start___dbe_table, addr); 433 if (!e) 434 e = search_module_dbetables(addr); 435 return e; 436 } 437 438 asmlinkage void do_be(struct pt_regs *regs) 439 { 440 const int field = 2 * sizeof(unsigned long); 441 const struct exception_table_entry *fixup = NULL; 442 int data = regs->cp0_cause & 4; 443 int action = MIPS_BE_FATAL; 444 enum ctx_state prev_state; 445 446 prev_state = exception_enter(); 447 /* XXX For now. Fixme, this searches the wrong table ... */ 448 if (data && !user_mode(regs)) 449 fixup = search_dbe_tables(exception_epc(regs)); 450 451 if (fixup) 452 action = MIPS_BE_FIXUP; 453 454 if (board_be_handler) 455 action = board_be_handler(regs, fixup != NULL); 456 else 457 mips_cm_error_report(); 458 459 switch (action) { 460 case MIPS_BE_DISCARD: 461 goto out; 462 case MIPS_BE_FIXUP: 463 if (fixup) { 464 regs->cp0_epc = fixup->nextinsn; 465 goto out; 466 } 467 break; 468 default: 469 break; 470 } 471 472 /* 473 * Assume it would be too dangerous to continue ... 474 */ 475 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 476 data ? "Data" : "Instruction", 477 field, regs->cp0_epc, field, regs->regs[31]); 478 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr, 479 SIGBUS) == NOTIFY_STOP) 480 goto out; 481 482 die_if_kernel("Oops", regs); 483 force_sig(SIGBUS, current); 484 485 out: 486 exception_exit(prev_state); 487 } 488 489 /* 490 * ll/sc, rdhwr, sync emulation 491 */ 492 493 #define OPCODE 0xfc000000 494 #define BASE 0x03e00000 495 #define RT 0x001f0000 496 #define OFFSET 0x0000ffff 497 #define LL 0xc0000000 498 #define SC 0xe0000000 499 #define SPEC0 0x00000000 500 #define SPEC3 0x7c000000 501 #define RD 0x0000f800 502 #define FUNC 0x0000003f 503 #define SYNC 0x0000000f 504 #define RDHWR 0x0000003b 505 506 /* microMIPS definitions */ 507 #define MM_POOL32A_FUNC 0xfc00ffff 508 #define MM_RDHWR 0x00006b3c 509 #define MM_RS 0x001f0000 510 #define MM_RT 0x03e00000 511 512 /* 513 * The ll_bit is cleared by r*_switch.S 514 */ 515 516 unsigned int ll_bit; 517 struct task_struct *ll_task; 518 519 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 520 { 521 unsigned long value, __user *vaddr; 522 long offset; 523 524 /* 525 * analyse the ll instruction that just caused a ri exception 526 * and put the referenced address to addr. 527 */ 528 529 /* sign extend offset */ 530 offset = opcode & OFFSET; 531 offset <<= 16; 532 offset >>= 16; 533 534 vaddr = (unsigned long __user *) 535 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 536 537 if ((unsigned long)vaddr & 3) 538 return SIGBUS; 539 if (get_user(value, vaddr)) 540 return SIGSEGV; 541 542 preempt_disable(); 543 544 if (ll_task == NULL || ll_task == current) { 545 ll_bit = 1; 546 } else { 547 ll_bit = 0; 548 } 549 ll_task = current; 550 551 preempt_enable(); 552 553 regs->regs[(opcode & RT) >> 16] = value; 554 555 return 0; 556 } 557 558 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 559 { 560 unsigned long __user *vaddr; 561 unsigned long reg; 562 long offset; 563 564 /* 565 * analyse the sc instruction that just caused a ri exception 566 * and put the referenced address to addr. 567 */ 568 569 /* sign extend offset */ 570 offset = opcode & OFFSET; 571 offset <<= 16; 572 offset >>= 16; 573 574 vaddr = (unsigned long __user *) 575 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 576 reg = (opcode & RT) >> 16; 577 578 if ((unsigned long)vaddr & 3) 579 return SIGBUS; 580 581 preempt_disable(); 582 583 if (ll_bit == 0 || ll_task != current) { 584 regs->regs[reg] = 0; 585 preempt_enable(); 586 return 0; 587 } 588 589 preempt_enable(); 590 591 if (put_user(regs->regs[reg], vaddr)) 592 return SIGSEGV; 593 594 regs->regs[reg] = 1; 595 596 return 0; 597 } 598 599 /* 600 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 601 * opcodes are supposed to result in coprocessor unusable exceptions if 602 * executed on ll/sc-less processors. That's the theory. In practice a 603 * few processors such as NEC's VR4100 throw reserved instruction exceptions 604 * instead, so we're doing the emulation thing in both exception handlers. 605 */ 606 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 607 { 608 if ((opcode & OPCODE) == LL) { 609 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 610 1, regs, 0); 611 return simulate_ll(regs, opcode); 612 } 613 if ((opcode & OPCODE) == SC) { 614 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 615 1, regs, 0); 616 return simulate_sc(regs, opcode); 617 } 618 619 return -1; /* Must be something else ... */ 620 } 621 622 /* 623 * Simulate trapping 'rdhwr' instructions to provide user accessible 624 * registers not implemented in hardware. 625 */ 626 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 627 { 628 struct thread_info *ti = task_thread_info(current); 629 630 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 631 1, regs, 0); 632 switch (rd) { 633 case MIPS_HWR_CPUNUM: /* CPU number */ 634 regs->regs[rt] = smp_processor_id(); 635 return 0; 636 case MIPS_HWR_SYNCISTEP: /* SYNCI length */ 637 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 638 current_cpu_data.icache.linesz); 639 return 0; 640 case MIPS_HWR_CC: /* Read count register */ 641 regs->regs[rt] = read_c0_count(); 642 return 0; 643 case MIPS_HWR_CCRES: /* Count register resolution */ 644 switch (current_cpu_type()) { 645 case CPU_20KC: 646 case CPU_25KF: 647 regs->regs[rt] = 1; 648 break; 649 default: 650 regs->regs[rt] = 2; 651 } 652 return 0; 653 case MIPS_HWR_ULR: /* Read UserLocal register */ 654 regs->regs[rt] = ti->tp_value; 655 return 0; 656 default: 657 return -1; 658 } 659 } 660 661 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 662 { 663 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 664 int rd = (opcode & RD) >> 11; 665 int rt = (opcode & RT) >> 16; 666 667 simulate_rdhwr(regs, rd, rt); 668 return 0; 669 } 670 671 /* Not ours. */ 672 return -1; 673 } 674 675 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) 676 { 677 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 678 int rd = (opcode & MM_RS) >> 16; 679 int rt = (opcode & MM_RT) >> 21; 680 simulate_rdhwr(regs, rd, rt); 681 return 0; 682 } 683 684 /* Not ours. */ 685 return -1; 686 } 687 688 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 689 { 690 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 691 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 692 1, regs, 0); 693 return 0; 694 } 695 696 return -1; /* Must be something else ... */ 697 } 698 699 asmlinkage void do_ov(struct pt_regs *regs) 700 { 701 enum ctx_state prev_state; 702 703 prev_state = exception_enter(); 704 die_if_kernel("Integer overflow", regs); 705 706 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current); 707 exception_exit(prev_state); 708 } 709 710 /* 711 * Send SIGFPE according to FCSR Cause bits, which must have already 712 * been masked against Enable bits. This is impotant as Inexact can 713 * happen together with Overflow or Underflow, and `ptrace' can set 714 * any bits. 715 */ 716 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr, 717 struct task_struct *tsk) 718 { 719 int si_code = FPE_FLTUNK; 720 721 if (fcr31 & FPU_CSR_INV_X) 722 si_code = FPE_FLTINV; 723 else if (fcr31 & FPU_CSR_DIV_X) 724 si_code = FPE_FLTDIV; 725 else if (fcr31 & FPU_CSR_OVF_X) 726 si_code = FPE_FLTOVF; 727 else if (fcr31 & FPU_CSR_UDF_X) 728 si_code = FPE_FLTUND; 729 else if (fcr31 & FPU_CSR_INE_X) 730 si_code = FPE_FLTRES; 731 732 force_sig_fault(SIGFPE, si_code, fault_addr, tsk); 733 } 734 735 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 736 { 737 int si_code; 738 struct vm_area_struct *vma; 739 740 switch (sig) { 741 case 0: 742 return 0; 743 744 case SIGFPE: 745 force_fcr31_sig(fcr31, fault_addr, current); 746 return 1; 747 748 case SIGBUS: 749 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current); 750 return 1; 751 752 case SIGSEGV: 753 down_read(¤t->mm->mmap_sem); 754 vma = find_vma(current->mm, (unsigned long)fault_addr); 755 if (vma && (vma->vm_start <= (unsigned long)fault_addr)) 756 si_code = SEGV_ACCERR; 757 else 758 si_code = SEGV_MAPERR; 759 up_read(¤t->mm->mmap_sem); 760 force_sig_fault(SIGSEGV, si_code, fault_addr, current); 761 return 1; 762 763 default: 764 force_sig(sig, current); 765 return 1; 766 } 767 } 768 769 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 770 unsigned long old_epc, unsigned long old_ra) 771 { 772 union mips_instruction inst = { .word = opcode }; 773 void __user *fault_addr; 774 unsigned long fcr31; 775 int sig; 776 777 /* If it's obviously not an FP instruction, skip it */ 778 switch (inst.i_format.opcode) { 779 case cop1_op: 780 case cop1x_op: 781 case lwc1_op: 782 case ldc1_op: 783 case swc1_op: 784 case sdc1_op: 785 break; 786 787 default: 788 return -1; 789 } 790 791 /* 792 * do_ri skipped over the instruction via compute_return_epc, undo 793 * that for the FPU emulator. 794 */ 795 regs->cp0_epc = old_epc; 796 regs->regs[31] = old_ra; 797 798 /* Save the FP context to struct thread_struct */ 799 lose_fpu(1); 800 801 /* Run the emulator */ 802 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 803 &fault_addr); 804 805 /* 806 * We can't allow the emulated instruction to leave any 807 * enabled Cause bits set in $fcr31. 808 */ 809 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 810 current->thread.fpu.fcr31 &= ~fcr31; 811 812 /* Restore the hardware register state */ 813 own_fpu(1); 814 815 /* Send a signal if required. */ 816 process_fpemu_return(sig, fault_addr, fcr31); 817 818 return 0; 819 } 820 821 /* 822 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 823 */ 824 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 825 { 826 enum ctx_state prev_state; 827 void __user *fault_addr; 828 int sig; 829 830 prev_state = exception_enter(); 831 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr, 832 SIGFPE) == NOTIFY_STOP) 833 goto out; 834 835 /* Clear FCSR.Cause before enabling interrupts */ 836 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31)); 837 local_irq_enable(); 838 839 die_if_kernel("FP exception in kernel code", regs); 840 841 if (fcr31 & FPU_CSR_UNI_X) { 842 /* 843 * Unimplemented operation exception. If we've got the full 844 * software emulator on-board, let's use it... 845 * 846 * Force FPU to dump state into task/thread context. We're 847 * moving a lot of data here for what is probably a single 848 * instruction, but the alternative is to pre-decode the FP 849 * register operands before invoking the emulator, which seems 850 * a bit extreme for what should be an infrequent event. 851 */ 852 /* Ensure 'resume' not overwrite saved fp context again. */ 853 lose_fpu(1); 854 855 /* Run the emulator */ 856 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 857 &fault_addr); 858 859 /* 860 * We can't allow the emulated instruction to leave any 861 * enabled Cause bits set in $fcr31. 862 */ 863 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 864 current->thread.fpu.fcr31 &= ~fcr31; 865 866 /* Restore the hardware register state */ 867 own_fpu(1); /* Using the FPU again. */ 868 } else { 869 sig = SIGFPE; 870 fault_addr = (void __user *) regs->cp0_epc; 871 } 872 873 /* Send a signal if required. */ 874 process_fpemu_return(sig, fault_addr, fcr31); 875 876 out: 877 exception_exit(prev_state); 878 } 879 880 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code, 881 const char *str) 882 { 883 char b[40]; 884 885 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 886 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr, 887 SIGTRAP) == NOTIFY_STOP) 888 return; 889 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 890 891 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr, 892 SIGTRAP) == NOTIFY_STOP) 893 return; 894 895 /* 896 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 897 * insns, even for trap and break codes that indicate arithmetic 898 * failures. Weird ... 899 * But should we continue the brokenness??? --macro 900 */ 901 switch (code) { 902 case BRK_OVERFLOW: 903 case BRK_DIVZERO: 904 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 905 die_if_kernel(b, regs); 906 force_sig_fault(SIGFPE, 907 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF, 908 (void __user *) regs->cp0_epc, current); 909 break; 910 case BRK_BUG: 911 die_if_kernel("Kernel bug detected", regs); 912 force_sig(SIGTRAP, current); 913 break; 914 case BRK_MEMU: 915 /* 916 * This breakpoint code is used by the FPU emulator to retake 917 * control of the CPU after executing the instruction from the 918 * delay slot of an emulated branch. 919 * 920 * Terminate if exception was recognized as a delay slot return 921 * otherwise handle as normal. 922 */ 923 if (do_dsemulret(regs)) 924 return; 925 926 die_if_kernel("Math emu break/trap", regs); 927 force_sig(SIGTRAP, current); 928 break; 929 default: 930 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 931 die_if_kernel(b, regs); 932 if (si_code) { 933 force_sig_fault(SIGTRAP, si_code, NULL, current); 934 } else { 935 force_sig(SIGTRAP, current); 936 } 937 } 938 } 939 940 asmlinkage void do_bp(struct pt_regs *regs) 941 { 942 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 943 unsigned int opcode, bcode; 944 enum ctx_state prev_state; 945 mm_segment_t seg; 946 947 seg = get_fs(); 948 if (!user_mode(regs)) 949 set_fs(KERNEL_DS); 950 951 prev_state = exception_enter(); 952 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 953 if (get_isa16_mode(regs->cp0_epc)) { 954 u16 instr[2]; 955 956 if (__get_user(instr[0], (u16 __user *)epc)) 957 goto out_sigsegv; 958 959 if (!cpu_has_mmips) { 960 /* MIPS16e mode */ 961 bcode = (instr[0] >> 5) & 0x3f; 962 } else if (mm_insn_16bit(instr[0])) { 963 /* 16-bit microMIPS BREAK */ 964 bcode = instr[0] & 0xf; 965 } else { 966 /* 32-bit microMIPS BREAK */ 967 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 968 goto out_sigsegv; 969 opcode = (instr[0] << 16) | instr[1]; 970 bcode = (opcode >> 6) & ((1 << 20) - 1); 971 } 972 } else { 973 if (__get_user(opcode, (unsigned int __user *)epc)) 974 goto out_sigsegv; 975 bcode = (opcode >> 6) & ((1 << 20) - 1); 976 } 977 978 /* 979 * There is the ancient bug in the MIPS assemblers that the break 980 * code starts left to bit 16 instead to bit 6 in the opcode. 981 * Gas is bug-compatible, but not always, grrr... 982 * We handle both cases with a simple heuristics. --macro 983 */ 984 if (bcode >= (1 << 10)) 985 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 986 987 /* 988 * notify the kprobe handlers, if instruction is likely to 989 * pertain to them. 990 */ 991 switch (bcode) { 992 case BRK_UPROBE: 993 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode, 994 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 995 goto out; 996 else 997 break; 998 case BRK_UPROBE_XOL: 999 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode, 1000 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1001 goto out; 1002 else 1003 break; 1004 case BRK_KPROBE_BP: 1005 if (notify_die(DIE_BREAK, "debug", regs, bcode, 1006 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1007 goto out; 1008 else 1009 break; 1010 case BRK_KPROBE_SSTEPBP: 1011 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 1012 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP) 1013 goto out; 1014 else 1015 break; 1016 default: 1017 break; 1018 } 1019 1020 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break"); 1021 1022 out: 1023 set_fs(seg); 1024 exception_exit(prev_state); 1025 return; 1026 1027 out_sigsegv: 1028 force_sig(SIGSEGV, current); 1029 goto out; 1030 } 1031 1032 asmlinkage void do_tr(struct pt_regs *regs) 1033 { 1034 u32 opcode, tcode = 0; 1035 enum ctx_state prev_state; 1036 u16 instr[2]; 1037 mm_segment_t seg; 1038 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1039 1040 seg = get_fs(); 1041 if (!user_mode(regs)) 1042 set_fs(get_ds()); 1043 1044 prev_state = exception_enter(); 1045 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1046 if (get_isa16_mode(regs->cp0_epc)) { 1047 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1048 __get_user(instr[1], (u16 __user *)(epc + 2))) 1049 goto out_sigsegv; 1050 opcode = (instr[0] << 16) | instr[1]; 1051 /* Immediate versions don't provide a code. */ 1052 if (!(opcode & OPCODE)) 1053 tcode = (opcode >> 12) & ((1 << 4) - 1); 1054 } else { 1055 if (__get_user(opcode, (u32 __user *)epc)) 1056 goto out_sigsegv; 1057 /* Immediate versions don't provide a code. */ 1058 if (!(opcode & OPCODE)) 1059 tcode = (opcode >> 6) & ((1 << 10) - 1); 1060 } 1061 1062 do_trap_or_bp(regs, tcode, 0, "Trap"); 1063 1064 out: 1065 set_fs(seg); 1066 exception_exit(prev_state); 1067 return; 1068 1069 out_sigsegv: 1070 force_sig(SIGSEGV, current); 1071 goto out; 1072 } 1073 1074 asmlinkage void do_ri(struct pt_regs *regs) 1075 { 1076 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1077 unsigned long old_epc = regs->cp0_epc; 1078 unsigned long old31 = regs->regs[31]; 1079 enum ctx_state prev_state; 1080 unsigned int opcode = 0; 1081 int status = -1; 1082 1083 /* 1084 * Avoid any kernel code. Just emulate the R2 instruction 1085 * as quickly as possible. 1086 */ 1087 if (mipsr2_emulation && cpu_has_mips_r6 && 1088 likely(user_mode(regs)) && 1089 likely(get_user(opcode, epc) >= 0)) { 1090 unsigned long fcr31 = 0; 1091 1092 status = mipsr2_decoder(regs, opcode, &fcr31); 1093 switch (status) { 1094 case 0: 1095 case SIGEMT: 1096 return; 1097 case SIGILL: 1098 goto no_r2_instr; 1099 default: 1100 process_fpemu_return(status, 1101 ¤t->thread.cp0_baduaddr, 1102 fcr31); 1103 return; 1104 } 1105 } 1106 1107 no_r2_instr: 1108 1109 prev_state = exception_enter(); 1110 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1111 1112 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr, 1113 SIGILL) == NOTIFY_STOP) 1114 goto out; 1115 1116 die_if_kernel("Reserved instruction in kernel code", regs); 1117 1118 if (unlikely(compute_return_epc(regs) < 0)) 1119 goto out; 1120 1121 if (!get_isa16_mode(regs->cp0_epc)) { 1122 if (unlikely(get_user(opcode, epc) < 0)) 1123 status = SIGSEGV; 1124 1125 if (!cpu_has_llsc && status < 0) 1126 status = simulate_llsc(regs, opcode); 1127 1128 if (status < 0) 1129 status = simulate_rdhwr_normal(regs, opcode); 1130 1131 if (status < 0) 1132 status = simulate_sync(regs, opcode); 1133 1134 if (status < 0) 1135 status = simulate_fp(regs, opcode, old_epc, old31); 1136 } else if (cpu_has_mmips) { 1137 unsigned short mmop[2] = { 0 }; 1138 1139 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0)) 1140 status = SIGSEGV; 1141 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0)) 1142 status = SIGSEGV; 1143 opcode = mmop[0]; 1144 opcode = (opcode << 16) | mmop[1]; 1145 1146 if (status < 0) 1147 status = simulate_rdhwr_mm(regs, opcode); 1148 } 1149 1150 if (status < 0) 1151 status = SIGILL; 1152 1153 if (unlikely(status > 0)) { 1154 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1155 regs->regs[31] = old31; 1156 force_sig(status, current); 1157 } 1158 1159 out: 1160 exception_exit(prev_state); 1161 } 1162 1163 /* 1164 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1165 * emulated more than some threshold number of instructions, force migration to 1166 * a "CPU" that has FP support. 1167 */ 1168 static void mt_ase_fp_affinity(void) 1169 { 1170 #ifdef CONFIG_MIPS_MT_FPAFF 1171 if (mt_fpemul_threshold > 0 && 1172 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1173 /* 1174 * If there's no FPU present, or if the application has already 1175 * restricted the allowed set to exclude any CPUs with FPUs, 1176 * we'll skip the procedure. 1177 */ 1178 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) { 1179 cpumask_t tmask; 1180 1181 current->thread.user_cpus_allowed 1182 = current->cpus_allowed; 1183 cpumask_and(&tmask, ¤t->cpus_allowed, 1184 &mt_fpu_cpumask); 1185 set_cpus_allowed_ptr(current, &tmask); 1186 set_thread_flag(TIF_FPUBOUND); 1187 } 1188 } 1189 #endif /* CONFIG_MIPS_MT_FPAFF */ 1190 } 1191 1192 /* 1193 * No lock; only written during early bootup by CPU 0. 1194 */ 1195 static RAW_NOTIFIER_HEAD(cu2_chain); 1196 1197 int __ref register_cu2_notifier(struct notifier_block *nb) 1198 { 1199 return raw_notifier_chain_register(&cu2_chain, nb); 1200 } 1201 1202 int cu2_notifier_call_chain(unsigned long val, void *v) 1203 { 1204 return raw_notifier_call_chain(&cu2_chain, val, v); 1205 } 1206 1207 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1208 void *data) 1209 { 1210 struct pt_regs *regs = data; 1211 1212 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1213 "instruction", regs); 1214 force_sig(SIGILL, current); 1215 1216 return NOTIFY_OK; 1217 } 1218 1219 static int enable_restore_fp_context(int msa) 1220 { 1221 int err, was_fpu_owner, prior_msa; 1222 1223 /* 1224 * If an FP mode switch is currently underway, wait for it to 1225 * complete before proceeding. 1226 */ 1227 wait_var_event(¤t->mm->context.fp_mode_switching, 1228 !atomic_read(¤t->mm->context.fp_mode_switching)); 1229 1230 if (!used_math()) { 1231 /* First time FP context user. */ 1232 preempt_disable(); 1233 err = init_fpu(); 1234 if (msa && !err) { 1235 enable_msa(); 1236 init_msa_upper(); 1237 set_thread_flag(TIF_USEDMSA); 1238 set_thread_flag(TIF_MSA_CTX_LIVE); 1239 } 1240 preempt_enable(); 1241 if (!err) 1242 set_used_math(); 1243 return err; 1244 } 1245 1246 /* 1247 * This task has formerly used the FP context. 1248 * 1249 * If this thread has no live MSA vector context then we can simply 1250 * restore the scalar FP context. If it has live MSA vector context 1251 * (that is, it has or may have used MSA since last performing a 1252 * function call) then we'll need to restore the vector context. This 1253 * applies even if we're currently only executing a scalar FP 1254 * instruction. This is because if we were to later execute an MSA 1255 * instruction then we'd either have to: 1256 * 1257 * - Restore the vector context & clobber any registers modified by 1258 * scalar FP instructions between now & then. 1259 * 1260 * or 1261 * 1262 * - Not restore the vector context & lose the most significant bits 1263 * of all vector registers. 1264 * 1265 * Neither of those options is acceptable. We cannot restore the least 1266 * significant bits of the registers now & only restore the most 1267 * significant bits later because the most significant bits of any 1268 * vector registers whose aliased FP register is modified now will have 1269 * been zeroed. We'd have no way to know that when restoring the vector 1270 * context & thus may load an outdated value for the most significant 1271 * bits of a vector register. 1272 */ 1273 if (!msa && !thread_msa_context_live()) 1274 return own_fpu(1); 1275 1276 /* 1277 * This task is using or has previously used MSA. Thus we require 1278 * that Status.FR == 1. 1279 */ 1280 preempt_disable(); 1281 was_fpu_owner = is_fpu_owner(); 1282 err = own_fpu_inatomic(0); 1283 if (err) 1284 goto out; 1285 1286 enable_msa(); 1287 write_msa_csr(current->thread.fpu.msacsr); 1288 set_thread_flag(TIF_USEDMSA); 1289 1290 /* 1291 * If this is the first time that the task is using MSA and it has 1292 * previously used scalar FP in this time slice then we already nave 1293 * FP context which we shouldn't clobber. We do however need to clear 1294 * the upper 64b of each vector register so that this task has no 1295 * opportunity to see data left behind by another. 1296 */ 1297 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1298 if (!prior_msa && was_fpu_owner) { 1299 init_msa_upper(); 1300 1301 goto out; 1302 } 1303 1304 if (!prior_msa) { 1305 /* 1306 * Restore the least significant 64b of each vector register 1307 * from the existing scalar FP context. 1308 */ 1309 _restore_fp(current); 1310 1311 /* 1312 * The task has not formerly used MSA, so clear the upper 64b 1313 * of each vector register such that it cannot see data left 1314 * behind by another task. 1315 */ 1316 init_msa_upper(); 1317 } else { 1318 /* We need to restore the vector context. */ 1319 restore_msa(current); 1320 1321 /* Restore the scalar FP control & status register */ 1322 if (!was_fpu_owner) 1323 write_32bit_cp1_register(CP1_STATUS, 1324 current->thread.fpu.fcr31); 1325 } 1326 1327 out: 1328 preempt_enable(); 1329 1330 return 0; 1331 } 1332 1333 asmlinkage void do_cpu(struct pt_regs *regs) 1334 { 1335 enum ctx_state prev_state; 1336 unsigned int __user *epc; 1337 unsigned long old_epc, old31; 1338 void __user *fault_addr; 1339 unsigned int opcode; 1340 unsigned long fcr31; 1341 unsigned int cpid; 1342 int status, err; 1343 int sig; 1344 1345 prev_state = exception_enter(); 1346 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1347 1348 if (cpid != 2) 1349 die_if_kernel("do_cpu invoked from kernel context!", regs); 1350 1351 switch (cpid) { 1352 case 0: 1353 epc = (unsigned int __user *)exception_epc(regs); 1354 old_epc = regs->cp0_epc; 1355 old31 = regs->regs[31]; 1356 opcode = 0; 1357 status = -1; 1358 1359 if (unlikely(compute_return_epc(regs) < 0)) 1360 break; 1361 1362 if (!get_isa16_mode(regs->cp0_epc)) { 1363 if (unlikely(get_user(opcode, epc) < 0)) 1364 status = SIGSEGV; 1365 1366 if (!cpu_has_llsc && status < 0) 1367 status = simulate_llsc(regs, opcode); 1368 } 1369 1370 if (status < 0) 1371 status = SIGILL; 1372 1373 if (unlikely(status > 0)) { 1374 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1375 regs->regs[31] = old31; 1376 force_sig(status, current); 1377 } 1378 1379 break; 1380 1381 case 3: 1382 /* 1383 * The COP3 opcode space and consequently the CP0.Status.CU3 1384 * bit and the CP0.Cause.CE=3 encoding have been removed as 1385 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1386 * up the space has been reused for COP1X instructions, that 1387 * are enabled by the CP0.Status.CU1 bit and consequently 1388 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1389 * exceptions. Some FPU-less processors that implement one 1390 * of these ISAs however use this code erroneously for COP1X 1391 * instructions. Therefore we redirect this trap to the FP 1392 * emulator too. 1393 */ 1394 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1395 force_sig(SIGILL, current); 1396 break; 1397 } 1398 /* Fall through. */ 1399 1400 case 1: 1401 err = enable_restore_fp_context(0); 1402 1403 if (raw_cpu_has_fpu && !err) 1404 break; 1405 1406 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1407 &fault_addr); 1408 1409 /* 1410 * We can't allow the emulated instruction to leave 1411 * any enabled Cause bits set in $fcr31. 1412 */ 1413 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31); 1414 current->thread.fpu.fcr31 &= ~fcr31; 1415 1416 /* Send a signal if required. */ 1417 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1418 mt_ase_fp_affinity(); 1419 1420 break; 1421 1422 case 2: 1423 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1424 break; 1425 } 1426 1427 exception_exit(prev_state); 1428 } 1429 1430 asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1431 { 1432 enum ctx_state prev_state; 1433 1434 prev_state = exception_enter(); 1435 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f; 1436 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1437 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP) 1438 goto out; 1439 1440 /* Clear MSACSR.Cause before enabling interrupts */ 1441 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1442 local_irq_enable(); 1443 1444 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1445 force_sig(SIGFPE, current); 1446 out: 1447 exception_exit(prev_state); 1448 } 1449 1450 asmlinkage void do_msa(struct pt_regs *regs) 1451 { 1452 enum ctx_state prev_state; 1453 int err; 1454 1455 prev_state = exception_enter(); 1456 1457 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1458 force_sig(SIGILL, current); 1459 goto out; 1460 } 1461 1462 die_if_kernel("do_msa invoked from kernel context!", regs); 1463 1464 err = enable_restore_fp_context(1); 1465 if (err) 1466 force_sig(SIGILL, current); 1467 out: 1468 exception_exit(prev_state); 1469 } 1470 1471 asmlinkage void do_mdmx(struct pt_regs *regs) 1472 { 1473 enum ctx_state prev_state; 1474 1475 prev_state = exception_enter(); 1476 force_sig(SIGILL, current); 1477 exception_exit(prev_state); 1478 } 1479 1480 /* 1481 * Called with interrupts disabled. 1482 */ 1483 asmlinkage void do_watch(struct pt_regs *regs) 1484 { 1485 enum ctx_state prev_state; 1486 1487 prev_state = exception_enter(); 1488 /* 1489 * Clear WP (bit 22) bit of cause register so we don't loop 1490 * forever. 1491 */ 1492 clear_c0_cause(CAUSEF_WP); 1493 1494 /* 1495 * If the current thread has the watch registers loaded, save 1496 * their values and send SIGTRAP. Otherwise another thread 1497 * left the registers set, clear them and continue. 1498 */ 1499 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1500 mips_read_watch_registers(); 1501 local_irq_enable(); 1502 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current); 1503 } else { 1504 mips_clear_watch_registers(); 1505 local_irq_enable(); 1506 } 1507 exception_exit(prev_state); 1508 } 1509 1510 asmlinkage void do_mcheck(struct pt_regs *regs) 1511 { 1512 int multi_match = regs->cp0_status & ST0_TS; 1513 enum ctx_state prev_state; 1514 mm_segment_t old_fs = get_fs(); 1515 1516 prev_state = exception_enter(); 1517 show_regs(regs); 1518 1519 if (multi_match) { 1520 dump_tlb_regs(); 1521 pr_info("\n"); 1522 dump_tlb_all(); 1523 } 1524 1525 if (!user_mode(regs)) 1526 set_fs(KERNEL_DS); 1527 1528 show_code((unsigned int __user *) regs->cp0_epc); 1529 1530 set_fs(old_fs); 1531 1532 /* 1533 * Some chips may have other causes of machine check (e.g. SB1 1534 * graduation timer) 1535 */ 1536 panic("Caught Machine Check exception - %scaused by multiple " 1537 "matching entries in the TLB.", 1538 (multi_match) ? "" : "not "); 1539 } 1540 1541 asmlinkage void do_mt(struct pt_regs *regs) 1542 { 1543 int subcode; 1544 1545 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1546 >> VPECONTROL_EXCPT_SHIFT; 1547 switch (subcode) { 1548 case 0: 1549 printk(KERN_DEBUG "Thread Underflow\n"); 1550 break; 1551 case 1: 1552 printk(KERN_DEBUG "Thread Overflow\n"); 1553 break; 1554 case 2: 1555 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1556 break; 1557 case 3: 1558 printk(KERN_DEBUG "Gating Storage Exception\n"); 1559 break; 1560 case 4: 1561 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1562 break; 1563 case 5: 1564 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1565 break; 1566 default: 1567 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1568 subcode); 1569 break; 1570 } 1571 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1572 1573 force_sig(SIGILL, current); 1574 } 1575 1576 1577 asmlinkage void do_dsp(struct pt_regs *regs) 1578 { 1579 if (cpu_has_dsp) 1580 panic("Unexpected DSP exception"); 1581 1582 force_sig(SIGILL, current); 1583 } 1584 1585 asmlinkage void do_reserved(struct pt_regs *regs) 1586 { 1587 /* 1588 * Game over - no way to handle this if it ever occurs. Most probably 1589 * caused by a new unknown cpu type or after another deadly 1590 * hard/software error. 1591 */ 1592 show_regs(regs); 1593 panic("Caught reserved exception %ld - should not happen.", 1594 (regs->cp0_cause & 0x7f) >> 2); 1595 } 1596 1597 static int __initdata l1parity = 1; 1598 static int __init nol1parity(char *s) 1599 { 1600 l1parity = 0; 1601 return 1; 1602 } 1603 __setup("nol1par", nol1parity); 1604 static int __initdata l2parity = 1; 1605 static int __init nol2parity(char *s) 1606 { 1607 l2parity = 0; 1608 return 1; 1609 } 1610 __setup("nol2par", nol2parity); 1611 1612 /* 1613 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1614 * it different ways. 1615 */ 1616 static inline void parity_protection_init(void) 1617 { 1618 #define ERRCTL_PE 0x80000000 1619 #define ERRCTL_L2P 0x00800000 1620 1621 if (mips_cm_revision() >= CM_REV_CM3) { 1622 ulong gcr_ectl, cp0_ectl; 1623 1624 /* 1625 * With CM3 systems we need to ensure that the L1 & L2 1626 * parity enables are set to the same value, since this 1627 * is presumed by the hardware engineers. 1628 * 1629 * If the user disabled either of L1 or L2 ECC checking, 1630 * disable both. 1631 */ 1632 l1parity &= l2parity; 1633 l2parity &= l1parity; 1634 1635 /* Probe L1 ECC support */ 1636 cp0_ectl = read_c0_ecc(); 1637 write_c0_ecc(cp0_ectl | ERRCTL_PE); 1638 back_to_back_c0_hazard(); 1639 cp0_ectl = read_c0_ecc(); 1640 1641 /* Probe L2 ECC support */ 1642 gcr_ectl = read_gcr_err_control(); 1643 1644 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) || 1645 !(cp0_ectl & ERRCTL_PE)) { 1646 /* 1647 * One of L1 or L2 ECC checking isn't supported, 1648 * so we cannot enable either. 1649 */ 1650 l1parity = l2parity = 0; 1651 } 1652 1653 /* Configure L1 ECC checking */ 1654 if (l1parity) 1655 cp0_ectl |= ERRCTL_PE; 1656 else 1657 cp0_ectl &= ~ERRCTL_PE; 1658 write_c0_ecc(cp0_ectl); 1659 back_to_back_c0_hazard(); 1660 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity); 1661 1662 /* Configure L2 ECC checking */ 1663 if (l2parity) 1664 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1665 else 1666 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN; 1667 write_gcr_err_control(gcr_ectl); 1668 gcr_ectl = read_gcr_err_control(); 1669 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN; 1670 WARN_ON(!!gcr_ectl != l2parity); 1671 1672 pr_info("Cache parity protection %sabled\n", 1673 l1parity ? "en" : "dis"); 1674 return; 1675 } 1676 1677 switch (current_cpu_type()) { 1678 case CPU_24K: 1679 case CPU_34K: 1680 case CPU_74K: 1681 case CPU_1004K: 1682 case CPU_1074K: 1683 case CPU_INTERAPTIV: 1684 case CPU_PROAPTIV: 1685 case CPU_P5600: 1686 case CPU_QEMU_GENERIC: 1687 case CPU_P6600: 1688 { 1689 unsigned long errctl; 1690 unsigned int l1parity_present, l2parity_present; 1691 1692 errctl = read_c0_ecc(); 1693 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1694 1695 /* probe L1 parity support */ 1696 write_c0_ecc(errctl | ERRCTL_PE); 1697 back_to_back_c0_hazard(); 1698 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1699 1700 /* probe L2 parity support */ 1701 write_c0_ecc(errctl|ERRCTL_L2P); 1702 back_to_back_c0_hazard(); 1703 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1704 1705 if (l1parity_present && l2parity_present) { 1706 if (l1parity) 1707 errctl |= ERRCTL_PE; 1708 if (l1parity ^ l2parity) 1709 errctl |= ERRCTL_L2P; 1710 } else if (l1parity_present) { 1711 if (l1parity) 1712 errctl |= ERRCTL_PE; 1713 } else if (l2parity_present) { 1714 if (l2parity) 1715 errctl |= ERRCTL_L2P; 1716 } else { 1717 /* No parity available */ 1718 } 1719 1720 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1721 1722 write_c0_ecc(errctl); 1723 back_to_back_c0_hazard(); 1724 errctl = read_c0_ecc(); 1725 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1726 1727 if (l1parity_present) 1728 printk(KERN_INFO "Cache parity protection %sabled\n", 1729 (errctl & ERRCTL_PE) ? "en" : "dis"); 1730 1731 if (l2parity_present) { 1732 if (l1parity_present && l1parity) 1733 errctl ^= ERRCTL_L2P; 1734 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1735 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1736 } 1737 } 1738 break; 1739 1740 case CPU_5KC: 1741 case CPU_5KE: 1742 case CPU_LOONGSON1: 1743 write_c0_ecc(0x80000000); 1744 back_to_back_c0_hazard(); 1745 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1746 printk(KERN_INFO "Cache parity protection %sabled\n", 1747 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1748 break; 1749 case CPU_20KC: 1750 case CPU_25KF: 1751 /* Clear the DE bit (bit 16) in the c0_status register. */ 1752 printk(KERN_INFO "Enable cache parity protection for " 1753 "MIPS 20KC/25KF CPUs.\n"); 1754 clear_c0_status(ST0_DE); 1755 break; 1756 default: 1757 break; 1758 } 1759 } 1760 1761 asmlinkage void cache_parity_error(void) 1762 { 1763 const int field = 2 * sizeof(unsigned long); 1764 unsigned int reg_val; 1765 1766 /* For the moment, report the problem and hang. */ 1767 printk("Cache error exception:\n"); 1768 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1769 reg_val = read_c0_cacheerr(); 1770 printk("c0_cacheerr == %08x\n", reg_val); 1771 1772 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1773 reg_val & (1<<30) ? "secondary" : "primary", 1774 reg_val & (1<<31) ? "data" : "insn"); 1775 if ((cpu_has_mips_r2_r6) && 1776 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1777 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1778 reg_val & (1<<29) ? "ED " : "", 1779 reg_val & (1<<28) ? "ET " : "", 1780 reg_val & (1<<27) ? "ES " : "", 1781 reg_val & (1<<26) ? "EE " : "", 1782 reg_val & (1<<25) ? "EB " : "", 1783 reg_val & (1<<24) ? "EI " : "", 1784 reg_val & (1<<23) ? "E1 " : "", 1785 reg_val & (1<<22) ? "E0 " : ""); 1786 } else { 1787 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1788 reg_val & (1<<29) ? "ED " : "", 1789 reg_val & (1<<28) ? "ET " : "", 1790 reg_val & (1<<26) ? "EE " : "", 1791 reg_val & (1<<25) ? "EB " : "", 1792 reg_val & (1<<24) ? "EI " : "", 1793 reg_val & (1<<23) ? "E1 " : "", 1794 reg_val & (1<<22) ? "E0 " : ""); 1795 } 1796 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1797 1798 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1799 if (reg_val & (1<<22)) 1800 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1801 1802 if (reg_val & (1<<23)) 1803 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1804 #endif 1805 1806 panic("Can't handle the cache error!"); 1807 } 1808 1809 asmlinkage void do_ftlb(void) 1810 { 1811 const int field = 2 * sizeof(unsigned long); 1812 unsigned int reg_val; 1813 1814 /* For the moment, report the problem and hang. */ 1815 if ((cpu_has_mips_r2_r6) && 1816 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) || 1817 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) { 1818 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1819 read_c0_ecc()); 1820 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1821 reg_val = read_c0_cacheerr(); 1822 pr_err("c0_cacheerr == %08x\n", reg_val); 1823 1824 if ((reg_val & 0xc0000000) == 0xc0000000) { 1825 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1826 } else { 1827 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1828 reg_val & (1<<30) ? "secondary" : "primary", 1829 reg_val & (1<<31) ? "data" : "insn"); 1830 } 1831 } else { 1832 pr_err("FTLB error exception\n"); 1833 } 1834 /* Just print the cacheerr bits for now */ 1835 cache_parity_error(); 1836 } 1837 1838 /* 1839 * SDBBP EJTAG debug exception handler. 1840 * We skip the instruction and return to the next instruction. 1841 */ 1842 void ejtag_exception_handler(struct pt_regs *regs) 1843 { 1844 const int field = 2 * sizeof(unsigned long); 1845 unsigned long depc, old_epc, old_ra; 1846 unsigned int debug; 1847 1848 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1849 depc = read_c0_depc(); 1850 debug = read_c0_debug(); 1851 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1852 if (debug & 0x80000000) { 1853 /* 1854 * In branch delay slot. 1855 * We cheat a little bit here and use EPC to calculate the 1856 * debug return address (DEPC). EPC is restored after the 1857 * calculation. 1858 */ 1859 old_epc = regs->cp0_epc; 1860 old_ra = regs->regs[31]; 1861 regs->cp0_epc = depc; 1862 compute_return_epc(regs); 1863 depc = regs->cp0_epc; 1864 regs->cp0_epc = old_epc; 1865 regs->regs[31] = old_ra; 1866 } else 1867 depc += 4; 1868 write_c0_depc(depc); 1869 1870 #if 0 1871 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1872 write_c0_debug(debug | 0x100); 1873 #endif 1874 } 1875 1876 /* 1877 * NMI exception handler. 1878 * No lock; only written during early bootup by CPU 0. 1879 */ 1880 static RAW_NOTIFIER_HEAD(nmi_chain); 1881 1882 int register_nmi_notifier(struct notifier_block *nb) 1883 { 1884 return raw_notifier_chain_register(&nmi_chain, nb); 1885 } 1886 1887 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1888 { 1889 char str[100]; 1890 1891 nmi_enter(); 1892 raw_notifier_call_chain(&nmi_chain, 0, regs); 1893 bust_spinlocks(1); 1894 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1895 smp_processor_id(), regs->cp0_epc); 1896 regs->cp0_epc = read_c0_errorepc(); 1897 die(str, regs); 1898 nmi_exit(); 1899 } 1900 1901 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1902 1903 unsigned long ebase; 1904 EXPORT_SYMBOL_GPL(ebase); 1905 unsigned long exception_handlers[32]; 1906 unsigned long vi_handlers[64]; 1907 1908 void __init *set_except_vector(int n, void *addr) 1909 { 1910 unsigned long handler = (unsigned long) addr; 1911 unsigned long old_handler; 1912 1913 #ifdef CONFIG_CPU_MICROMIPS 1914 /* 1915 * Only the TLB handlers are cache aligned with an even 1916 * address. All other handlers are on an odd address and 1917 * require no modification. Otherwise, MIPS32 mode will 1918 * be entered when handling any TLB exceptions. That 1919 * would be bad...since we must stay in microMIPS mode. 1920 */ 1921 if (!(handler & 0x1)) 1922 handler |= 1; 1923 #endif 1924 old_handler = xchg(&exception_handlers[n], handler); 1925 1926 if (n == 0 && cpu_has_divec) { 1927 #ifdef CONFIG_CPU_MICROMIPS 1928 unsigned long jump_mask = ~((1 << 27) - 1); 1929 #else 1930 unsigned long jump_mask = ~((1 << 28) - 1); 1931 #endif 1932 u32 *buf = (u32 *)(ebase + 0x200); 1933 unsigned int k0 = 26; 1934 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1935 uasm_i_j(&buf, handler & ~jump_mask); 1936 uasm_i_nop(&buf); 1937 } else { 1938 UASM_i_LA(&buf, k0, handler); 1939 uasm_i_jr(&buf, k0); 1940 uasm_i_nop(&buf); 1941 } 1942 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1943 } 1944 return (void *)old_handler; 1945 } 1946 1947 static void do_default_vi(void) 1948 { 1949 show_regs(get_irq_regs()); 1950 panic("Caught unexpected vectored interrupt."); 1951 } 1952 1953 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1954 { 1955 unsigned long handler; 1956 unsigned long old_handler = vi_handlers[n]; 1957 int srssets = current_cpu_data.srsets; 1958 u16 *h; 1959 unsigned char *b; 1960 1961 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1962 1963 if (addr == NULL) { 1964 handler = (unsigned long) do_default_vi; 1965 srs = 0; 1966 } else 1967 handler = (unsigned long) addr; 1968 vi_handlers[n] = handler; 1969 1970 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1971 1972 if (srs >= srssets) 1973 panic("Shadow register set %d not supported", srs); 1974 1975 if (cpu_has_veic) { 1976 if (board_bind_eic_interrupt) 1977 board_bind_eic_interrupt(n, srs); 1978 } else if (cpu_has_vint) { 1979 /* SRSMap is only defined if shadow sets are implemented */ 1980 if (srssets > 1) 1981 change_c0_srsmap(0xf << n*4, srs << n*4); 1982 } 1983 1984 if (srs == 0) { 1985 /* 1986 * If no shadow set is selected then use the default handler 1987 * that does normal register saving and standard interrupt exit 1988 */ 1989 extern char except_vec_vi, except_vec_vi_lui; 1990 extern char except_vec_vi_ori, except_vec_vi_end; 1991 extern char rollback_except_vec_vi; 1992 char *vec_start = using_rollback_handler() ? 1993 &rollback_except_vec_vi : &except_vec_vi; 1994 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1995 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1996 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1997 #else 1998 const int lui_offset = &except_vec_vi_lui - vec_start; 1999 const int ori_offset = &except_vec_vi_ori - vec_start; 2000 #endif 2001 const int handler_len = &except_vec_vi_end - vec_start; 2002 2003 if (handler_len > VECTORSPACING) { 2004 /* 2005 * Sigh... panicing won't help as the console 2006 * is probably not configured :( 2007 */ 2008 panic("VECTORSPACING too small"); 2009 } 2010 2011 set_handler(((unsigned long)b - ebase), vec_start, 2012 #ifdef CONFIG_CPU_MICROMIPS 2013 (handler_len - 1)); 2014 #else 2015 handler_len); 2016 #endif 2017 h = (u16 *)(b + lui_offset); 2018 *h = (handler >> 16) & 0xffff; 2019 h = (u16 *)(b + ori_offset); 2020 *h = (handler & 0xffff); 2021 local_flush_icache_range((unsigned long)b, 2022 (unsigned long)(b+handler_len)); 2023 } 2024 else { 2025 /* 2026 * In other cases jump directly to the interrupt handler. It 2027 * is the handler's responsibility to save registers if required 2028 * (eg hi/lo) and return from the exception using "eret". 2029 */ 2030 u32 insn; 2031 2032 h = (u16 *)b; 2033 /* j handler */ 2034 #ifdef CONFIG_CPU_MICROMIPS 2035 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 2036 #else 2037 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2038 #endif 2039 h[0] = (insn >> 16) & 0xffff; 2040 h[1] = insn & 0xffff; 2041 h[2] = 0; 2042 h[3] = 0; 2043 local_flush_icache_range((unsigned long)b, 2044 (unsigned long)(b+8)); 2045 } 2046 2047 return (void *)old_handler; 2048 } 2049 2050 void *set_vi_handler(int n, vi_handler_t addr) 2051 { 2052 return set_vi_srs_handler(n, addr, 0); 2053 } 2054 2055 extern void tlb_init(void); 2056 2057 /* 2058 * Timer interrupt 2059 */ 2060 int cp0_compare_irq; 2061 EXPORT_SYMBOL_GPL(cp0_compare_irq); 2062 int cp0_compare_irq_shift; 2063 2064 /* 2065 * Performance counter IRQ or -1 if shared with timer 2066 */ 2067 int cp0_perfcount_irq; 2068 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2069 2070 /* 2071 * Fast debug channel IRQ or -1 if not present 2072 */ 2073 int cp0_fdc_irq; 2074 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2075 2076 static int noulri; 2077 2078 static int __init ulri_disable(char *s) 2079 { 2080 pr_info("Disabling ulri\n"); 2081 noulri = 1; 2082 2083 return 1; 2084 } 2085 __setup("noulri", ulri_disable); 2086 2087 /* configure STATUS register */ 2088 static void configure_status(void) 2089 { 2090 /* 2091 * Disable coprocessors and select 32-bit or 64-bit addressing 2092 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2093 * flag that some firmware may have left set and the TS bit (for 2094 * IP27). Set XX for ISA IV code to work. 2095 */ 2096 unsigned int status_set = ST0_CU0; 2097 #ifdef CONFIG_64BIT 2098 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2099 #endif 2100 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2101 status_set |= ST0_XX; 2102 if (cpu_has_dsp) 2103 status_set |= ST0_MX; 2104 2105 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2106 status_set); 2107 } 2108 2109 unsigned int hwrena; 2110 EXPORT_SYMBOL_GPL(hwrena); 2111 2112 /* configure HWRENA register */ 2113 static void configure_hwrena(void) 2114 { 2115 hwrena = cpu_hwrena_impl_bits; 2116 2117 if (cpu_has_mips_r2_r6) 2118 hwrena |= MIPS_HWRENA_CPUNUM | 2119 MIPS_HWRENA_SYNCISTEP | 2120 MIPS_HWRENA_CC | 2121 MIPS_HWRENA_CCRES; 2122 2123 if (!noulri && cpu_has_userlocal) 2124 hwrena |= MIPS_HWRENA_ULR; 2125 2126 if (hwrena) 2127 write_c0_hwrena(hwrena); 2128 } 2129 2130 static void configure_exception_vector(void) 2131 { 2132 if (cpu_has_veic || cpu_has_vint) { 2133 unsigned long sr = set_c0_status(ST0_BEV); 2134 /* If available, use WG to set top bits of EBASE */ 2135 if (cpu_has_ebase_wg) { 2136 #ifdef CONFIG_64BIT 2137 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2138 #else 2139 write_c0_ebase(ebase | MIPS_EBASE_WG); 2140 #endif 2141 } 2142 write_c0_ebase(ebase); 2143 write_c0_status(sr); 2144 /* Setting vector spacing enables EI/VI mode */ 2145 change_c0_intctl(0x3e0, VECTORSPACING); 2146 } 2147 if (cpu_has_divec) { 2148 if (cpu_has_mipsmt) { 2149 unsigned int vpflags = dvpe(); 2150 set_c0_cause(CAUSEF_IV); 2151 evpe(vpflags); 2152 } else 2153 set_c0_cause(CAUSEF_IV); 2154 } 2155 } 2156 2157 void per_cpu_trap_init(bool is_boot_cpu) 2158 { 2159 unsigned int cpu = smp_processor_id(); 2160 2161 configure_status(); 2162 configure_hwrena(); 2163 2164 configure_exception_vector(); 2165 2166 /* 2167 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2168 * 2169 * o read IntCtl.IPTI to determine the timer interrupt 2170 * o read IntCtl.IPPCI to determine the performance counter interrupt 2171 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2172 */ 2173 if (cpu_has_mips_r2_r6) { 2174 /* 2175 * We shouldn't trust a secondary core has a sane EBASE register 2176 * so use the one calculated by the boot CPU. 2177 */ 2178 if (!is_boot_cpu) { 2179 /* If available, use WG to set top bits of EBASE */ 2180 if (cpu_has_ebase_wg) { 2181 #ifdef CONFIG_64BIT 2182 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 2183 #else 2184 write_c0_ebase(ebase | MIPS_EBASE_WG); 2185 #endif 2186 } 2187 write_c0_ebase(ebase); 2188 } 2189 2190 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2191 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2192 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2193 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2194 if (!cp0_fdc_irq) 2195 cp0_fdc_irq = -1; 2196 2197 } else { 2198 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2199 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2200 cp0_perfcount_irq = -1; 2201 cp0_fdc_irq = -1; 2202 } 2203 2204 if (!cpu_data[cpu].asid_cache) 2205 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2206 2207 mmgrab(&init_mm); 2208 current->active_mm = &init_mm; 2209 BUG_ON(current->mm); 2210 enter_lazy_tlb(&init_mm, current); 2211 2212 /* Boot CPU's cache setup in setup_arch(). */ 2213 if (!is_boot_cpu) 2214 cpu_cache_init(); 2215 tlb_init(); 2216 TLBMISS_HANDLER_SETUP(); 2217 } 2218 2219 /* Install CPU exception handler */ 2220 void set_handler(unsigned long offset, void *addr, unsigned long size) 2221 { 2222 #ifdef CONFIG_CPU_MICROMIPS 2223 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2224 #else 2225 memcpy((void *)(ebase + offset), addr, size); 2226 #endif 2227 local_flush_icache_range(ebase + offset, ebase + offset + size); 2228 } 2229 2230 static const char panic_null_cerr[] = 2231 "Trying to set NULL cache error exception handler\n"; 2232 2233 /* 2234 * Install uncached CPU exception handler. 2235 * This is suitable only for the cache error exception which is the only 2236 * exception handler that is being run uncached. 2237 */ 2238 void set_uncached_handler(unsigned long offset, void *addr, 2239 unsigned long size) 2240 { 2241 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2242 2243 if (!addr) 2244 panic(panic_null_cerr); 2245 2246 memcpy((void *)(uncached_ebase + offset), addr, size); 2247 } 2248 2249 static int __initdata rdhwr_noopt; 2250 static int __init set_rdhwr_noopt(char *str) 2251 { 2252 rdhwr_noopt = 1; 2253 return 1; 2254 } 2255 2256 __setup("rdhwr_noopt", set_rdhwr_noopt); 2257 2258 void __init trap_init(void) 2259 { 2260 extern char except_vec3_generic; 2261 extern char except_vec4; 2262 extern char except_vec3_r4000; 2263 unsigned long i; 2264 2265 check_wait(); 2266 2267 if (cpu_has_veic || cpu_has_vint) { 2268 unsigned long size = 0x200 + VECTORSPACING*64; 2269 phys_addr_t ebase_pa; 2270 2271 ebase = (unsigned long) 2272 __alloc_bootmem(size, 1 << fls(size), 0); 2273 2274 /* 2275 * Try to ensure ebase resides in KSeg0 if possible. 2276 * 2277 * It shouldn't generally be in XKPhys on MIPS64 to avoid 2278 * hitting a poorly defined exception base for Cache Errors. 2279 * The allocation is likely to be in the low 512MB of physical, 2280 * in which case we should be able to convert to KSeg0. 2281 * 2282 * EVA is special though as it allows segments to be rearranged 2283 * and to become uncached during cache error handling. 2284 */ 2285 ebase_pa = __pa(ebase); 2286 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) 2287 ebase = CKSEG0ADDR(ebase_pa); 2288 } else { 2289 ebase = CAC_BASE; 2290 2291 if (cpu_has_mips_r2_r6) { 2292 if (cpu_has_ebase_wg) { 2293 #ifdef CONFIG_64BIT 2294 ebase = (read_c0_ebase_64() & ~0xfff); 2295 #else 2296 ebase = (read_c0_ebase() & ~0xfff); 2297 #endif 2298 } else { 2299 ebase += (read_c0_ebase() & 0x3ffff000); 2300 } 2301 } 2302 } 2303 2304 if (cpu_has_mmips) { 2305 unsigned int config3 = read_c0_config3(); 2306 2307 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2308 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2309 else 2310 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2311 } 2312 2313 if (board_ebase_setup) 2314 board_ebase_setup(); 2315 per_cpu_trap_init(true); 2316 2317 /* 2318 * Copy the generic exception handlers to their final destination. 2319 * This will be overridden later as suitable for a particular 2320 * configuration. 2321 */ 2322 set_handler(0x180, &except_vec3_generic, 0x80); 2323 2324 /* 2325 * Setup default vectors 2326 */ 2327 for (i = 0; i <= 31; i++) 2328 set_except_vector(i, handle_reserved); 2329 2330 /* 2331 * Copy the EJTAG debug exception vector handler code to it's final 2332 * destination. 2333 */ 2334 if (cpu_has_ejtag && board_ejtag_handler_setup) 2335 board_ejtag_handler_setup(); 2336 2337 /* 2338 * Only some CPUs have the watch exceptions. 2339 */ 2340 if (cpu_has_watch) 2341 set_except_vector(EXCCODE_WATCH, handle_watch); 2342 2343 /* 2344 * Initialise interrupt handlers 2345 */ 2346 if (cpu_has_veic || cpu_has_vint) { 2347 int nvec = cpu_has_veic ? 64 : 8; 2348 for (i = 0; i < nvec; i++) 2349 set_vi_handler(i, NULL); 2350 } 2351 else if (cpu_has_divec) 2352 set_handler(0x200, &except_vec4, 0x8); 2353 2354 /* 2355 * Some CPUs can enable/disable for cache parity detection, but does 2356 * it different ways. 2357 */ 2358 parity_protection_init(); 2359 2360 /* 2361 * The Data Bus Errors / Instruction Bus Errors are signaled 2362 * by external hardware. Therefore these two exceptions 2363 * may have board specific handlers. 2364 */ 2365 if (board_be_init) 2366 board_be_init(); 2367 2368 set_except_vector(EXCCODE_INT, using_rollback_handler() ? 2369 rollback_handle_int : handle_int); 2370 set_except_vector(EXCCODE_MOD, handle_tlbm); 2371 set_except_vector(EXCCODE_TLBL, handle_tlbl); 2372 set_except_vector(EXCCODE_TLBS, handle_tlbs); 2373 2374 set_except_vector(EXCCODE_ADEL, handle_adel); 2375 set_except_vector(EXCCODE_ADES, handle_ades); 2376 2377 set_except_vector(EXCCODE_IBE, handle_ibe); 2378 set_except_vector(EXCCODE_DBE, handle_dbe); 2379 2380 set_except_vector(EXCCODE_SYS, handle_sys); 2381 set_except_vector(EXCCODE_BP, handle_bp); 2382 2383 if (rdhwr_noopt) 2384 set_except_vector(EXCCODE_RI, handle_ri); 2385 else { 2386 if (cpu_has_vtag_icache) 2387 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2388 else if (current_cpu_type() == CPU_LOONGSON3) 2389 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp); 2390 else 2391 set_except_vector(EXCCODE_RI, handle_ri_rdhwr); 2392 } 2393 2394 set_except_vector(EXCCODE_CPU, handle_cpu); 2395 set_except_vector(EXCCODE_OV, handle_ov); 2396 set_except_vector(EXCCODE_TR, handle_tr); 2397 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe); 2398 2399 if (board_nmi_handler_setup) 2400 board_nmi_handler_setup(); 2401 2402 if (cpu_has_fpu && !cpu_has_nofpuex) 2403 set_except_vector(EXCCODE_FPE, handle_fpe); 2404 2405 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb); 2406 2407 if (cpu_has_rixiex) { 2408 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0); 2409 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0); 2410 } 2411 2412 set_except_vector(EXCCODE_MSADIS, handle_msa); 2413 set_except_vector(EXCCODE_MDMX, handle_mdmx); 2414 2415 if (cpu_has_mcheck) 2416 set_except_vector(EXCCODE_MCHECK, handle_mcheck); 2417 2418 if (cpu_has_mipsmt) 2419 set_except_vector(EXCCODE_THREAD, handle_mt); 2420 2421 set_except_vector(EXCCODE_DSPDIS, handle_dsp); 2422 2423 if (board_cache_error_setup) 2424 board_cache_error_setup(); 2425 2426 if (cpu_has_vce) 2427 /* Special exception: R4[04]00 uses also the divec space. */ 2428 set_handler(0x180, &except_vec3_r4000, 0x100); 2429 else if (cpu_has_4kex) 2430 set_handler(0x180, &except_vec3_generic, 0x80); 2431 else 2432 set_handler(0x080, &except_vec3_generic, 0x80); 2433 2434 local_flush_icache_range(ebase, ebase + 0x400); 2435 2436 sort_extable(__start___dbe_table, __stop___dbe_table); 2437 2438 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2439 } 2440 2441 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2442 void *v) 2443 { 2444 switch (cmd) { 2445 case CPU_PM_ENTER_FAILED: 2446 case CPU_PM_EXIT: 2447 configure_status(); 2448 configure_hwrena(); 2449 configure_exception_vector(); 2450 2451 /* Restore register with CPU number for TLB handlers */ 2452 TLBMISS_HANDLER_RESTORE(); 2453 2454 break; 2455 } 2456 2457 return NOTIFY_OK; 2458 } 2459 2460 static struct notifier_block trap_pm_notifier_block = { 2461 .notifier_call = trap_pm_notifier, 2462 }; 2463 2464 static int __init trap_pm_init(void) 2465 { 2466 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2467 } 2468 arch_initcall(trap_pm_init); 2469