1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 #include <linux/kgdb.h> 27 #include <linux/kdebug.h> 28 #include <linux/notifier.h> 29 #include <linux/kdb.h> 30 31 #include <asm/bootinfo.h> 32 #include <asm/branch.h> 33 #include <asm/break.h> 34 #include <asm/cop2.h> 35 #include <asm/cpu.h> 36 #include <asm/dsp.h> 37 #include <asm/fpu.h> 38 #include <asm/fpu_emulator.h> 39 #include <asm/mipsregs.h> 40 #include <asm/mipsmtregs.h> 41 #include <asm/module.h> 42 #include <asm/pgtable.h> 43 #include <asm/ptrace.h> 44 #include <asm/sections.h> 45 #include <asm/system.h> 46 #include <asm/tlbdebug.h> 47 #include <asm/traps.h> 48 #include <asm/uaccess.h> 49 #include <asm/watch.h> 50 #include <asm/mmu_context.h> 51 #include <asm/types.h> 52 #include <asm/stacktrace.h> 53 #include <asm/irq.h> 54 #include <asm/uasm.h> 55 56 extern void check_wait(void); 57 extern asmlinkage void r4k_wait(void); 58 extern asmlinkage void rollback_handle_int(void); 59 extern asmlinkage void handle_int(void); 60 extern asmlinkage void handle_tlbm(void); 61 extern asmlinkage void handle_tlbl(void); 62 extern asmlinkage void handle_tlbs(void); 63 extern asmlinkage void handle_adel(void); 64 extern asmlinkage void handle_ades(void); 65 extern asmlinkage void handle_ibe(void); 66 extern asmlinkage void handle_dbe(void); 67 extern asmlinkage void handle_sys(void); 68 extern asmlinkage void handle_bp(void); 69 extern asmlinkage void handle_ri(void); 70 extern asmlinkage void handle_ri_rdhwr_vivt(void); 71 extern asmlinkage void handle_ri_rdhwr(void); 72 extern asmlinkage void handle_cpu(void); 73 extern asmlinkage void handle_ov(void); 74 extern asmlinkage void handle_tr(void); 75 extern asmlinkage void handle_fpe(void); 76 extern asmlinkage void handle_mdmx(void); 77 extern asmlinkage void handle_watch(void); 78 extern asmlinkage void handle_mt(void); 79 extern asmlinkage void handle_dsp(void); 80 extern asmlinkage void handle_mcheck(void); 81 extern asmlinkage void handle_reserved(void); 82 83 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 84 struct mips_fpu_struct *ctx, int has_fpu); 85 86 void (*board_be_init)(void); 87 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 88 void (*board_nmi_handler_setup)(void); 89 void (*board_ejtag_handler_setup)(void); 90 void (*board_bind_eic_interrupt)(int irq, int regset); 91 92 93 static void show_raw_backtrace(unsigned long reg29) 94 { 95 unsigned long *sp = (unsigned long *)(reg29 & ~3); 96 unsigned long addr; 97 98 printk("Call Trace:"); 99 #ifdef CONFIG_KALLSYMS 100 printk("\n"); 101 #endif 102 while (!kstack_end(sp)) { 103 unsigned long __user *p = 104 (unsigned long __user *)(unsigned long)sp++; 105 if (__get_user(addr, p)) { 106 printk(" (Bad stack address)"); 107 break; 108 } 109 if (__kernel_text_address(addr)) 110 print_ip_sym(addr); 111 } 112 printk("\n"); 113 } 114 115 #ifdef CONFIG_KALLSYMS 116 int raw_show_trace; 117 static int __init set_raw_show_trace(char *str) 118 { 119 raw_show_trace = 1; 120 return 1; 121 } 122 __setup("raw_show_trace", set_raw_show_trace); 123 #endif 124 125 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 126 { 127 unsigned long sp = regs->regs[29]; 128 unsigned long ra = regs->regs[31]; 129 unsigned long pc = regs->cp0_epc; 130 131 if (raw_show_trace || !__kernel_text_address(pc)) { 132 show_raw_backtrace(sp); 133 return; 134 } 135 printk("Call Trace:\n"); 136 do { 137 print_ip_sym(pc); 138 pc = unwind_stack(task, &sp, pc, &ra); 139 } while (pc); 140 printk("\n"); 141 } 142 143 /* 144 * This routine abuses get_user()/put_user() to reference pointers 145 * with at least a bit of error checking ... 146 */ 147 static void show_stacktrace(struct task_struct *task, 148 const struct pt_regs *regs) 149 { 150 const int field = 2 * sizeof(unsigned long); 151 long stackdata; 152 int i; 153 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 154 155 printk("Stack :"); 156 i = 0; 157 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 158 if (i && ((i % (64 / field)) == 0)) 159 printk("\n "); 160 if (i > 39) { 161 printk(" ..."); 162 break; 163 } 164 165 if (__get_user(stackdata, sp++)) { 166 printk(" (Bad stack address)"); 167 break; 168 } 169 170 printk(" %0*lx", field, stackdata); 171 i++; 172 } 173 printk("\n"); 174 show_backtrace(task, regs); 175 } 176 177 void show_stack(struct task_struct *task, unsigned long *sp) 178 { 179 struct pt_regs regs; 180 if (sp) { 181 regs.regs[29] = (unsigned long)sp; 182 regs.regs[31] = 0; 183 regs.cp0_epc = 0; 184 } else { 185 if (task && task != current) { 186 regs.regs[29] = task->thread.reg29; 187 regs.regs[31] = 0; 188 regs.cp0_epc = task->thread.reg31; 189 #ifdef CONFIG_KGDB_KDB 190 } else if (atomic_read(&kgdb_active) != -1 && 191 kdb_current_regs) { 192 memcpy(®s, kdb_current_regs, sizeof(regs)); 193 #endif /* CONFIG_KGDB_KDB */ 194 } else { 195 prepare_frametrace(®s); 196 } 197 } 198 show_stacktrace(task, ®s); 199 } 200 201 /* 202 * The architecture-independent dump_stack generator 203 */ 204 void dump_stack(void) 205 { 206 struct pt_regs regs; 207 208 prepare_frametrace(®s); 209 show_backtrace(current, ®s); 210 } 211 212 EXPORT_SYMBOL(dump_stack); 213 214 static void show_code(unsigned int __user *pc) 215 { 216 long i; 217 unsigned short __user *pc16 = NULL; 218 219 printk("\nCode:"); 220 221 if ((unsigned long)pc & 1) 222 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 223 for(i = -3 ; i < 6 ; i++) { 224 unsigned int insn; 225 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 226 printk(" (Bad address in epc)\n"); 227 break; 228 } 229 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 230 } 231 } 232 233 static void __show_regs(const struct pt_regs *regs) 234 { 235 const int field = 2 * sizeof(unsigned long); 236 unsigned int cause = regs->cp0_cause; 237 int i; 238 239 printk("Cpu %d\n", smp_processor_id()); 240 241 /* 242 * Saved main processor registers 243 */ 244 for (i = 0; i < 32; ) { 245 if ((i % 4) == 0) 246 printk("$%2d :", i); 247 if (i == 0) 248 printk(" %0*lx", field, 0UL); 249 else if (i == 26 || i == 27) 250 printk(" %*s", field, ""); 251 else 252 printk(" %0*lx", field, regs->regs[i]); 253 254 i++; 255 if ((i % 4) == 0) 256 printk("\n"); 257 } 258 259 #ifdef CONFIG_CPU_HAS_SMARTMIPS 260 printk("Acx : %0*lx\n", field, regs->acx); 261 #endif 262 printk("Hi : %0*lx\n", field, regs->hi); 263 printk("Lo : %0*lx\n", field, regs->lo); 264 265 /* 266 * Saved cp0 registers 267 */ 268 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 269 (void *) regs->cp0_epc); 270 printk(" %s\n", print_tainted()); 271 printk("ra : %0*lx %pS\n", field, regs->regs[31], 272 (void *) regs->regs[31]); 273 274 printk("Status: %08x ", (uint32_t) regs->cp0_status); 275 276 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 277 if (regs->cp0_status & ST0_KUO) 278 printk("KUo "); 279 if (regs->cp0_status & ST0_IEO) 280 printk("IEo "); 281 if (regs->cp0_status & ST0_KUP) 282 printk("KUp "); 283 if (regs->cp0_status & ST0_IEP) 284 printk("IEp "); 285 if (regs->cp0_status & ST0_KUC) 286 printk("KUc "); 287 if (regs->cp0_status & ST0_IEC) 288 printk("IEc "); 289 } else { 290 if (regs->cp0_status & ST0_KX) 291 printk("KX "); 292 if (regs->cp0_status & ST0_SX) 293 printk("SX "); 294 if (regs->cp0_status & ST0_UX) 295 printk("UX "); 296 switch (regs->cp0_status & ST0_KSU) { 297 case KSU_USER: 298 printk("USER "); 299 break; 300 case KSU_SUPERVISOR: 301 printk("SUPERVISOR "); 302 break; 303 case KSU_KERNEL: 304 printk("KERNEL "); 305 break; 306 default: 307 printk("BAD_MODE "); 308 break; 309 } 310 if (regs->cp0_status & ST0_ERL) 311 printk("ERL "); 312 if (regs->cp0_status & ST0_EXL) 313 printk("EXL "); 314 if (regs->cp0_status & ST0_IE) 315 printk("IE "); 316 } 317 printk("\n"); 318 319 printk("Cause : %08x\n", cause); 320 321 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 322 if (1 <= cause && cause <= 5) 323 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 324 325 printk("PrId : %08x (%s)\n", read_c0_prid(), 326 cpu_name_string()); 327 } 328 329 /* 330 * FIXME: really the generic show_regs should take a const pointer argument. 331 */ 332 void show_regs(struct pt_regs *regs) 333 { 334 __show_regs((struct pt_regs *)regs); 335 } 336 337 void show_registers(const struct pt_regs *regs) 338 { 339 const int field = 2 * sizeof(unsigned long); 340 341 __show_regs(regs); 342 print_modules(); 343 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 344 current->comm, current->pid, current_thread_info(), current, 345 field, current_thread_info()->tp_value); 346 if (cpu_has_userlocal) { 347 unsigned long tls; 348 349 tls = read_c0_userlocal(); 350 if (tls != current_thread_info()->tp_value) 351 printk("*HwTLS: %0*lx\n", field, tls); 352 } 353 354 show_stacktrace(current, regs); 355 show_code((unsigned int __user *) regs->cp0_epc); 356 printk("\n"); 357 } 358 359 static DEFINE_SPINLOCK(die_lock); 360 361 void __noreturn die(const char * str, struct pt_regs * regs) 362 { 363 static int die_counter; 364 int sig = SIGSEGV; 365 #ifdef CONFIG_MIPS_MT_SMTC 366 unsigned long dvpret = dvpe(); 367 #endif /* CONFIG_MIPS_MT_SMTC */ 368 369 notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0); 370 371 console_verbose(); 372 spin_lock_irq(&die_lock); 373 bust_spinlocks(1); 374 #ifdef CONFIG_MIPS_MT_SMTC 375 mips_mt_regdump(dvpret); 376 #endif /* CONFIG_MIPS_MT_SMTC */ 377 378 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) 379 sig = 0; 380 381 printk("%s[#%d]:\n", str, ++die_counter); 382 show_registers(regs); 383 add_taint(TAINT_DIE); 384 spin_unlock_irq(&die_lock); 385 386 if (in_interrupt()) 387 panic("Fatal exception in interrupt"); 388 389 if (panic_on_oops) { 390 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 391 ssleep(5); 392 panic("Fatal exception"); 393 } 394 395 do_exit(sig); 396 } 397 398 extern struct exception_table_entry __start___dbe_table[]; 399 extern struct exception_table_entry __stop___dbe_table[]; 400 401 __asm__( 402 " .section __dbe_table, \"a\"\n" 403 " .previous \n"); 404 405 /* Given an address, look for it in the exception tables. */ 406 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 407 { 408 const struct exception_table_entry *e; 409 410 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 411 if (!e) 412 e = search_module_dbetables(addr); 413 return e; 414 } 415 416 asmlinkage void do_be(struct pt_regs *regs) 417 { 418 const int field = 2 * sizeof(unsigned long); 419 const struct exception_table_entry *fixup = NULL; 420 int data = regs->cp0_cause & 4; 421 int action = MIPS_BE_FATAL; 422 423 /* XXX For now. Fixme, this searches the wrong table ... */ 424 if (data && !user_mode(regs)) 425 fixup = search_dbe_tables(exception_epc(regs)); 426 427 if (fixup) 428 action = MIPS_BE_FIXUP; 429 430 if (board_be_handler) 431 action = board_be_handler(regs, fixup != NULL); 432 433 switch (action) { 434 case MIPS_BE_DISCARD: 435 return; 436 case MIPS_BE_FIXUP: 437 if (fixup) { 438 regs->cp0_epc = fixup->nextinsn; 439 return; 440 } 441 break; 442 default: 443 break; 444 } 445 446 /* 447 * Assume it would be too dangerous to continue ... 448 */ 449 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 450 data ? "Data" : "Instruction", 451 field, regs->cp0_epc, field, regs->regs[31]); 452 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) 453 == NOTIFY_STOP) 454 return; 455 456 die_if_kernel("Oops", regs); 457 force_sig(SIGBUS, current); 458 } 459 460 /* 461 * ll/sc, rdhwr, sync emulation 462 */ 463 464 #define OPCODE 0xfc000000 465 #define BASE 0x03e00000 466 #define RT 0x001f0000 467 #define OFFSET 0x0000ffff 468 #define LL 0xc0000000 469 #define SC 0xe0000000 470 #define SPEC0 0x00000000 471 #define SPEC3 0x7c000000 472 #define RD 0x0000f800 473 #define FUNC 0x0000003f 474 #define SYNC 0x0000000f 475 #define RDHWR 0x0000003b 476 477 /* 478 * The ll_bit is cleared by r*_switch.S 479 */ 480 481 unsigned int ll_bit; 482 struct task_struct *ll_task; 483 484 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 485 { 486 unsigned long value, __user *vaddr; 487 long offset; 488 489 /* 490 * analyse the ll instruction that just caused a ri exception 491 * and put the referenced address to addr. 492 */ 493 494 /* sign extend offset */ 495 offset = opcode & OFFSET; 496 offset <<= 16; 497 offset >>= 16; 498 499 vaddr = (unsigned long __user *) 500 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 501 502 if ((unsigned long)vaddr & 3) 503 return SIGBUS; 504 if (get_user(value, vaddr)) 505 return SIGSEGV; 506 507 preempt_disable(); 508 509 if (ll_task == NULL || ll_task == current) { 510 ll_bit = 1; 511 } else { 512 ll_bit = 0; 513 } 514 ll_task = current; 515 516 preempt_enable(); 517 518 regs->regs[(opcode & RT) >> 16] = value; 519 520 return 0; 521 } 522 523 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 524 { 525 unsigned long __user *vaddr; 526 unsigned long reg; 527 long offset; 528 529 /* 530 * analyse the sc instruction that just caused a ri exception 531 * and put the referenced address to addr. 532 */ 533 534 /* sign extend offset */ 535 offset = opcode & OFFSET; 536 offset <<= 16; 537 offset >>= 16; 538 539 vaddr = (unsigned long __user *) 540 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 541 reg = (opcode & RT) >> 16; 542 543 if ((unsigned long)vaddr & 3) 544 return SIGBUS; 545 546 preempt_disable(); 547 548 if (ll_bit == 0 || ll_task != current) { 549 regs->regs[reg] = 0; 550 preempt_enable(); 551 return 0; 552 } 553 554 preempt_enable(); 555 556 if (put_user(regs->regs[reg], vaddr)) 557 return SIGSEGV; 558 559 regs->regs[reg] = 1; 560 561 return 0; 562 } 563 564 /* 565 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 566 * opcodes are supposed to result in coprocessor unusable exceptions if 567 * executed on ll/sc-less processors. That's the theory. In practice a 568 * few processors such as NEC's VR4100 throw reserved instruction exceptions 569 * instead, so we're doing the emulation thing in both exception handlers. 570 */ 571 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 572 { 573 if ((opcode & OPCODE) == LL) 574 return simulate_ll(regs, opcode); 575 if ((opcode & OPCODE) == SC) 576 return simulate_sc(regs, opcode); 577 578 return -1; /* Must be something else ... */ 579 } 580 581 /* 582 * Simulate trapping 'rdhwr' instructions to provide user accessible 583 * registers not implemented in hardware. 584 */ 585 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 586 { 587 struct thread_info *ti = task_thread_info(current); 588 589 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 590 int rd = (opcode & RD) >> 11; 591 int rt = (opcode & RT) >> 16; 592 switch (rd) { 593 case 0: /* CPU number */ 594 regs->regs[rt] = smp_processor_id(); 595 return 0; 596 case 1: /* SYNCI length */ 597 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 598 current_cpu_data.icache.linesz); 599 return 0; 600 case 2: /* Read count register */ 601 regs->regs[rt] = read_c0_count(); 602 return 0; 603 case 3: /* Count register resolution */ 604 switch (current_cpu_data.cputype) { 605 case CPU_20KC: 606 case CPU_25KF: 607 regs->regs[rt] = 1; 608 break; 609 default: 610 regs->regs[rt] = 2; 611 } 612 return 0; 613 case 29: 614 regs->regs[rt] = ti->tp_value; 615 return 0; 616 default: 617 return -1; 618 } 619 } 620 621 /* Not ours. */ 622 return -1; 623 } 624 625 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 626 { 627 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 628 return 0; 629 630 return -1; /* Must be something else ... */ 631 } 632 633 asmlinkage void do_ov(struct pt_regs *regs) 634 { 635 siginfo_t info; 636 637 die_if_kernel("Integer overflow", regs); 638 639 info.si_code = FPE_INTOVF; 640 info.si_signo = SIGFPE; 641 info.si_errno = 0; 642 info.si_addr = (void __user *) regs->cp0_epc; 643 force_sig_info(SIGFPE, &info, current); 644 } 645 646 /* 647 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 648 */ 649 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 650 { 651 siginfo_t info; 652 653 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) 654 == NOTIFY_STOP) 655 return; 656 die_if_kernel("FP exception in kernel code", regs); 657 658 if (fcr31 & FPU_CSR_UNI_X) { 659 int sig; 660 661 /* 662 * Unimplemented operation exception. If we've got the full 663 * software emulator on-board, let's use it... 664 * 665 * Force FPU to dump state into task/thread context. We're 666 * moving a lot of data here for what is probably a single 667 * instruction, but the alternative is to pre-decode the FP 668 * register operands before invoking the emulator, which seems 669 * a bit extreme for what should be an infrequent event. 670 */ 671 /* Ensure 'resume' not overwrite saved fp context again. */ 672 lose_fpu(1); 673 674 /* Run the emulator */ 675 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 676 677 /* 678 * We can't allow the emulated instruction to leave any of 679 * the cause bit set in $fcr31. 680 */ 681 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 682 683 /* Restore the hardware register state */ 684 own_fpu(1); /* Using the FPU again. */ 685 686 /* If something went wrong, signal */ 687 if (sig) 688 force_sig(sig, current); 689 690 return; 691 } else if (fcr31 & FPU_CSR_INV_X) 692 info.si_code = FPE_FLTINV; 693 else if (fcr31 & FPU_CSR_DIV_X) 694 info.si_code = FPE_FLTDIV; 695 else if (fcr31 & FPU_CSR_OVF_X) 696 info.si_code = FPE_FLTOVF; 697 else if (fcr31 & FPU_CSR_UDF_X) 698 info.si_code = FPE_FLTUND; 699 else if (fcr31 & FPU_CSR_INE_X) 700 info.si_code = FPE_FLTRES; 701 else 702 info.si_code = __SI_FAULT; 703 info.si_signo = SIGFPE; 704 info.si_errno = 0; 705 info.si_addr = (void __user *) regs->cp0_epc; 706 force_sig_info(SIGFPE, &info, current); 707 } 708 709 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 710 const char *str) 711 { 712 siginfo_t info; 713 char b[40]; 714 715 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 716 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 717 return; 718 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 719 720 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 721 return; 722 723 /* 724 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 725 * insns, even for trap and break codes that indicate arithmetic 726 * failures. Weird ... 727 * But should we continue the brokenness??? --macro 728 */ 729 switch (code) { 730 case BRK_OVERFLOW: 731 case BRK_DIVZERO: 732 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 733 die_if_kernel(b, regs); 734 if (code == BRK_DIVZERO) 735 info.si_code = FPE_INTDIV; 736 else 737 info.si_code = FPE_INTOVF; 738 info.si_signo = SIGFPE; 739 info.si_errno = 0; 740 info.si_addr = (void __user *) regs->cp0_epc; 741 force_sig_info(SIGFPE, &info, current); 742 break; 743 case BRK_BUG: 744 die_if_kernel("Kernel bug detected", regs); 745 force_sig(SIGTRAP, current); 746 break; 747 case BRK_MEMU: 748 /* 749 * Address errors may be deliberately induced by the FPU 750 * emulator to retake control of the CPU after executing the 751 * instruction in the delay slot of an emulated branch. 752 * 753 * Terminate if exception was recognized as a delay slot return 754 * otherwise handle as normal. 755 */ 756 if (do_dsemulret(regs)) 757 return; 758 759 die_if_kernel("Math emu break/trap", regs); 760 force_sig(SIGTRAP, current); 761 break; 762 default: 763 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 764 die_if_kernel(b, regs); 765 force_sig(SIGTRAP, current); 766 } 767 } 768 769 asmlinkage void do_bp(struct pt_regs *regs) 770 { 771 unsigned int opcode, bcode; 772 773 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 774 goto out_sigsegv; 775 776 /* 777 * There is the ancient bug in the MIPS assemblers that the break 778 * code starts left to bit 16 instead to bit 6 in the opcode. 779 * Gas is bug-compatible, but not always, grrr... 780 * We handle both cases with a simple heuristics. --macro 781 */ 782 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 783 if (bcode >= (1 << 10)) 784 bcode >>= 10; 785 786 do_trap_or_bp(regs, bcode, "Break"); 787 return; 788 789 out_sigsegv: 790 force_sig(SIGSEGV, current); 791 } 792 793 asmlinkage void do_tr(struct pt_regs *regs) 794 { 795 unsigned int opcode, tcode = 0; 796 797 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 798 goto out_sigsegv; 799 800 /* Immediate versions don't provide a code. */ 801 if (!(opcode & OPCODE)) 802 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 803 804 do_trap_or_bp(regs, tcode, "Trap"); 805 return; 806 807 out_sigsegv: 808 force_sig(SIGSEGV, current); 809 } 810 811 asmlinkage void do_ri(struct pt_regs *regs) 812 { 813 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 814 unsigned long old_epc = regs->cp0_epc; 815 unsigned int opcode = 0; 816 int status = -1; 817 818 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) 819 == NOTIFY_STOP) 820 return; 821 822 die_if_kernel("Reserved instruction in kernel code", regs); 823 824 if (unlikely(compute_return_epc(regs) < 0)) 825 return; 826 827 if (unlikely(get_user(opcode, epc) < 0)) 828 status = SIGSEGV; 829 830 if (!cpu_has_llsc && status < 0) 831 status = simulate_llsc(regs, opcode); 832 833 if (status < 0) 834 status = simulate_rdhwr(regs, opcode); 835 836 if (status < 0) 837 status = simulate_sync(regs, opcode); 838 839 if (status < 0) 840 status = SIGILL; 841 842 if (unlikely(status > 0)) { 843 regs->cp0_epc = old_epc; /* Undo skip-over. */ 844 force_sig(status, current); 845 } 846 } 847 848 /* 849 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 850 * emulated more than some threshold number of instructions, force migration to 851 * a "CPU" that has FP support. 852 */ 853 static void mt_ase_fp_affinity(void) 854 { 855 #ifdef CONFIG_MIPS_MT_FPAFF 856 if (mt_fpemul_threshold > 0 && 857 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 858 /* 859 * If there's no FPU present, or if the application has already 860 * restricted the allowed set to exclude any CPUs with FPUs, 861 * we'll skip the procedure. 862 */ 863 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 864 cpumask_t tmask; 865 866 current->thread.user_cpus_allowed 867 = current->cpus_allowed; 868 cpus_and(tmask, current->cpus_allowed, 869 mt_fpu_cpumask); 870 set_cpus_allowed_ptr(current, &tmask); 871 set_thread_flag(TIF_FPUBOUND); 872 } 873 } 874 #endif /* CONFIG_MIPS_MT_FPAFF */ 875 } 876 877 /* 878 * No lock; only written during early bootup by CPU 0. 879 */ 880 static RAW_NOTIFIER_HEAD(cu2_chain); 881 882 int __ref register_cu2_notifier(struct notifier_block *nb) 883 { 884 return raw_notifier_chain_register(&cu2_chain, nb); 885 } 886 887 int cu2_notifier_call_chain(unsigned long val, void *v) 888 { 889 return raw_notifier_call_chain(&cu2_chain, val, v); 890 } 891 892 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 893 void *data) 894 { 895 struct pt_regs *regs = data; 896 897 switch (action) { 898 default: 899 die_if_kernel("Unhandled kernel unaligned access or invalid " 900 "instruction", regs); 901 /* Fall through */ 902 903 case CU2_EXCEPTION: 904 force_sig(SIGILL, current); 905 } 906 907 return NOTIFY_OK; 908 } 909 910 static struct notifier_block default_cu2_notifier = { 911 .notifier_call = default_cu2_call, 912 .priority = 0x80000000, /* Run last */ 913 }; 914 915 asmlinkage void do_cpu(struct pt_regs *regs) 916 { 917 unsigned int __user *epc; 918 unsigned long old_epc; 919 unsigned int opcode; 920 unsigned int cpid; 921 int status; 922 unsigned long __maybe_unused flags; 923 924 die_if_kernel("do_cpu invoked from kernel context!", regs); 925 926 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 927 928 switch (cpid) { 929 case 0: 930 epc = (unsigned int __user *)exception_epc(regs); 931 old_epc = regs->cp0_epc; 932 opcode = 0; 933 status = -1; 934 935 if (unlikely(compute_return_epc(regs) < 0)) 936 return; 937 938 if (unlikely(get_user(opcode, epc) < 0)) 939 status = SIGSEGV; 940 941 if (!cpu_has_llsc && status < 0) 942 status = simulate_llsc(regs, opcode); 943 944 if (status < 0) 945 status = simulate_rdhwr(regs, opcode); 946 947 if (status < 0) 948 status = SIGILL; 949 950 if (unlikely(status > 0)) { 951 regs->cp0_epc = old_epc; /* Undo skip-over. */ 952 force_sig(status, current); 953 } 954 955 return; 956 957 case 1: 958 if (used_math()) /* Using the FPU again. */ 959 own_fpu(1); 960 else { /* First time FPU user. */ 961 init_fpu(); 962 set_used_math(); 963 } 964 965 if (!raw_cpu_has_fpu) { 966 int sig; 967 sig = fpu_emulator_cop1Handler(regs, 968 ¤t->thread.fpu, 0); 969 if (sig) 970 force_sig(sig, current); 971 else 972 mt_ase_fp_affinity(); 973 } 974 975 return; 976 977 case 2: 978 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 979 break; 980 981 case 3: 982 break; 983 } 984 985 force_sig(SIGILL, current); 986 } 987 988 asmlinkage void do_mdmx(struct pt_regs *regs) 989 { 990 force_sig(SIGILL, current); 991 } 992 993 /* 994 * Called with interrupts disabled. 995 */ 996 asmlinkage void do_watch(struct pt_regs *regs) 997 { 998 u32 cause; 999 1000 /* 1001 * Clear WP (bit 22) bit of cause register so we don't loop 1002 * forever. 1003 */ 1004 cause = read_c0_cause(); 1005 cause &= ~(1 << 22); 1006 write_c0_cause(cause); 1007 1008 /* 1009 * If the current thread has the watch registers loaded, save 1010 * their values and send SIGTRAP. Otherwise another thread 1011 * left the registers set, clear them and continue. 1012 */ 1013 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1014 mips_read_watch_registers(); 1015 local_irq_enable(); 1016 force_sig(SIGTRAP, current); 1017 } else { 1018 mips_clear_watch_registers(); 1019 local_irq_enable(); 1020 } 1021 } 1022 1023 asmlinkage void do_mcheck(struct pt_regs *regs) 1024 { 1025 const int field = 2 * sizeof(unsigned long); 1026 int multi_match = regs->cp0_status & ST0_TS; 1027 1028 show_regs(regs); 1029 1030 if (multi_match) { 1031 printk("Index : %0x\n", read_c0_index()); 1032 printk("Pagemask: %0x\n", read_c0_pagemask()); 1033 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1034 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1035 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1036 printk("\n"); 1037 dump_tlb_all(); 1038 } 1039 1040 show_code((unsigned int __user *) regs->cp0_epc); 1041 1042 /* 1043 * Some chips may have other causes of machine check (e.g. SB1 1044 * graduation timer) 1045 */ 1046 panic("Caught Machine Check exception - %scaused by multiple " 1047 "matching entries in the TLB.", 1048 (multi_match) ? "" : "not "); 1049 } 1050 1051 asmlinkage void do_mt(struct pt_regs *regs) 1052 { 1053 int subcode; 1054 1055 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1056 >> VPECONTROL_EXCPT_SHIFT; 1057 switch (subcode) { 1058 case 0: 1059 printk(KERN_DEBUG "Thread Underflow\n"); 1060 break; 1061 case 1: 1062 printk(KERN_DEBUG "Thread Overflow\n"); 1063 break; 1064 case 2: 1065 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1066 break; 1067 case 3: 1068 printk(KERN_DEBUG "Gating Storage Exception\n"); 1069 break; 1070 case 4: 1071 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1072 break; 1073 case 5: 1074 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 1075 break; 1076 default: 1077 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1078 subcode); 1079 break; 1080 } 1081 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1082 1083 force_sig(SIGILL, current); 1084 } 1085 1086 1087 asmlinkage void do_dsp(struct pt_regs *regs) 1088 { 1089 if (cpu_has_dsp) 1090 panic("Unexpected DSP exception\n"); 1091 1092 force_sig(SIGILL, current); 1093 } 1094 1095 asmlinkage void do_reserved(struct pt_regs *regs) 1096 { 1097 /* 1098 * Game over - no way to handle this if it ever occurs. Most probably 1099 * caused by a new unknown cpu type or after another deadly 1100 * hard/software error. 1101 */ 1102 show_regs(regs); 1103 panic("Caught reserved exception %ld - should not happen.", 1104 (regs->cp0_cause & 0x7f) >> 2); 1105 } 1106 1107 static int __initdata l1parity = 1; 1108 static int __init nol1parity(char *s) 1109 { 1110 l1parity = 0; 1111 return 1; 1112 } 1113 __setup("nol1par", nol1parity); 1114 static int __initdata l2parity = 1; 1115 static int __init nol2parity(char *s) 1116 { 1117 l2parity = 0; 1118 return 1; 1119 } 1120 __setup("nol2par", nol2parity); 1121 1122 /* 1123 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1124 * it different ways. 1125 */ 1126 static inline void parity_protection_init(void) 1127 { 1128 switch (current_cpu_type()) { 1129 case CPU_24K: 1130 case CPU_34K: 1131 case CPU_74K: 1132 case CPU_1004K: 1133 { 1134 #define ERRCTL_PE 0x80000000 1135 #define ERRCTL_L2P 0x00800000 1136 unsigned long errctl; 1137 unsigned int l1parity_present, l2parity_present; 1138 1139 errctl = read_c0_ecc(); 1140 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1141 1142 /* probe L1 parity support */ 1143 write_c0_ecc(errctl | ERRCTL_PE); 1144 back_to_back_c0_hazard(); 1145 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1146 1147 /* probe L2 parity support */ 1148 write_c0_ecc(errctl|ERRCTL_L2P); 1149 back_to_back_c0_hazard(); 1150 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1151 1152 if (l1parity_present && l2parity_present) { 1153 if (l1parity) 1154 errctl |= ERRCTL_PE; 1155 if (l1parity ^ l2parity) 1156 errctl |= ERRCTL_L2P; 1157 } else if (l1parity_present) { 1158 if (l1parity) 1159 errctl |= ERRCTL_PE; 1160 } else if (l2parity_present) { 1161 if (l2parity) 1162 errctl |= ERRCTL_L2P; 1163 } else { 1164 /* No parity available */ 1165 } 1166 1167 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1168 1169 write_c0_ecc(errctl); 1170 back_to_back_c0_hazard(); 1171 errctl = read_c0_ecc(); 1172 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1173 1174 if (l1parity_present) 1175 printk(KERN_INFO "Cache parity protection %sabled\n", 1176 (errctl & ERRCTL_PE) ? "en" : "dis"); 1177 1178 if (l2parity_present) { 1179 if (l1parity_present && l1parity) 1180 errctl ^= ERRCTL_L2P; 1181 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1182 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1183 } 1184 } 1185 break; 1186 1187 case CPU_5KC: 1188 write_c0_ecc(0x80000000); 1189 back_to_back_c0_hazard(); 1190 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1191 printk(KERN_INFO "Cache parity protection %sabled\n", 1192 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1193 break; 1194 case CPU_20KC: 1195 case CPU_25KF: 1196 /* Clear the DE bit (bit 16) in the c0_status register. */ 1197 printk(KERN_INFO "Enable cache parity protection for " 1198 "MIPS 20KC/25KF CPUs.\n"); 1199 clear_c0_status(ST0_DE); 1200 break; 1201 default: 1202 break; 1203 } 1204 } 1205 1206 asmlinkage void cache_parity_error(void) 1207 { 1208 const int field = 2 * sizeof(unsigned long); 1209 unsigned int reg_val; 1210 1211 /* For the moment, report the problem and hang. */ 1212 printk("Cache error exception:\n"); 1213 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1214 reg_val = read_c0_cacheerr(); 1215 printk("c0_cacheerr == %08x\n", reg_val); 1216 1217 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1218 reg_val & (1<<30) ? "secondary" : "primary", 1219 reg_val & (1<<31) ? "data" : "insn"); 1220 printk("Error bits: %s%s%s%s%s%s%s\n", 1221 reg_val & (1<<29) ? "ED " : "", 1222 reg_val & (1<<28) ? "ET " : "", 1223 reg_val & (1<<26) ? "EE " : "", 1224 reg_val & (1<<25) ? "EB " : "", 1225 reg_val & (1<<24) ? "EI " : "", 1226 reg_val & (1<<23) ? "E1 " : "", 1227 reg_val & (1<<22) ? "E0 " : ""); 1228 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1229 1230 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1231 if (reg_val & (1<<22)) 1232 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1233 1234 if (reg_val & (1<<23)) 1235 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1236 #endif 1237 1238 panic("Can't handle the cache error!"); 1239 } 1240 1241 /* 1242 * SDBBP EJTAG debug exception handler. 1243 * We skip the instruction and return to the next instruction. 1244 */ 1245 void ejtag_exception_handler(struct pt_regs *regs) 1246 { 1247 const int field = 2 * sizeof(unsigned long); 1248 unsigned long depc, old_epc; 1249 unsigned int debug; 1250 1251 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1252 depc = read_c0_depc(); 1253 debug = read_c0_debug(); 1254 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1255 if (debug & 0x80000000) { 1256 /* 1257 * In branch delay slot. 1258 * We cheat a little bit here and use EPC to calculate the 1259 * debug return address (DEPC). EPC is restored after the 1260 * calculation. 1261 */ 1262 old_epc = regs->cp0_epc; 1263 regs->cp0_epc = depc; 1264 __compute_return_epc(regs); 1265 depc = regs->cp0_epc; 1266 regs->cp0_epc = old_epc; 1267 } else 1268 depc += 4; 1269 write_c0_depc(depc); 1270 1271 #if 0 1272 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1273 write_c0_debug(debug | 0x100); 1274 #endif 1275 } 1276 1277 /* 1278 * NMI exception handler. 1279 */ 1280 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1281 { 1282 bust_spinlocks(1); 1283 printk("NMI taken!!!!\n"); 1284 die("NMI", regs); 1285 } 1286 1287 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1288 1289 unsigned long ebase; 1290 unsigned long exception_handlers[32]; 1291 unsigned long vi_handlers[64]; 1292 1293 void __init *set_except_vector(int n, void *addr) 1294 { 1295 unsigned long handler = (unsigned long) addr; 1296 unsigned long old_handler = exception_handlers[n]; 1297 1298 exception_handlers[n] = handler; 1299 if (n == 0 && cpu_has_divec) { 1300 unsigned long jump_mask = ~((1 << 28) - 1); 1301 u32 *buf = (u32 *)(ebase + 0x200); 1302 unsigned int k0 = 26; 1303 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1304 uasm_i_j(&buf, handler & ~jump_mask); 1305 uasm_i_nop(&buf); 1306 } else { 1307 UASM_i_LA(&buf, k0, handler); 1308 uasm_i_jr(&buf, k0); 1309 uasm_i_nop(&buf); 1310 } 1311 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1312 } 1313 return (void *)old_handler; 1314 } 1315 1316 static asmlinkage void do_default_vi(void) 1317 { 1318 show_regs(get_irq_regs()); 1319 panic("Caught unexpected vectored interrupt."); 1320 } 1321 1322 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1323 { 1324 unsigned long handler; 1325 unsigned long old_handler = vi_handlers[n]; 1326 int srssets = current_cpu_data.srsets; 1327 u32 *w; 1328 unsigned char *b; 1329 1330 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1331 1332 if (addr == NULL) { 1333 handler = (unsigned long) do_default_vi; 1334 srs = 0; 1335 } else 1336 handler = (unsigned long) addr; 1337 vi_handlers[n] = (unsigned long) addr; 1338 1339 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1340 1341 if (srs >= srssets) 1342 panic("Shadow register set %d not supported", srs); 1343 1344 if (cpu_has_veic) { 1345 if (board_bind_eic_interrupt) 1346 board_bind_eic_interrupt(n, srs); 1347 } else if (cpu_has_vint) { 1348 /* SRSMap is only defined if shadow sets are implemented */ 1349 if (srssets > 1) 1350 change_c0_srsmap(0xf << n*4, srs << n*4); 1351 } 1352 1353 if (srs == 0) { 1354 /* 1355 * If no shadow set is selected then use the default handler 1356 * that does normal register saving and a standard interrupt exit 1357 */ 1358 1359 extern char except_vec_vi, except_vec_vi_lui; 1360 extern char except_vec_vi_ori, except_vec_vi_end; 1361 extern char rollback_except_vec_vi; 1362 char *vec_start = (cpu_wait == r4k_wait) ? 1363 &rollback_except_vec_vi : &except_vec_vi; 1364 #ifdef CONFIG_MIPS_MT_SMTC 1365 /* 1366 * We need to provide the SMTC vectored interrupt handler 1367 * not only with the address of the handler, but with the 1368 * Status.IM bit to be masked before going there. 1369 */ 1370 extern char except_vec_vi_mori; 1371 const int mori_offset = &except_vec_vi_mori - vec_start; 1372 #endif /* CONFIG_MIPS_MT_SMTC */ 1373 const int handler_len = &except_vec_vi_end - vec_start; 1374 const int lui_offset = &except_vec_vi_lui - vec_start; 1375 const int ori_offset = &except_vec_vi_ori - vec_start; 1376 1377 if (handler_len > VECTORSPACING) { 1378 /* 1379 * Sigh... panicing won't help as the console 1380 * is probably not configured :( 1381 */ 1382 panic("VECTORSPACING too small"); 1383 } 1384 1385 memcpy(b, vec_start, handler_len); 1386 #ifdef CONFIG_MIPS_MT_SMTC 1387 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1388 1389 w = (u32 *)(b + mori_offset); 1390 *w = (*w & 0xffff0000) | (0x100 << n); 1391 #endif /* CONFIG_MIPS_MT_SMTC */ 1392 w = (u32 *)(b + lui_offset); 1393 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1394 w = (u32 *)(b + ori_offset); 1395 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1396 local_flush_icache_range((unsigned long)b, 1397 (unsigned long)(b+handler_len)); 1398 } 1399 else { 1400 /* 1401 * In other cases jump directly to the interrupt handler 1402 * 1403 * It is the handlers responsibility to save registers if required 1404 * (eg hi/lo) and return from the exception using "eret" 1405 */ 1406 w = (u32 *)b; 1407 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1408 *w = 0; 1409 local_flush_icache_range((unsigned long)b, 1410 (unsigned long)(b+8)); 1411 } 1412 1413 return (void *)old_handler; 1414 } 1415 1416 void *set_vi_handler(int n, vi_handler_t addr) 1417 { 1418 return set_vi_srs_handler(n, addr, 0); 1419 } 1420 1421 extern void cpu_cache_init(void); 1422 extern void tlb_init(void); 1423 extern void flush_tlb_handlers(void); 1424 1425 /* 1426 * Timer interrupt 1427 */ 1428 int cp0_compare_irq; 1429 int cp0_compare_irq_shift; 1430 1431 /* 1432 * Performance counter IRQ or -1 if shared with timer 1433 */ 1434 int cp0_perfcount_irq; 1435 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1436 1437 static int __cpuinitdata noulri; 1438 1439 static int __init ulri_disable(char *s) 1440 { 1441 pr_info("Disabling ulri\n"); 1442 noulri = 1; 1443 1444 return 1; 1445 } 1446 __setup("noulri", ulri_disable); 1447 1448 void __cpuinit per_cpu_trap_init(void) 1449 { 1450 unsigned int cpu = smp_processor_id(); 1451 unsigned int status_set = ST0_CU0; 1452 #ifdef CONFIG_MIPS_MT_SMTC 1453 int secondaryTC = 0; 1454 int bootTC = (cpu == 0); 1455 1456 /* 1457 * Only do per_cpu_trap_init() for first TC of Each VPE. 1458 * Note that this hack assumes that the SMTC init code 1459 * assigns TCs consecutively and in ascending order. 1460 */ 1461 1462 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1463 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1464 secondaryTC = 1; 1465 #endif /* CONFIG_MIPS_MT_SMTC */ 1466 1467 /* 1468 * Disable coprocessors and select 32-bit or 64-bit addressing 1469 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1470 * flag that some firmware may have left set and the TS bit (for 1471 * IP27). Set XX for ISA IV code to work. 1472 */ 1473 #ifdef CONFIG_64BIT 1474 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1475 #endif 1476 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1477 status_set |= ST0_XX; 1478 if (cpu_has_dsp) 1479 status_set |= ST0_MX; 1480 1481 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1482 status_set); 1483 1484 if (cpu_has_mips_r2) { 1485 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits; 1486 1487 if (!noulri && cpu_has_userlocal) 1488 enable |= (1 << 29); 1489 1490 write_c0_hwrena(enable); 1491 } 1492 1493 #ifdef CONFIG_MIPS_MT_SMTC 1494 if (!secondaryTC) { 1495 #endif /* CONFIG_MIPS_MT_SMTC */ 1496 1497 if (cpu_has_veic || cpu_has_vint) { 1498 unsigned long sr = set_c0_status(ST0_BEV); 1499 write_c0_ebase(ebase); 1500 write_c0_status(sr); 1501 /* Setting vector spacing enables EI/VI mode */ 1502 change_c0_intctl(0x3e0, VECTORSPACING); 1503 } 1504 if (cpu_has_divec) { 1505 if (cpu_has_mipsmt) { 1506 unsigned int vpflags = dvpe(); 1507 set_c0_cause(CAUSEF_IV); 1508 evpe(vpflags); 1509 } else 1510 set_c0_cause(CAUSEF_IV); 1511 } 1512 1513 /* 1514 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1515 * 1516 * o read IntCtl.IPTI to determine the timer interrupt 1517 * o read IntCtl.IPPCI to determine the performance counter interrupt 1518 */ 1519 if (cpu_has_mips_r2) { 1520 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1521 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1522 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1523 if (cp0_perfcount_irq == cp0_compare_irq) 1524 cp0_perfcount_irq = -1; 1525 } else { 1526 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1527 cp0_compare_irq_shift = cp0_compare_irq; 1528 cp0_perfcount_irq = -1; 1529 } 1530 1531 #ifdef CONFIG_MIPS_MT_SMTC 1532 } 1533 #endif /* CONFIG_MIPS_MT_SMTC */ 1534 1535 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1536 TLBMISS_HANDLER_SETUP(); 1537 1538 atomic_inc(&init_mm.mm_count); 1539 current->active_mm = &init_mm; 1540 BUG_ON(current->mm); 1541 enter_lazy_tlb(&init_mm, current); 1542 1543 #ifdef CONFIG_MIPS_MT_SMTC 1544 if (bootTC) { 1545 #endif /* CONFIG_MIPS_MT_SMTC */ 1546 cpu_cache_init(); 1547 tlb_init(); 1548 #ifdef CONFIG_MIPS_MT_SMTC 1549 } else if (!secondaryTC) { 1550 /* 1551 * First TC in non-boot VPE must do subset of tlb_init() 1552 * for MMU countrol registers. 1553 */ 1554 write_c0_pagemask(PM_DEFAULT_MASK); 1555 write_c0_wired(0); 1556 } 1557 #endif /* CONFIG_MIPS_MT_SMTC */ 1558 } 1559 1560 /* Install CPU exception handler */ 1561 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1562 { 1563 memcpy((void *)(ebase + offset), addr, size); 1564 local_flush_icache_range(ebase + offset, ebase + offset + size); 1565 } 1566 1567 static char panic_null_cerr[] __cpuinitdata = 1568 "Trying to set NULL cache error exception handler"; 1569 1570 /* 1571 * Install uncached CPU exception handler. 1572 * This is suitable only for the cache error exception which is the only 1573 * exception handler that is being run uncached. 1574 */ 1575 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1576 unsigned long size) 1577 { 1578 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1579 1580 if (!addr) 1581 panic(panic_null_cerr); 1582 1583 memcpy((void *)(uncached_ebase + offset), addr, size); 1584 } 1585 1586 static int __initdata rdhwr_noopt; 1587 static int __init set_rdhwr_noopt(char *str) 1588 { 1589 rdhwr_noopt = 1; 1590 return 1; 1591 } 1592 1593 __setup("rdhwr_noopt", set_rdhwr_noopt); 1594 1595 void __init trap_init(void) 1596 { 1597 extern char except_vec3_generic, except_vec3_r4000; 1598 extern char except_vec4; 1599 unsigned long i; 1600 int rollback; 1601 1602 check_wait(); 1603 rollback = (cpu_wait == r4k_wait); 1604 1605 #if defined(CONFIG_KGDB) 1606 if (kgdb_early_setup) 1607 return; /* Already done */ 1608 #endif 1609 1610 if (cpu_has_veic || cpu_has_vint) { 1611 unsigned long size = 0x200 + VECTORSPACING*64; 1612 ebase = (unsigned long) 1613 __alloc_bootmem(size, 1 << fls(size), 0); 1614 } else { 1615 ebase = CKSEG0; 1616 if (cpu_has_mips_r2) 1617 ebase += (read_c0_ebase() & 0x3ffff000); 1618 } 1619 1620 per_cpu_trap_init(); 1621 1622 /* 1623 * Copy the generic exception handlers to their final destination. 1624 * This will be overriden later as suitable for a particular 1625 * configuration. 1626 */ 1627 set_handler(0x180, &except_vec3_generic, 0x80); 1628 1629 /* 1630 * Setup default vectors 1631 */ 1632 for (i = 0; i <= 31; i++) 1633 set_except_vector(i, handle_reserved); 1634 1635 /* 1636 * Copy the EJTAG debug exception vector handler code to it's final 1637 * destination. 1638 */ 1639 if (cpu_has_ejtag && board_ejtag_handler_setup) 1640 board_ejtag_handler_setup(); 1641 1642 /* 1643 * Only some CPUs have the watch exceptions. 1644 */ 1645 if (cpu_has_watch) 1646 set_except_vector(23, handle_watch); 1647 1648 /* 1649 * Initialise interrupt handlers 1650 */ 1651 if (cpu_has_veic || cpu_has_vint) { 1652 int nvec = cpu_has_veic ? 64 : 8; 1653 for (i = 0; i < nvec; i++) 1654 set_vi_handler(i, NULL); 1655 } 1656 else if (cpu_has_divec) 1657 set_handler(0x200, &except_vec4, 0x8); 1658 1659 /* 1660 * Some CPUs can enable/disable for cache parity detection, but does 1661 * it different ways. 1662 */ 1663 parity_protection_init(); 1664 1665 /* 1666 * The Data Bus Errors / Instruction Bus Errors are signaled 1667 * by external hardware. Therefore these two exceptions 1668 * may have board specific handlers. 1669 */ 1670 if (board_be_init) 1671 board_be_init(); 1672 1673 set_except_vector(0, rollback ? rollback_handle_int : handle_int); 1674 set_except_vector(1, handle_tlbm); 1675 set_except_vector(2, handle_tlbl); 1676 set_except_vector(3, handle_tlbs); 1677 1678 set_except_vector(4, handle_adel); 1679 set_except_vector(5, handle_ades); 1680 1681 set_except_vector(6, handle_ibe); 1682 set_except_vector(7, handle_dbe); 1683 1684 set_except_vector(8, handle_sys); 1685 set_except_vector(9, handle_bp); 1686 set_except_vector(10, rdhwr_noopt ? handle_ri : 1687 (cpu_has_vtag_icache ? 1688 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1689 set_except_vector(11, handle_cpu); 1690 set_except_vector(12, handle_ov); 1691 set_except_vector(13, handle_tr); 1692 1693 if (current_cpu_type() == CPU_R6000 || 1694 current_cpu_type() == CPU_R6000A) { 1695 /* 1696 * The R6000 is the only R-series CPU that features a machine 1697 * check exception (similar to the R4000 cache error) and 1698 * unaligned ldc1/sdc1 exception. The handlers have not been 1699 * written yet. Well, anyway there is no R6000 machine on the 1700 * current list of targets for Linux/MIPS. 1701 * (Duh, crap, there is someone with a triple R6k machine) 1702 */ 1703 //set_except_vector(14, handle_mc); 1704 //set_except_vector(15, handle_ndc); 1705 } 1706 1707 1708 if (board_nmi_handler_setup) 1709 board_nmi_handler_setup(); 1710 1711 if (cpu_has_fpu && !cpu_has_nofpuex) 1712 set_except_vector(15, handle_fpe); 1713 1714 set_except_vector(22, handle_mdmx); 1715 1716 if (cpu_has_mcheck) 1717 set_except_vector(24, handle_mcheck); 1718 1719 if (cpu_has_mipsmt) 1720 set_except_vector(25, handle_mt); 1721 1722 set_except_vector(26, handle_dsp); 1723 1724 if (cpu_has_vce) 1725 /* Special exception: R4[04]00 uses also the divec space. */ 1726 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1727 else if (cpu_has_4kex) 1728 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); 1729 else 1730 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1731 1732 local_flush_icache_range(ebase, ebase + 0x400); 1733 flush_tlb_handlers(); 1734 1735 sort_extable(__start___dbe_table, __stop___dbe_table); 1736 1737 register_cu2_notifier(&default_cu2_notifier); 1738 } 1739