1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/init.h> 15 #include <linux/mm.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/spinlock.h> 20 #include <linux/kallsyms.h> 21 #include <linux/bootmem.h> 22 #include <linux/interrupt.h> 23 24 #include <asm/bootinfo.h> 25 #include <asm/branch.h> 26 #include <asm/break.h> 27 #include <asm/cpu.h> 28 #include <asm/dsp.h> 29 #include <asm/fpu.h> 30 #include <asm/mipsregs.h> 31 #include <asm/mipsmtregs.h> 32 #include <asm/module.h> 33 #include <asm/pgtable.h> 34 #include <asm/ptrace.h> 35 #include <asm/sections.h> 36 #include <asm/system.h> 37 #include <asm/tlbdebug.h> 38 #include <asm/traps.h> 39 #include <asm/uaccess.h> 40 #include <asm/mmu_context.h> 41 #include <asm/watch.h> 42 #include <asm/types.h> 43 #include <asm/stacktrace.h> 44 45 extern asmlinkage void handle_int(void); 46 extern asmlinkage void handle_tlbm(void); 47 extern asmlinkage void handle_tlbl(void); 48 extern asmlinkage void handle_tlbs(void); 49 extern asmlinkage void handle_adel(void); 50 extern asmlinkage void handle_ades(void); 51 extern asmlinkage void handle_ibe(void); 52 extern asmlinkage void handle_dbe(void); 53 extern asmlinkage void handle_sys(void); 54 extern asmlinkage void handle_bp(void); 55 extern asmlinkage void handle_ri(void); 56 extern asmlinkage void handle_ri_rdhwr_vivt(void); 57 extern asmlinkage void handle_ri_rdhwr(void); 58 extern asmlinkage void handle_cpu(void); 59 extern asmlinkage void handle_ov(void); 60 extern asmlinkage void handle_tr(void); 61 extern asmlinkage void handle_fpe(void); 62 extern asmlinkage void handle_mdmx(void); 63 extern asmlinkage void handle_watch(void); 64 extern asmlinkage void handle_mt(void); 65 extern asmlinkage void handle_dsp(void); 66 extern asmlinkage void handle_mcheck(void); 67 extern asmlinkage void handle_reserved(void); 68 69 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 70 struct mips_fpu_struct *ctx, int has_fpu); 71 72 void (*board_be_init)(void); 73 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 74 void (*board_nmi_handler_setup)(void); 75 void (*board_ejtag_handler_setup)(void); 76 void (*board_bind_eic_interrupt)(int irq, int regset); 77 78 79 static void show_raw_backtrace(unsigned long reg29) 80 { 81 unsigned long *sp = (unsigned long *)reg29; 82 unsigned long addr; 83 84 printk("Call Trace:"); 85 #ifdef CONFIG_KALLSYMS 86 printk("\n"); 87 #endif 88 while (!kstack_end(sp)) { 89 addr = *sp++; 90 if (__kernel_text_address(addr)) 91 print_ip_sym(addr); 92 } 93 printk("\n"); 94 } 95 96 #ifdef CONFIG_KALLSYMS 97 int raw_show_trace; 98 static int __init set_raw_show_trace(char *str) 99 { 100 raw_show_trace = 1; 101 return 1; 102 } 103 __setup("raw_show_trace", set_raw_show_trace); 104 #endif 105 106 static void show_backtrace(struct task_struct *task, struct pt_regs *regs) 107 { 108 unsigned long sp = regs->regs[29]; 109 unsigned long ra = regs->regs[31]; 110 unsigned long pc = regs->cp0_epc; 111 112 if (raw_show_trace || !__kernel_text_address(pc)) { 113 show_raw_backtrace(sp); 114 return; 115 } 116 printk("Call Trace:\n"); 117 do { 118 print_ip_sym(pc); 119 pc = unwind_stack(task, &sp, pc, &ra); 120 } while (pc); 121 printk("\n"); 122 } 123 124 /* 125 * This routine abuses get_user()/put_user() to reference pointers 126 * with at least a bit of error checking ... 127 */ 128 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) 129 { 130 const int field = 2 * sizeof(unsigned long); 131 long stackdata; 132 int i; 133 unsigned long *sp = (unsigned long *)regs->regs[29]; 134 135 printk("Stack :"); 136 i = 0; 137 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 138 if (i && ((i % (64 / field)) == 0)) 139 printk("\n "); 140 if (i > 39) { 141 printk(" ..."); 142 break; 143 } 144 145 if (__get_user(stackdata, sp++)) { 146 printk(" (Bad stack address)"); 147 break; 148 } 149 150 printk(" %0*lx", field, stackdata); 151 i++; 152 } 153 printk("\n"); 154 show_backtrace(task, regs); 155 } 156 157 void show_stack(struct task_struct *task, unsigned long *sp) 158 { 159 struct pt_regs regs; 160 if (sp) { 161 regs.regs[29] = (unsigned long)sp; 162 regs.regs[31] = 0; 163 regs.cp0_epc = 0; 164 } else { 165 if (task && task != current) { 166 regs.regs[29] = task->thread.reg29; 167 regs.regs[31] = 0; 168 regs.cp0_epc = task->thread.reg31; 169 } else { 170 prepare_frametrace(®s); 171 } 172 } 173 show_stacktrace(task, ®s); 174 } 175 176 /* 177 * The architecture-independent dump_stack generator 178 */ 179 void dump_stack(void) 180 { 181 struct pt_regs regs; 182 183 prepare_frametrace(®s); 184 show_backtrace(current, ®s); 185 } 186 187 EXPORT_SYMBOL(dump_stack); 188 189 void show_code(unsigned int *pc) 190 { 191 long i; 192 193 printk("\nCode:"); 194 195 for(i = -3 ; i < 6 ; i++) { 196 unsigned int insn; 197 if (__get_user(insn, pc + i)) { 198 printk(" (Bad address in epc)\n"); 199 break; 200 } 201 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 202 } 203 } 204 205 void show_regs(struct pt_regs *regs) 206 { 207 const int field = 2 * sizeof(unsigned long); 208 unsigned int cause = regs->cp0_cause; 209 int i; 210 211 printk("Cpu %d\n", smp_processor_id()); 212 213 /* 214 * Saved main processor registers 215 */ 216 for (i = 0; i < 32; ) { 217 if ((i % 4) == 0) 218 printk("$%2d :", i); 219 if (i == 0) 220 printk(" %0*lx", field, 0UL); 221 else if (i == 26 || i == 27) 222 printk(" %*s", field, ""); 223 else 224 printk(" %0*lx", field, regs->regs[i]); 225 226 i++; 227 if ((i % 4) == 0) 228 printk("\n"); 229 } 230 231 #ifdef CONFIG_CPU_HAS_SMARTMIPS 232 printk("Acx : %0*lx\n", field, regs->acx); 233 #endif 234 printk("Hi : %0*lx\n", field, regs->hi); 235 printk("Lo : %0*lx\n", field, regs->lo); 236 237 /* 238 * Saved cp0 registers 239 */ 240 printk("epc : %0*lx ", field, regs->cp0_epc); 241 print_symbol("%s ", regs->cp0_epc); 242 printk(" %s\n", print_tainted()); 243 printk("ra : %0*lx ", field, regs->regs[31]); 244 print_symbol("%s\n", regs->regs[31]); 245 246 printk("Status: %08x ", (uint32_t) regs->cp0_status); 247 248 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 249 if (regs->cp0_status & ST0_KUO) 250 printk("KUo "); 251 if (regs->cp0_status & ST0_IEO) 252 printk("IEo "); 253 if (regs->cp0_status & ST0_KUP) 254 printk("KUp "); 255 if (regs->cp0_status & ST0_IEP) 256 printk("IEp "); 257 if (regs->cp0_status & ST0_KUC) 258 printk("KUc "); 259 if (regs->cp0_status & ST0_IEC) 260 printk("IEc "); 261 } else { 262 if (regs->cp0_status & ST0_KX) 263 printk("KX "); 264 if (regs->cp0_status & ST0_SX) 265 printk("SX "); 266 if (regs->cp0_status & ST0_UX) 267 printk("UX "); 268 switch (regs->cp0_status & ST0_KSU) { 269 case KSU_USER: 270 printk("USER "); 271 break; 272 case KSU_SUPERVISOR: 273 printk("SUPERVISOR "); 274 break; 275 case KSU_KERNEL: 276 printk("KERNEL "); 277 break; 278 default: 279 printk("BAD_MODE "); 280 break; 281 } 282 if (regs->cp0_status & ST0_ERL) 283 printk("ERL "); 284 if (regs->cp0_status & ST0_EXL) 285 printk("EXL "); 286 if (regs->cp0_status & ST0_IE) 287 printk("IE "); 288 } 289 printk("\n"); 290 291 printk("Cause : %08x\n", cause); 292 293 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 294 if (1 <= cause && cause <= 5) 295 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 296 297 printk("PrId : %08x\n", read_c0_prid()); 298 } 299 300 void show_registers(struct pt_regs *regs) 301 { 302 show_regs(regs); 303 print_modules(); 304 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 305 current->comm, current->pid, current_thread_info(), current); 306 show_stacktrace(current, regs); 307 show_code((unsigned int *) regs->cp0_epc); 308 printk("\n"); 309 } 310 311 static DEFINE_SPINLOCK(die_lock); 312 313 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) 314 { 315 static int die_counter; 316 #ifdef CONFIG_MIPS_MT_SMTC 317 unsigned long dvpret = dvpe(); 318 #endif /* CONFIG_MIPS_MT_SMTC */ 319 320 console_verbose(); 321 spin_lock_irq(&die_lock); 322 bust_spinlocks(1); 323 #ifdef CONFIG_MIPS_MT_SMTC 324 mips_mt_regdump(dvpret); 325 #endif /* CONFIG_MIPS_MT_SMTC */ 326 printk("%s[#%d]:\n", str, ++die_counter); 327 show_registers(regs); 328 spin_unlock_irq(&die_lock); 329 330 if (in_interrupt()) 331 panic("Fatal exception in interrupt"); 332 333 if (panic_on_oops) { 334 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 335 ssleep(5); 336 panic("Fatal exception"); 337 } 338 339 do_exit(SIGSEGV); 340 } 341 342 extern const struct exception_table_entry __start___dbe_table[]; 343 extern const struct exception_table_entry __stop___dbe_table[]; 344 345 __asm__( 346 " .section __dbe_table, \"a\"\n" 347 " .previous \n"); 348 349 /* Given an address, look for it in the exception tables. */ 350 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 351 { 352 const struct exception_table_entry *e; 353 354 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 355 if (!e) 356 e = search_module_dbetables(addr); 357 return e; 358 } 359 360 asmlinkage void do_be(struct pt_regs *regs) 361 { 362 const int field = 2 * sizeof(unsigned long); 363 const struct exception_table_entry *fixup = NULL; 364 int data = regs->cp0_cause & 4; 365 int action = MIPS_BE_FATAL; 366 367 /* XXX For now. Fixme, this searches the wrong table ... */ 368 if (data && !user_mode(regs)) 369 fixup = search_dbe_tables(exception_epc(regs)); 370 371 if (fixup) 372 action = MIPS_BE_FIXUP; 373 374 if (board_be_handler) 375 action = board_be_handler(regs, fixup != 0); 376 377 switch (action) { 378 case MIPS_BE_DISCARD: 379 return; 380 case MIPS_BE_FIXUP: 381 if (fixup) { 382 regs->cp0_epc = fixup->nextinsn; 383 return; 384 } 385 break; 386 default: 387 break; 388 } 389 390 /* 391 * Assume it would be too dangerous to continue ... 392 */ 393 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 394 data ? "Data" : "Instruction", 395 field, regs->cp0_epc, field, regs->regs[31]); 396 die_if_kernel("Oops", regs); 397 force_sig(SIGBUS, current); 398 } 399 400 /* 401 * ll/sc emulation 402 */ 403 404 #define OPCODE 0xfc000000 405 #define BASE 0x03e00000 406 #define RT 0x001f0000 407 #define OFFSET 0x0000ffff 408 #define LL 0xc0000000 409 #define SC 0xe0000000 410 #define SPEC3 0x7c000000 411 #define RD 0x0000f800 412 #define FUNC 0x0000003f 413 #define RDHWR 0x0000003b 414 415 /* 416 * The ll_bit is cleared by r*_switch.S 417 */ 418 419 unsigned long ll_bit; 420 421 static struct task_struct *ll_task = NULL; 422 423 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 424 { 425 unsigned long value, __user *vaddr; 426 long offset; 427 int signal = 0; 428 429 /* 430 * analyse the ll instruction that just caused a ri exception 431 * and put the referenced address to addr. 432 */ 433 434 /* sign extend offset */ 435 offset = opcode & OFFSET; 436 offset <<= 16; 437 offset >>= 16; 438 439 vaddr = (unsigned long __user *) 440 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 441 442 if ((unsigned long)vaddr & 3) { 443 signal = SIGBUS; 444 goto sig; 445 } 446 if (get_user(value, vaddr)) { 447 signal = SIGSEGV; 448 goto sig; 449 } 450 451 preempt_disable(); 452 453 if (ll_task == NULL || ll_task == current) { 454 ll_bit = 1; 455 } else { 456 ll_bit = 0; 457 } 458 ll_task = current; 459 460 preempt_enable(); 461 462 compute_return_epc(regs); 463 464 regs->regs[(opcode & RT) >> 16] = value; 465 466 return; 467 468 sig: 469 force_sig(signal, current); 470 } 471 472 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 473 { 474 unsigned long __user *vaddr; 475 unsigned long reg; 476 long offset; 477 int signal = 0; 478 479 /* 480 * analyse the sc instruction that just caused a ri exception 481 * and put the referenced address to addr. 482 */ 483 484 /* sign extend offset */ 485 offset = opcode & OFFSET; 486 offset <<= 16; 487 offset >>= 16; 488 489 vaddr = (unsigned long __user *) 490 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 491 reg = (opcode & RT) >> 16; 492 493 if ((unsigned long)vaddr & 3) { 494 signal = SIGBUS; 495 goto sig; 496 } 497 498 preempt_disable(); 499 500 if (ll_bit == 0 || ll_task != current) { 501 compute_return_epc(regs); 502 regs->regs[reg] = 0; 503 preempt_enable(); 504 return; 505 } 506 507 preempt_enable(); 508 509 if (put_user(regs->regs[reg], vaddr)) { 510 signal = SIGSEGV; 511 goto sig; 512 } 513 514 compute_return_epc(regs); 515 regs->regs[reg] = 1; 516 517 return; 518 519 sig: 520 force_sig(signal, current); 521 } 522 523 /* 524 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 525 * opcodes are supposed to result in coprocessor unusable exceptions if 526 * executed on ll/sc-less processors. That's the theory. In practice a 527 * few processors such as NEC's VR4100 throw reserved instruction exceptions 528 * instead, so we're doing the emulation thing in both exception handlers. 529 */ 530 static inline int simulate_llsc(struct pt_regs *regs) 531 { 532 unsigned int opcode; 533 534 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 535 goto out_sigsegv; 536 537 if ((opcode & OPCODE) == LL) { 538 simulate_ll(regs, opcode); 539 return 0; 540 } 541 if ((opcode & OPCODE) == SC) { 542 simulate_sc(regs, opcode); 543 return 0; 544 } 545 546 return -EFAULT; /* Strange things going on ... */ 547 548 out_sigsegv: 549 force_sig(SIGSEGV, current); 550 return -EFAULT; 551 } 552 553 /* 554 * Simulate trapping 'rdhwr' instructions to provide user accessible 555 * registers not implemented in hardware. The only current use of this 556 * is the thread area pointer. 557 */ 558 static inline int simulate_rdhwr(struct pt_regs *regs) 559 { 560 struct thread_info *ti = task_thread_info(current); 561 unsigned int opcode; 562 563 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 564 goto out_sigsegv; 565 566 if (unlikely(compute_return_epc(regs))) 567 return -EFAULT; 568 569 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 570 int rd = (opcode & RD) >> 11; 571 int rt = (opcode & RT) >> 16; 572 switch (rd) { 573 case 29: 574 regs->regs[rt] = ti->tp_value; 575 return 0; 576 default: 577 return -EFAULT; 578 } 579 } 580 581 /* Not ours. */ 582 return -EFAULT; 583 584 out_sigsegv: 585 force_sig(SIGSEGV, current); 586 return -EFAULT; 587 } 588 589 asmlinkage void do_ov(struct pt_regs *regs) 590 { 591 siginfo_t info; 592 593 die_if_kernel("Integer overflow", regs); 594 595 info.si_code = FPE_INTOVF; 596 info.si_signo = SIGFPE; 597 info.si_errno = 0; 598 info.si_addr = (void __user *) regs->cp0_epc; 599 force_sig_info(SIGFPE, &info, current); 600 } 601 602 /* 603 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 604 */ 605 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 606 { 607 die_if_kernel("FP exception in kernel code", regs); 608 609 if (fcr31 & FPU_CSR_UNI_X) { 610 int sig; 611 612 /* 613 * Unimplemented operation exception. If we've got the full 614 * software emulator on-board, let's use it... 615 * 616 * Force FPU to dump state into task/thread context. We're 617 * moving a lot of data here for what is probably a single 618 * instruction, but the alternative is to pre-decode the FP 619 * register operands before invoking the emulator, which seems 620 * a bit extreme for what should be an infrequent event. 621 */ 622 /* Ensure 'resume' not overwrite saved fp context again. */ 623 lose_fpu(1); 624 625 /* Run the emulator */ 626 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); 627 628 /* 629 * We can't allow the emulated instruction to leave any of 630 * the cause bit set in $fcr31. 631 */ 632 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 633 634 /* Restore the hardware register state */ 635 own_fpu(1); /* Using the FPU again. */ 636 637 /* If something went wrong, signal */ 638 if (sig) 639 force_sig(sig, current); 640 641 return; 642 } 643 644 force_sig(SIGFPE, current); 645 } 646 647 asmlinkage void do_bp(struct pt_regs *regs) 648 { 649 unsigned int opcode, bcode; 650 siginfo_t info; 651 652 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 653 goto out_sigsegv; 654 655 /* 656 * There is the ancient bug in the MIPS assemblers that the break 657 * code starts left to bit 16 instead to bit 6 in the opcode. 658 * Gas is bug-compatible, but not always, grrr... 659 * We handle both cases with a simple heuristics. --macro 660 */ 661 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 662 if (bcode < (1 << 10)) 663 bcode <<= 10; 664 665 /* 666 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 667 * insns, even for break codes that indicate arithmetic failures. 668 * Weird ...) 669 * But should we continue the brokenness??? --macro 670 */ 671 switch (bcode) { 672 case BRK_OVERFLOW << 10: 673 case BRK_DIVZERO << 10: 674 die_if_kernel("Break instruction in kernel code", regs); 675 if (bcode == (BRK_DIVZERO << 10)) 676 info.si_code = FPE_INTDIV; 677 else 678 info.si_code = FPE_INTOVF; 679 info.si_signo = SIGFPE; 680 info.si_errno = 0; 681 info.si_addr = (void __user *) regs->cp0_epc; 682 force_sig_info(SIGFPE, &info, current); 683 break; 684 case BRK_BUG: 685 die("Kernel bug detected", regs); 686 break; 687 default: 688 die_if_kernel("Break instruction in kernel code", regs); 689 force_sig(SIGTRAP, current); 690 } 691 return; 692 693 out_sigsegv: 694 force_sig(SIGSEGV, current); 695 } 696 697 asmlinkage void do_tr(struct pt_regs *regs) 698 { 699 unsigned int opcode, tcode = 0; 700 siginfo_t info; 701 702 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 703 goto out_sigsegv; 704 705 /* Immediate versions don't provide a code. */ 706 if (!(opcode & OPCODE)) 707 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 708 709 /* 710 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 711 * insns, even for trap codes that indicate arithmetic failures. 712 * Weird ...) 713 * But should we continue the brokenness??? --macro 714 */ 715 switch (tcode) { 716 case BRK_OVERFLOW: 717 case BRK_DIVZERO: 718 die_if_kernel("Trap instruction in kernel code", regs); 719 if (tcode == BRK_DIVZERO) 720 info.si_code = FPE_INTDIV; 721 else 722 info.si_code = FPE_INTOVF; 723 info.si_signo = SIGFPE; 724 info.si_errno = 0; 725 info.si_addr = (void __user *) regs->cp0_epc; 726 force_sig_info(SIGFPE, &info, current); 727 break; 728 case BRK_BUG: 729 die("Kernel bug detected", regs); 730 break; 731 default: 732 die_if_kernel("Trap instruction in kernel code", regs); 733 force_sig(SIGTRAP, current); 734 } 735 return; 736 737 out_sigsegv: 738 force_sig(SIGSEGV, current); 739 } 740 741 asmlinkage void do_ri(struct pt_regs *regs) 742 { 743 die_if_kernel("Reserved instruction in kernel code", regs); 744 745 if (!cpu_has_llsc) 746 if (!simulate_llsc(regs)) 747 return; 748 749 if (!simulate_rdhwr(regs)) 750 return; 751 752 force_sig(SIGILL, current); 753 } 754 755 asmlinkage void do_cpu(struct pt_regs *regs) 756 { 757 unsigned int cpid; 758 759 die_if_kernel("do_cpu invoked from kernel context!", regs); 760 761 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 762 763 switch (cpid) { 764 case 0: 765 if (!cpu_has_llsc) 766 if (!simulate_llsc(regs)) 767 return; 768 769 if (!simulate_rdhwr(regs)) 770 return; 771 772 break; 773 774 case 1: 775 if (used_math()) /* Using the FPU again. */ 776 own_fpu(1); 777 else { /* First time FPU user. */ 778 init_fpu(); 779 set_used_math(); 780 } 781 782 if (!raw_cpu_has_fpu) { 783 int sig; 784 sig = fpu_emulator_cop1Handler(regs, 785 ¤t->thread.fpu, 0); 786 if (sig) 787 force_sig(sig, current); 788 #ifdef CONFIG_MIPS_MT_FPAFF 789 else { 790 /* 791 * MIPS MT processors may have fewer FPU contexts 792 * than CPU threads. If we've emulated more than 793 * some threshold number of instructions, force 794 * migration to a "CPU" that has FP support. 795 */ 796 if(mt_fpemul_threshold > 0 797 && ((current->thread.emulated_fp++ 798 > mt_fpemul_threshold))) { 799 /* 800 * If there's no FPU present, or if the 801 * application has already restricted 802 * the allowed set to exclude any CPUs 803 * with FPUs, we'll skip the procedure. 804 */ 805 if (cpus_intersects(current->cpus_allowed, 806 mt_fpu_cpumask)) { 807 cpumask_t tmask; 808 809 cpus_and(tmask, 810 current->thread.user_cpus_allowed, 811 mt_fpu_cpumask); 812 set_cpus_allowed(current, tmask); 813 current->thread.mflags |= MF_FPUBOUND; 814 } 815 } 816 } 817 #endif /* CONFIG_MIPS_MT_FPAFF */ 818 } 819 820 return; 821 822 case 2: 823 case 3: 824 break; 825 } 826 827 force_sig(SIGILL, current); 828 } 829 830 asmlinkage void do_mdmx(struct pt_regs *regs) 831 { 832 force_sig(SIGILL, current); 833 } 834 835 asmlinkage void do_watch(struct pt_regs *regs) 836 { 837 /* 838 * We use the watch exception where available to detect stack 839 * overflows. 840 */ 841 dump_tlb_all(); 842 show_regs(regs); 843 panic("Caught WATCH exception - probably caused by stack overflow."); 844 } 845 846 asmlinkage void do_mcheck(struct pt_regs *regs) 847 { 848 const int field = 2 * sizeof(unsigned long); 849 int multi_match = regs->cp0_status & ST0_TS; 850 851 show_regs(regs); 852 853 if (multi_match) { 854 printk("Index : %0x\n", read_c0_index()); 855 printk("Pagemask: %0x\n", read_c0_pagemask()); 856 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 857 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 858 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 859 printk("\n"); 860 dump_tlb_all(); 861 } 862 863 show_code((unsigned int *) regs->cp0_epc); 864 865 /* 866 * Some chips may have other causes of machine check (e.g. SB1 867 * graduation timer) 868 */ 869 panic("Caught Machine Check exception - %scaused by multiple " 870 "matching entries in the TLB.", 871 (multi_match) ? "" : "not "); 872 } 873 874 asmlinkage void do_mt(struct pt_regs *regs) 875 { 876 int subcode; 877 878 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 879 >> VPECONTROL_EXCPT_SHIFT; 880 switch (subcode) { 881 case 0: 882 printk(KERN_DEBUG "Thread Underflow\n"); 883 break; 884 case 1: 885 printk(KERN_DEBUG "Thread Overflow\n"); 886 break; 887 case 2: 888 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 889 break; 890 case 3: 891 printk(KERN_DEBUG "Gating Storage Exception\n"); 892 break; 893 case 4: 894 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 895 break; 896 case 5: 897 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 898 break; 899 default: 900 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 901 subcode); 902 break; 903 } 904 die_if_kernel("MIPS MT Thread exception in kernel", regs); 905 906 force_sig(SIGILL, current); 907 } 908 909 910 asmlinkage void do_dsp(struct pt_regs *regs) 911 { 912 if (cpu_has_dsp) 913 panic("Unexpected DSP exception\n"); 914 915 force_sig(SIGILL, current); 916 } 917 918 asmlinkage void do_reserved(struct pt_regs *regs) 919 { 920 /* 921 * Game over - no way to handle this if it ever occurs. Most probably 922 * caused by a new unknown cpu type or after another deadly 923 * hard/software error. 924 */ 925 show_regs(regs); 926 panic("Caught reserved exception %ld - should not happen.", 927 (regs->cp0_cause & 0x7f) >> 2); 928 } 929 930 /* 931 * Some MIPS CPUs can enable/disable for cache parity detection, but do 932 * it different ways. 933 */ 934 static inline void parity_protection_init(void) 935 { 936 switch (current_cpu_data.cputype) { 937 case CPU_24K: 938 case CPU_34K: 939 case CPU_5KC: 940 write_c0_ecc(0x80000000); 941 back_to_back_c0_hazard(); 942 /* Set the PE bit (bit 31) in the c0_errctl register. */ 943 printk(KERN_INFO "Cache parity protection %sabled\n", 944 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 945 break; 946 case CPU_20KC: 947 case CPU_25KF: 948 /* Clear the DE bit (bit 16) in the c0_status register. */ 949 printk(KERN_INFO "Enable cache parity protection for " 950 "MIPS 20KC/25KF CPUs.\n"); 951 clear_c0_status(ST0_DE); 952 break; 953 default: 954 break; 955 } 956 } 957 958 asmlinkage void cache_parity_error(void) 959 { 960 const int field = 2 * sizeof(unsigned long); 961 unsigned int reg_val; 962 963 /* For the moment, report the problem and hang. */ 964 printk("Cache error exception:\n"); 965 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 966 reg_val = read_c0_cacheerr(); 967 printk("c0_cacheerr == %08x\n", reg_val); 968 969 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 970 reg_val & (1<<30) ? "secondary" : "primary", 971 reg_val & (1<<31) ? "data" : "insn"); 972 printk("Error bits: %s%s%s%s%s%s%s\n", 973 reg_val & (1<<29) ? "ED " : "", 974 reg_val & (1<<28) ? "ET " : "", 975 reg_val & (1<<26) ? "EE " : "", 976 reg_val & (1<<25) ? "EB " : "", 977 reg_val & (1<<24) ? "EI " : "", 978 reg_val & (1<<23) ? "E1 " : "", 979 reg_val & (1<<22) ? "E0 " : ""); 980 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 981 982 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 983 if (reg_val & (1<<22)) 984 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 985 986 if (reg_val & (1<<23)) 987 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 988 #endif 989 990 panic("Can't handle the cache error!"); 991 } 992 993 /* 994 * SDBBP EJTAG debug exception handler. 995 * We skip the instruction and return to the next instruction. 996 */ 997 void ejtag_exception_handler(struct pt_regs *regs) 998 { 999 const int field = 2 * sizeof(unsigned long); 1000 unsigned long depc, old_epc; 1001 unsigned int debug; 1002 1003 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1004 depc = read_c0_depc(); 1005 debug = read_c0_debug(); 1006 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1007 if (debug & 0x80000000) { 1008 /* 1009 * In branch delay slot. 1010 * We cheat a little bit here and use EPC to calculate the 1011 * debug return address (DEPC). EPC is restored after the 1012 * calculation. 1013 */ 1014 old_epc = regs->cp0_epc; 1015 regs->cp0_epc = depc; 1016 __compute_return_epc(regs); 1017 depc = regs->cp0_epc; 1018 regs->cp0_epc = old_epc; 1019 } else 1020 depc += 4; 1021 write_c0_depc(depc); 1022 1023 #if 0 1024 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1025 write_c0_debug(debug | 0x100); 1026 #endif 1027 } 1028 1029 /* 1030 * NMI exception handler. 1031 */ 1032 void nmi_exception_handler(struct pt_regs *regs) 1033 { 1034 #ifdef CONFIG_MIPS_MT_SMTC 1035 unsigned long dvpret = dvpe(); 1036 bust_spinlocks(1); 1037 printk("NMI taken!!!!\n"); 1038 mips_mt_regdump(dvpret); 1039 #else 1040 bust_spinlocks(1); 1041 printk("NMI taken!!!!\n"); 1042 #endif /* CONFIG_MIPS_MT_SMTC */ 1043 die("NMI", regs); 1044 while(1) ; 1045 } 1046 1047 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1048 1049 unsigned long ebase; 1050 unsigned long exception_handlers[32]; 1051 unsigned long vi_handlers[64]; 1052 1053 /* 1054 * As a side effect of the way this is implemented we're limited 1055 * to interrupt handlers in the address range from 1056 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1057 */ 1058 void *set_except_vector(int n, void *addr) 1059 { 1060 unsigned long handler = (unsigned long) addr; 1061 unsigned long old_handler = exception_handlers[n]; 1062 1063 exception_handlers[n] = handler; 1064 if (n == 0 && cpu_has_divec) { 1065 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1066 (0x03ffffff & (handler >> 2)); 1067 flush_icache_range(ebase + 0x200, ebase + 0x204); 1068 } 1069 return (void *)old_handler; 1070 } 1071 1072 #ifdef CONFIG_CPU_MIPSR2_SRS 1073 /* 1074 * MIPSR2 shadow register set allocation 1075 * FIXME: SMP... 1076 */ 1077 1078 static struct shadow_registers { 1079 /* 1080 * Number of shadow register sets supported 1081 */ 1082 unsigned long sr_supported; 1083 /* 1084 * Bitmap of allocated shadow registers 1085 */ 1086 unsigned long sr_allocated; 1087 } shadow_registers; 1088 1089 static void mips_srs_init(void) 1090 { 1091 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1092 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1093 shadow_registers.sr_supported); 1094 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1095 } 1096 1097 int mips_srs_max(void) 1098 { 1099 return shadow_registers.sr_supported; 1100 } 1101 1102 int mips_srs_alloc(void) 1103 { 1104 struct shadow_registers *sr = &shadow_registers; 1105 int set; 1106 1107 again: 1108 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1109 if (set >= sr->sr_supported) 1110 return -1; 1111 1112 if (test_and_set_bit(set, &sr->sr_allocated)) 1113 goto again; 1114 1115 return set; 1116 } 1117 1118 void mips_srs_free(int set) 1119 { 1120 struct shadow_registers *sr = &shadow_registers; 1121 1122 clear_bit(set, &sr->sr_allocated); 1123 } 1124 1125 static asmlinkage void do_default_vi(void) 1126 { 1127 show_regs(get_irq_regs()); 1128 panic("Caught unexpected vectored interrupt."); 1129 } 1130 1131 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1132 { 1133 unsigned long handler; 1134 unsigned long old_handler = vi_handlers[n]; 1135 u32 *w; 1136 unsigned char *b; 1137 1138 if (!cpu_has_veic && !cpu_has_vint) 1139 BUG(); 1140 1141 if (addr == NULL) { 1142 handler = (unsigned long) do_default_vi; 1143 srs = 0; 1144 } else 1145 handler = (unsigned long) addr; 1146 vi_handlers[n] = (unsigned long) addr; 1147 1148 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1149 1150 if (srs >= mips_srs_max()) 1151 panic("Shadow register set %d not supported", srs); 1152 1153 if (cpu_has_veic) { 1154 if (board_bind_eic_interrupt) 1155 board_bind_eic_interrupt (n, srs); 1156 } else if (cpu_has_vint) { 1157 /* SRSMap is only defined if shadow sets are implemented */ 1158 if (mips_srs_max() > 1) 1159 change_c0_srsmap (0xf << n*4, srs << n*4); 1160 } 1161 1162 if (srs == 0) { 1163 /* 1164 * If no shadow set is selected then use the default handler 1165 * that does normal register saving and a standard interrupt exit 1166 */ 1167 1168 extern char except_vec_vi, except_vec_vi_lui; 1169 extern char except_vec_vi_ori, except_vec_vi_end; 1170 #ifdef CONFIG_MIPS_MT_SMTC 1171 /* 1172 * We need to provide the SMTC vectored interrupt handler 1173 * not only with the address of the handler, but with the 1174 * Status.IM bit to be masked before going there. 1175 */ 1176 extern char except_vec_vi_mori; 1177 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1178 #endif /* CONFIG_MIPS_MT_SMTC */ 1179 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1180 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1181 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1182 1183 if (handler_len > VECTORSPACING) { 1184 /* 1185 * Sigh... panicing won't help as the console 1186 * is probably not configured :( 1187 */ 1188 panic ("VECTORSPACING too small"); 1189 } 1190 1191 memcpy (b, &except_vec_vi, handler_len); 1192 #ifdef CONFIG_MIPS_MT_SMTC 1193 if (n > 7) 1194 printk("Vector index %d exceeds SMTC maximum\n", n); 1195 w = (u32 *)(b + mori_offset); 1196 *w = (*w & 0xffff0000) | (0x100 << n); 1197 #endif /* CONFIG_MIPS_MT_SMTC */ 1198 w = (u32 *)(b + lui_offset); 1199 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1200 w = (u32 *)(b + ori_offset); 1201 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1202 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1203 } 1204 else { 1205 /* 1206 * In other cases jump directly to the interrupt handler 1207 * 1208 * It is the handlers responsibility to save registers if required 1209 * (eg hi/lo) and return from the exception using "eret" 1210 */ 1211 w = (u32 *)b; 1212 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1213 *w = 0; 1214 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1215 } 1216 1217 return (void *)old_handler; 1218 } 1219 1220 void *set_vi_handler(int n, vi_handler_t addr) 1221 { 1222 return set_vi_srs_handler(n, addr, 0); 1223 } 1224 1225 #else 1226 1227 static inline void mips_srs_init(void) 1228 { 1229 } 1230 1231 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1232 1233 /* 1234 * This is used by native signal handling 1235 */ 1236 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1237 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1238 1239 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1240 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1241 1242 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1243 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1244 1245 #ifdef CONFIG_SMP 1246 static int smp_save_fp_context(struct sigcontext __user *sc) 1247 { 1248 return raw_cpu_has_fpu 1249 ? _save_fp_context(sc) 1250 : fpu_emulator_save_context(sc); 1251 } 1252 1253 static int smp_restore_fp_context(struct sigcontext __user *sc) 1254 { 1255 return raw_cpu_has_fpu 1256 ? _restore_fp_context(sc) 1257 : fpu_emulator_restore_context(sc); 1258 } 1259 #endif 1260 1261 static inline void signal_init(void) 1262 { 1263 #ifdef CONFIG_SMP 1264 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1265 save_fp_context = smp_save_fp_context; 1266 restore_fp_context = smp_restore_fp_context; 1267 #else 1268 if (cpu_has_fpu) { 1269 save_fp_context = _save_fp_context; 1270 restore_fp_context = _restore_fp_context; 1271 } else { 1272 save_fp_context = fpu_emulator_save_context; 1273 restore_fp_context = fpu_emulator_restore_context; 1274 } 1275 #endif 1276 } 1277 1278 #ifdef CONFIG_MIPS32_COMPAT 1279 1280 /* 1281 * This is used by 32-bit signal stuff on the 64-bit kernel 1282 */ 1283 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1284 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1285 1286 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1287 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1288 1289 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1290 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1291 1292 static inline void signal32_init(void) 1293 { 1294 if (cpu_has_fpu) { 1295 save_fp_context32 = _save_fp_context32; 1296 restore_fp_context32 = _restore_fp_context32; 1297 } else { 1298 save_fp_context32 = fpu_emulator_save_context32; 1299 restore_fp_context32 = fpu_emulator_restore_context32; 1300 } 1301 } 1302 #endif 1303 1304 extern void cpu_cache_init(void); 1305 extern void tlb_init(void); 1306 extern void flush_tlb_handlers(void); 1307 1308 void __init per_cpu_trap_init(void) 1309 { 1310 unsigned int cpu = smp_processor_id(); 1311 unsigned int status_set = ST0_CU0; 1312 #ifdef CONFIG_MIPS_MT_SMTC 1313 int secondaryTC = 0; 1314 int bootTC = (cpu == 0); 1315 1316 /* 1317 * Only do per_cpu_trap_init() for first TC of Each VPE. 1318 * Note that this hack assumes that the SMTC init code 1319 * assigns TCs consecutively and in ascending order. 1320 */ 1321 1322 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1323 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1324 secondaryTC = 1; 1325 #endif /* CONFIG_MIPS_MT_SMTC */ 1326 1327 /* 1328 * Disable coprocessors and select 32-bit or 64-bit addressing 1329 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1330 * flag that some firmware may have left set and the TS bit (for 1331 * IP27). Set XX for ISA IV code to work. 1332 */ 1333 #ifdef CONFIG_64BIT 1334 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1335 #endif 1336 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1337 status_set |= ST0_XX; 1338 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1339 status_set); 1340 1341 if (cpu_has_dsp) 1342 set_c0_status(ST0_MX); 1343 1344 #ifdef CONFIG_CPU_MIPSR2 1345 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ 1346 #endif 1347 1348 #ifdef CONFIG_MIPS_MT_SMTC 1349 if (!secondaryTC) { 1350 #endif /* CONFIG_MIPS_MT_SMTC */ 1351 1352 /* 1353 * Interrupt handling. 1354 */ 1355 if (cpu_has_veic || cpu_has_vint) { 1356 write_c0_ebase (ebase); 1357 /* Setting vector spacing enables EI/VI mode */ 1358 change_c0_intctl (0x3e0, VECTORSPACING); 1359 } 1360 if (cpu_has_divec) { 1361 if (cpu_has_mipsmt) { 1362 unsigned int vpflags = dvpe(); 1363 set_c0_cause(CAUSEF_IV); 1364 evpe(vpflags); 1365 } else 1366 set_c0_cause(CAUSEF_IV); 1367 } 1368 #ifdef CONFIG_MIPS_MT_SMTC 1369 } 1370 #endif /* CONFIG_MIPS_MT_SMTC */ 1371 1372 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1373 TLBMISS_HANDLER_SETUP(); 1374 1375 atomic_inc(&init_mm.mm_count); 1376 current->active_mm = &init_mm; 1377 BUG_ON(current->mm); 1378 enter_lazy_tlb(&init_mm, current); 1379 1380 #ifdef CONFIG_MIPS_MT_SMTC 1381 if (bootTC) { 1382 #endif /* CONFIG_MIPS_MT_SMTC */ 1383 cpu_cache_init(); 1384 tlb_init(); 1385 #ifdef CONFIG_MIPS_MT_SMTC 1386 } 1387 #endif /* CONFIG_MIPS_MT_SMTC */ 1388 } 1389 1390 /* Install CPU exception handler */ 1391 void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1392 { 1393 memcpy((void *)(ebase + offset), addr, size); 1394 flush_icache_range(ebase + offset, ebase + offset + size); 1395 } 1396 1397 /* Install uncached CPU exception handler */ 1398 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1399 { 1400 #ifdef CONFIG_32BIT 1401 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1402 #endif 1403 #ifdef CONFIG_64BIT 1404 unsigned long uncached_ebase = TO_UNCAC(ebase); 1405 #endif 1406 1407 memcpy((void *)(uncached_ebase + offset), addr, size); 1408 } 1409 1410 static int __initdata rdhwr_noopt; 1411 static int __init set_rdhwr_noopt(char *str) 1412 { 1413 rdhwr_noopt = 1; 1414 return 1; 1415 } 1416 1417 __setup("rdhwr_noopt", set_rdhwr_noopt); 1418 1419 void __init trap_init(void) 1420 { 1421 extern char except_vec3_generic, except_vec3_r4000; 1422 extern char except_vec4; 1423 unsigned long i; 1424 1425 if (cpu_has_veic || cpu_has_vint) 1426 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1427 else 1428 ebase = CAC_BASE; 1429 1430 mips_srs_init(); 1431 1432 per_cpu_trap_init(); 1433 1434 /* 1435 * Copy the generic exception handlers to their final destination. 1436 * This will be overriden later as suitable for a particular 1437 * configuration. 1438 */ 1439 set_handler(0x180, &except_vec3_generic, 0x80); 1440 1441 /* 1442 * Setup default vectors 1443 */ 1444 for (i = 0; i <= 31; i++) 1445 set_except_vector(i, handle_reserved); 1446 1447 /* 1448 * Copy the EJTAG debug exception vector handler code to it's final 1449 * destination. 1450 */ 1451 if (cpu_has_ejtag && board_ejtag_handler_setup) 1452 board_ejtag_handler_setup (); 1453 1454 /* 1455 * Only some CPUs have the watch exceptions. 1456 */ 1457 if (cpu_has_watch) 1458 set_except_vector(23, handle_watch); 1459 1460 /* 1461 * Initialise interrupt handlers 1462 */ 1463 if (cpu_has_veic || cpu_has_vint) { 1464 int nvec = cpu_has_veic ? 64 : 8; 1465 for (i = 0; i < nvec; i++) 1466 set_vi_handler(i, NULL); 1467 } 1468 else if (cpu_has_divec) 1469 set_handler(0x200, &except_vec4, 0x8); 1470 1471 /* 1472 * Some CPUs can enable/disable for cache parity detection, but does 1473 * it different ways. 1474 */ 1475 parity_protection_init(); 1476 1477 /* 1478 * The Data Bus Errors / Instruction Bus Errors are signaled 1479 * by external hardware. Therefore these two exceptions 1480 * may have board specific handlers. 1481 */ 1482 if (board_be_init) 1483 board_be_init(); 1484 1485 set_except_vector(0, handle_int); 1486 set_except_vector(1, handle_tlbm); 1487 set_except_vector(2, handle_tlbl); 1488 set_except_vector(3, handle_tlbs); 1489 1490 set_except_vector(4, handle_adel); 1491 set_except_vector(5, handle_ades); 1492 1493 set_except_vector(6, handle_ibe); 1494 set_except_vector(7, handle_dbe); 1495 1496 set_except_vector(8, handle_sys); 1497 set_except_vector(9, handle_bp); 1498 set_except_vector(10, rdhwr_noopt ? handle_ri : 1499 (cpu_has_vtag_icache ? 1500 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1501 set_except_vector(11, handle_cpu); 1502 set_except_vector(12, handle_ov); 1503 set_except_vector(13, handle_tr); 1504 1505 if (current_cpu_data.cputype == CPU_R6000 || 1506 current_cpu_data.cputype == CPU_R6000A) { 1507 /* 1508 * The R6000 is the only R-series CPU that features a machine 1509 * check exception (similar to the R4000 cache error) and 1510 * unaligned ldc1/sdc1 exception. The handlers have not been 1511 * written yet. Well, anyway there is no R6000 machine on the 1512 * current list of targets for Linux/MIPS. 1513 * (Duh, crap, there is someone with a triple R6k machine) 1514 */ 1515 //set_except_vector(14, handle_mc); 1516 //set_except_vector(15, handle_ndc); 1517 } 1518 1519 1520 if (board_nmi_handler_setup) 1521 board_nmi_handler_setup(); 1522 1523 if (cpu_has_fpu && !cpu_has_nofpuex) 1524 set_except_vector(15, handle_fpe); 1525 1526 set_except_vector(22, handle_mdmx); 1527 1528 if (cpu_has_mcheck) 1529 set_except_vector(24, handle_mcheck); 1530 1531 if (cpu_has_mipsmt) 1532 set_except_vector(25, handle_mt); 1533 1534 if (cpu_has_dsp) 1535 set_except_vector(26, handle_dsp); 1536 1537 if (cpu_has_vce) 1538 /* Special exception: R4[04]00 uses also the divec space. */ 1539 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1540 else if (cpu_has_4kex) 1541 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1542 else 1543 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1544 1545 signal_init(); 1546 #ifdef CONFIG_MIPS32_COMPAT 1547 signal32_init(); 1548 #endif 1549 1550 flush_icache_range(ebase, ebase + 0x400); 1551 flush_tlb_handlers(); 1552 } 1553