1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 #include <linux/kgdb.h> 27 #include <linux/kdebug.h> 28 29 #include <asm/bootinfo.h> 30 #include <asm/branch.h> 31 #include <asm/break.h> 32 #include <asm/cpu.h> 33 #include <asm/dsp.h> 34 #include <asm/fpu.h> 35 #include <asm/fpu_emulator.h> 36 #include <asm/mipsregs.h> 37 #include <asm/mipsmtregs.h> 38 #include <asm/module.h> 39 #include <asm/pgtable.h> 40 #include <asm/ptrace.h> 41 #include <asm/sections.h> 42 #include <asm/system.h> 43 #include <asm/tlbdebug.h> 44 #include <asm/traps.h> 45 #include <asm/uaccess.h> 46 #include <asm/watch.h> 47 #include <asm/mmu_context.h> 48 #include <asm/types.h> 49 #include <asm/stacktrace.h> 50 #include <asm/irq.h> 51 52 extern void check_wait(void); 53 extern asmlinkage void r4k_wait(void); 54 extern asmlinkage void rollback_handle_int(void); 55 extern asmlinkage void handle_int(void); 56 extern asmlinkage void handle_tlbm(void); 57 extern asmlinkage void handle_tlbl(void); 58 extern asmlinkage void handle_tlbs(void); 59 extern asmlinkage void handle_adel(void); 60 extern asmlinkage void handle_ades(void); 61 extern asmlinkage void handle_ibe(void); 62 extern asmlinkage void handle_dbe(void); 63 extern asmlinkage void handle_sys(void); 64 extern asmlinkage void handle_bp(void); 65 extern asmlinkage void handle_ri(void); 66 extern asmlinkage void handle_ri_rdhwr_vivt(void); 67 extern asmlinkage void handle_ri_rdhwr(void); 68 extern asmlinkage void handle_cpu(void); 69 extern asmlinkage void handle_ov(void); 70 extern asmlinkage void handle_tr(void); 71 extern asmlinkage void handle_fpe(void); 72 extern asmlinkage void handle_mdmx(void); 73 extern asmlinkage void handle_watch(void); 74 extern asmlinkage void handle_mt(void); 75 extern asmlinkage void handle_dsp(void); 76 extern asmlinkage void handle_mcheck(void); 77 extern asmlinkage void handle_reserved(void); 78 79 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 80 struct mips_fpu_struct *ctx, int has_fpu); 81 82 #ifdef CONFIG_CPU_CAVIUM_OCTEON 83 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); 84 #endif 85 86 void (*board_be_init)(void); 87 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 88 void (*board_nmi_handler_setup)(void); 89 void (*board_ejtag_handler_setup)(void); 90 void (*board_bind_eic_interrupt)(int irq, int regset); 91 92 93 static void show_raw_backtrace(unsigned long reg29) 94 { 95 unsigned long *sp = (unsigned long *)(reg29 & ~3); 96 unsigned long addr; 97 98 printk("Call Trace:"); 99 #ifdef CONFIG_KALLSYMS 100 printk("\n"); 101 #endif 102 while (!kstack_end(sp)) { 103 unsigned long __user *p = 104 (unsigned long __user *)(unsigned long)sp++; 105 if (__get_user(addr, p)) { 106 printk(" (Bad stack address)"); 107 break; 108 } 109 if (__kernel_text_address(addr)) 110 print_ip_sym(addr); 111 } 112 printk("\n"); 113 } 114 115 #ifdef CONFIG_KALLSYMS 116 int raw_show_trace; 117 static int __init set_raw_show_trace(char *str) 118 { 119 raw_show_trace = 1; 120 return 1; 121 } 122 __setup("raw_show_trace", set_raw_show_trace); 123 #endif 124 125 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 126 { 127 unsigned long sp = regs->regs[29]; 128 unsigned long ra = regs->regs[31]; 129 unsigned long pc = regs->cp0_epc; 130 131 if (raw_show_trace || !__kernel_text_address(pc)) { 132 show_raw_backtrace(sp); 133 return; 134 } 135 printk("Call Trace:\n"); 136 do { 137 print_ip_sym(pc); 138 pc = unwind_stack(task, &sp, pc, &ra); 139 } while (pc); 140 printk("\n"); 141 } 142 143 /* 144 * This routine abuses get_user()/put_user() to reference pointers 145 * with at least a bit of error checking ... 146 */ 147 static void show_stacktrace(struct task_struct *task, 148 const struct pt_regs *regs) 149 { 150 const int field = 2 * sizeof(unsigned long); 151 long stackdata; 152 int i; 153 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 154 155 printk("Stack :"); 156 i = 0; 157 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 158 if (i && ((i % (64 / field)) == 0)) 159 printk("\n "); 160 if (i > 39) { 161 printk(" ..."); 162 break; 163 } 164 165 if (__get_user(stackdata, sp++)) { 166 printk(" (Bad stack address)"); 167 break; 168 } 169 170 printk(" %0*lx", field, stackdata); 171 i++; 172 } 173 printk("\n"); 174 show_backtrace(task, regs); 175 } 176 177 void show_stack(struct task_struct *task, unsigned long *sp) 178 { 179 struct pt_regs regs; 180 if (sp) { 181 regs.regs[29] = (unsigned long)sp; 182 regs.regs[31] = 0; 183 regs.cp0_epc = 0; 184 } else { 185 if (task && task != current) { 186 regs.regs[29] = task->thread.reg29; 187 regs.regs[31] = 0; 188 regs.cp0_epc = task->thread.reg31; 189 } else { 190 prepare_frametrace(®s); 191 } 192 } 193 show_stacktrace(task, ®s); 194 } 195 196 /* 197 * The architecture-independent dump_stack generator 198 */ 199 void dump_stack(void) 200 { 201 struct pt_regs regs; 202 203 prepare_frametrace(®s); 204 show_backtrace(current, ®s); 205 } 206 207 EXPORT_SYMBOL(dump_stack); 208 209 static void show_code(unsigned int __user *pc) 210 { 211 long i; 212 unsigned short __user *pc16 = NULL; 213 214 printk("\nCode:"); 215 216 if ((unsigned long)pc & 1) 217 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 218 for(i = -3 ; i < 6 ; i++) { 219 unsigned int insn; 220 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 221 printk(" (Bad address in epc)\n"); 222 break; 223 } 224 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 225 } 226 } 227 228 static void __show_regs(const struct pt_regs *regs) 229 { 230 const int field = 2 * sizeof(unsigned long); 231 unsigned int cause = regs->cp0_cause; 232 int i; 233 234 printk("Cpu %d\n", smp_processor_id()); 235 236 /* 237 * Saved main processor registers 238 */ 239 for (i = 0; i < 32; ) { 240 if ((i % 4) == 0) 241 printk("$%2d :", i); 242 if (i == 0) 243 printk(" %0*lx", field, 0UL); 244 else if (i == 26 || i == 27) 245 printk(" %*s", field, ""); 246 else 247 printk(" %0*lx", field, regs->regs[i]); 248 249 i++; 250 if ((i % 4) == 0) 251 printk("\n"); 252 } 253 254 #ifdef CONFIG_CPU_HAS_SMARTMIPS 255 printk("Acx : %0*lx\n", field, regs->acx); 256 #endif 257 printk("Hi : %0*lx\n", field, regs->hi); 258 printk("Lo : %0*lx\n", field, regs->lo); 259 260 /* 261 * Saved cp0 registers 262 */ 263 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 264 (void *) regs->cp0_epc); 265 printk(" %s\n", print_tainted()); 266 printk("ra : %0*lx %pS\n", field, regs->regs[31], 267 (void *) regs->regs[31]); 268 269 printk("Status: %08x ", (uint32_t) regs->cp0_status); 270 271 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 272 if (regs->cp0_status & ST0_KUO) 273 printk("KUo "); 274 if (regs->cp0_status & ST0_IEO) 275 printk("IEo "); 276 if (regs->cp0_status & ST0_KUP) 277 printk("KUp "); 278 if (regs->cp0_status & ST0_IEP) 279 printk("IEp "); 280 if (regs->cp0_status & ST0_KUC) 281 printk("KUc "); 282 if (regs->cp0_status & ST0_IEC) 283 printk("IEc "); 284 } else { 285 if (regs->cp0_status & ST0_KX) 286 printk("KX "); 287 if (regs->cp0_status & ST0_SX) 288 printk("SX "); 289 if (regs->cp0_status & ST0_UX) 290 printk("UX "); 291 switch (regs->cp0_status & ST0_KSU) { 292 case KSU_USER: 293 printk("USER "); 294 break; 295 case KSU_SUPERVISOR: 296 printk("SUPERVISOR "); 297 break; 298 case KSU_KERNEL: 299 printk("KERNEL "); 300 break; 301 default: 302 printk("BAD_MODE "); 303 break; 304 } 305 if (regs->cp0_status & ST0_ERL) 306 printk("ERL "); 307 if (regs->cp0_status & ST0_EXL) 308 printk("EXL "); 309 if (regs->cp0_status & ST0_IE) 310 printk("IE "); 311 } 312 printk("\n"); 313 314 printk("Cause : %08x\n", cause); 315 316 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 317 if (1 <= cause && cause <= 5) 318 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 319 320 printk("PrId : %08x (%s)\n", read_c0_prid(), 321 cpu_name_string()); 322 } 323 324 /* 325 * FIXME: really the generic show_regs should take a const pointer argument. 326 */ 327 void show_regs(struct pt_regs *regs) 328 { 329 __show_regs((struct pt_regs *)regs); 330 } 331 332 void show_registers(const struct pt_regs *regs) 333 { 334 const int field = 2 * sizeof(unsigned long); 335 336 __show_regs(regs); 337 print_modules(); 338 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 339 current->comm, current->pid, current_thread_info(), current, 340 field, current_thread_info()->tp_value); 341 if (cpu_has_userlocal) { 342 unsigned long tls; 343 344 tls = read_c0_userlocal(); 345 if (tls != current_thread_info()->tp_value) 346 printk("*HwTLS: %0*lx\n", field, tls); 347 } 348 349 show_stacktrace(current, regs); 350 show_code((unsigned int __user *) regs->cp0_epc); 351 printk("\n"); 352 } 353 354 static DEFINE_SPINLOCK(die_lock); 355 356 void __noreturn die(const char * str, const struct pt_regs * regs) 357 { 358 static int die_counter; 359 #ifdef CONFIG_MIPS_MT_SMTC 360 unsigned long dvpret = dvpe(); 361 #endif /* CONFIG_MIPS_MT_SMTC */ 362 363 console_verbose(); 364 spin_lock_irq(&die_lock); 365 bust_spinlocks(1); 366 #ifdef CONFIG_MIPS_MT_SMTC 367 mips_mt_regdump(dvpret); 368 #endif /* CONFIG_MIPS_MT_SMTC */ 369 printk("%s[#%d]:\n", str, ++die_counter); 370 show_registers(regs); 371 add_taint(TAINT_DIE); 372 spin_unlock_irq(&die_lock); 373 374 if (in_interrupt()) 375 panic("Fatal exception in interrupt"); 376 377 if (panic_on_oops) { 378 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 379 ssleep(5); 380 panic("Fatal exception"); 381 } 382 383 do_exit(SIGSEGV); 384 } 385 386 extern struct exception_table_entry __start___dbe_table[]; 387 extern struct exception_table_entry __stop___dbe_table[]; 388 389 __asm__( 390 " .section __dbe_table, \"a\"\n" 391 " .previous \n"); 392 393 /* Given an address, look for it in the exception tables. */ 394 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 395 { 396 const struct exception_table_entry *e; 397 398 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 399 if (!e) 400 e = search_module_dbetables(addr); 401 return e; 402 } 403 404 asmlinkage void do_be(struct pt_regs *regs) 405 { 406 const int field = 2 * sizeof(unsigned long); 407 const struct exception_table_entry *fixup = NULL; 408 int data = regs->cp0_cause & 4; 409 int action = MIPS_BE_FATAL; 410 411 /* XXX For now. Fixme, this searches the wrong table ... */ 412 if (data && !user_mode(regs)) 413 fixup = search_dbe_tables(exception_epc(regs)); 414 415 if (fixup) 416 action = MIPS_BE_FIXUP; 417 418 if (board_be_handler) 419 action = board_be_handler(regs, fixup != NULL); 420 421 switch (action) { 422 case MIPS_BE_DISCARD: 423 return; 424 case MIPS_BE_FIXUP: 425 if (fixup) { 426 regs->cp0_epc = fixup->nextinsn; 427 return; 428 } 429 break; 430 default: 431 break; 432 } 433 434 /* 435 * Assume it would be too dangerous to continue ... 436 */ 437 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 438 data ? "Data" : "Instruction", 439 field, regs->cp0_epc, field, regs->regs[31]); 440 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) 441 == NOTIFY_STOP) 442 return; 443 444 die_if_kernel("Oops", regs); 445 force_sig(SIGBUS, current); 446 } 447 448 /* 449 * ll/sc, rdhwr, sync emulation 450 */ 451 452 #define OPCODE 0xfc000000 453 #define BASE 0x03e00000 454 #define RT 0x001f0000 455 #define OFFSET 0x0000ffff 456 #define LL 0xc0000000 457 #define SC 0xe0000000 458 #define SPEC0 0x00000000 459 #define SPEC3 0x7c000000 460 #define RD 0x0000f800 461 #define FUNC 0x0000003f 462 #define SYNC 0x0000000f 463 #define RDHWR 0x0000003b 464 465 /* 466 * The ll_bit is cleared by r*_switch.S 467 */ 468 469 unsigned long ll_bit; 470 471 static struct task_struct *ll_task = NULL; 472 473 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 474 { 475 unsigned long value, __user *vaddr; 476 long offset; 477 478 /* 479 * analyse the ll instruction that just caused a ri exception 480 * and put the referenced address to addr. 481 */ 482 483 /* sign extend offset */ 484 offset = opcode & OFFSET; 485 offset <<= 16; 486 offset >>= 16; 487 488 vaddr = (unsigned long __user *) 489 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 490 491 if ((unsigned long)vaddr & 3) 492 return SIGBUS; 493 if (get_user(value, vaddr)) 494 return SIGSEGV; 495 496 preempt_disable(); 497 498 if (ll_task == NULL || ll_task == current) { 499 ll_bit = 1; 500 } else { 501 ll_bit = 0; 502 } 503 ll_task = current; 504 505 preempt_enable(); 506 507 regs->regs[(opcode & RT) >> 16] = value; 508 509 return 0; 510 } 511 512 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 513 { 514 unsigned long __user *vaddr; 515 unsigned long reg; 516 long offset; 517 518 /* 519 * analyse the sc instruction that just caused a ri exception 520 * and put the referenced address to addr. 521 */ 522 523 /* sign extend offset */ 524 offset = opcode & OFFSET; 525 offset <<= 16; 526 offset >>= 16; 527 528 vaddr = (unsigned long __user *) 529 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 530 reg = (opcode & RT) >> 16; 531 532 if ((unsigned long)vaddr & 3) 533 return SIGBUS; 534 535 preempt_disable(); 536 537 if (ll_bit == 0 || ll_task != current) { 538 regs->regs[reg] = 0; 539 preempt_enable(); 540 return 0; 541 } 542 543 preempt_enable(); 544 545 if (put_user(regs->regs[reg], vaddr)) 546 return SIGSEGV; 547 548 regs->regs[reg] = 1; 549 550 return 0; 551 } 552 553 /* 554 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 555 * opcodes are supposed to result in coprocessor unusable exceptions if 556 * executed on ll/sc-less processors. That's the theory. In practice a 557 * few processors such as NEC's VR4100 throw reserved instruction exceptions 558 * instead, so we're doing the emulation thing in both exception handlers. 559 */ 560 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 561 { 562 if ((opcode & OPCODE) == LL) 563 return simulate_ll(regs, opcode); 564 if ((opcode & OPCODE) == SC) 565 return simulate_sc(regs, opcode); 566 567 return -1; /* Must be something else ... */ 568 } 569 570 /* 571 * Simulate trapping 'rdhwr' instructions to provide user accessible 572 * registers not implemented in hardware. 573 */ 574 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 575 { 576 struct thread_info *ti = task_thread_info(current); 577 578 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 579 int rd = (opcode & RD) >> 11; 580 int rt = (opcode & RT) >> 16; 581 switch (rd) { 582 case 0: /* CPU number */ 583 regs->regs[rt] = smp_processor_id(); 584 return 0; 585 case 1: /* SYNCI length */ 586 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 587 current_cpu_data.icache.linesz); 588 return 0; 589 case 2: /* Read count register */ 590 regs->regs[rt] = read_c0_count(); 591 return 0; 592 case 3: /* Count register resolution */ 593 switch (current_cpu_data.cputype) { 594 case CPU_20KC: 595 case CPU_25KF: 596 regs->regs[rt] = 1; 597 break; 598 default: 599 regs->regs[rt] = 2; 600 } 601 return 0; 602 case 29: 603 regs->regs[rt] = ti->tp_value; 604 return 0; 605 default: 606 return -1; 607 } 608 } 609 610 /* Not ours. */ 611 return -1; 612 } 613 614 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 615 { 616 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 617 return 0; 618 619 return -1; /* Must be something else ... */ 620 } 621 622 asmlinkage void do_ov(struct pt_regs *regs) 623 { 624 siginfo_t info; 625 626 die_if_kernel("Integer overflow", regs); 627 628 info.si_code = FPE_INTOVF; 629 info.si_signo = SIGFPE; 630 info.si_errno = 0; 631 info.si_addr = (void __user *) regs->cp0_epc; 632 force_sig_info(SIGFPE, &info, current); 633 } 634 635 /* 636 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 637 */ 638 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 639 { 640 siginfo_t info; 641 642 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) 643 == NOTIFY_STOP) 644 return; 645 die_if_kernel("FP exception in kernel code", regs); 646 647 if (fcr31 & FPU_CSR_UNI_X) { 648 int sig; 649 650 /* 651 * Unimplemented operation exception. If we've got the full 652 * software emulator on-board, let's use it... 653 * 654 * Force FPU to dump state into task/thread context. We're 655 * moving a lot of data here for what is probably a single 656 * instruction, but the alternative is to pre-decode the FP 657 * register operands before invoking the emulator, which seems 658 * a bit extreme for what should be an infrequent event. 659 */ 660 /* Ensure 'resume' not overwrite saved fp context again. */ 661 lose_fpu(1); 662 663 /* Run the emulator */ 664 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 665 666 /* 667 * We can't allow the emulated instruction to leave any of 668 * the cause bit set in $fcr31. 669 */ 670 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 671 672 /* Restore the hardware register state */ 673 own_fpu(1); /* Using the FPU again. */ 674 675 /* If something went wrong, signal */ 676 if (sig) 677 force_sig(sig, current); 678 679 return; 680 } else if (fcr31 & FPU_CSR_INV_X) 681 info.si_code = FPE_FLTINV; 682 else if (fcr31 & FPU_CSR_DIV_X) 683 info.si_code = FPE_FLTDIV; 684 else if (fcr31 & FPU_CSR_OVF_X) 685 info.si_code = FPE_FLTOVF; 686 else if (fcr31 & FPU_CSR_UDF_X) 687 info.si_code = FPE_FLTUND; 688 else if (fcr31 & FPU_CSR_INE_X) 689 info.si_code = FPE_FLTRES; 690 else 691 info.si_code = __SI_FAULT; 692 info.si_signo = SIGFPE; 693 info.si_errno = 0; 694 info.si_addr = (void __user *) regs->cp0_epc; 695 force_sig_info(SIGFPE, &info, current); 696 } 697 698 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 699 const char *str) 700 { 701 siginfo_t info; 702 char b[40]; 703 704 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 705 return; 706 707 /* 708 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 709 * insns, even for trap and break codes that indicate arithmetic 710 * failures. Weird ... 711 * But should we continue the brokenness??? --macro 712 */ 713 switch (code) { 714 case BRK_OVERFLOW: 715 case BRK_DIVZERO: 716 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 717 die_if_kernel(b, regs); 718 if (code == BRK_DIVZERO) 719 info.si_code = FPE_INTDIV; 720 else 721 info.si_code = FPE_INTOVF; 722 info.si_signo = SIGFPE; 723 info.si_errno = 0; 724 info.si_addr = (void __user *) regs->cp0_epc; 725 force_sig_info(SIGFPE, &info, current); 726 break; 727 case BRK_BUG: 728 die_if_kernel("Kernel bug detected", regs); 729 force_sig(SIGTRAP, current); 730 break; 731 case BRK_MEMU: 732 /* 733 * Address errors may be deliberately induced by the FPU 734 * emulator to retake control of the CPU after executing the 735 * instruction in the delay slot of an emulated branch. 736 * 737 * Terminate if exception was recognized as a delay slot return 738 * otherwise handle as normal. 739 */ 740 if (do_dsemulret(regs)) 741 return; 742 743 die_if_kernel("Math emu break/trap", regs); 744 force_sig(SIGTRAP, current); 745 break; 746 default: 747 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 748 die_if_kernel(b, regs); 749 force_sig(SIGTRAP, current); 750 } 751 } 752 753 asmlinkage void do_bp(struct pt_regs *regs) 754 { 755 unsigned int opcode, bcode; 756 757 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 758 goto out_sigsegv; 759 760 /* 761 * There is the ancient bug in the MIPS assemblers that the break 762 * code starts left to bit 16 instead to bit 6 in the opcode. 763 * Gas is bug-compatible, but not always, grrr... 764 * We handle both cases with a simple heuristics. --macro 765 */ 766 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 767 if (bcode >= (1 << 10)) 768 bcode >>= 10; 769 770 do_trap_or_bp(regs, bcode, "Break"); 771 return; 772 773 out_sigsegv: 774 force_sig(SIGSEGV, current); 775 } 776 777 asmlinkage void do_tr(struct pt_regs *regs) 778 { 779 unsigned int opcode, tcode = 0; 780 781 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 782 goto out_sigsegv; 783 784 /* Immediate versions don't provide a code. */ 785 if (!(opcode & OPCODE)) 786 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 787 788 do_trap_or_bp(regs, tcode, "Trap"); 789 return; 790 791 out_sigsegv: 792 force_sig(SIGSEGV, current); 793 } 794 795 asmlinkage void do_ri(struct pt_regs *regs) 796 { 797 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 798 unsigned long old_epc = regs->cp0_epc; 799 unsigned int opcode = 0; 800 int status = -1; 801 802 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) 803 == NOTIFY_STOP) 804 return; 805 806 die_if_kernel("Reserved instruction in kernel code", regs); 807 808 if (unlikely(compute_return_epc(regs) < 0)) 809 return; 810 811 if (unlikely(get_user(opcode, epc) < 0)) 812 status = SIGSEGV; 813 814 if (!cpu_has_llsc && status < 0) 815 status = simulate_llsc(regs, opcode); 816 817 if (status < 0) 818 status = simulate_rdhwr(regs, opcode); 819 820 if (status < 0) 821 status = simulate_sync(regs, opcode); 822 823 if (status < 0) 824 status = SIGILL; 825 826 if (unlikely(status > 0)) { 827 regs->cp0_epc = old_epc; /* Undo skip-over. */ 828 force_sig(status, current); 829 } 830 } 831 832 /* 833 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 834 * emulated more than some threshold number of instructions, force migration to 835 * a "CPU" that has FP support. 836 */ 837 static void mt_ase_fp_affinity(void) 838 { 839 #ifdef CONFIG_MIPS_MT_FPAFF 840 if (mt_fpemul_threshold > 0 && 841 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 842 /* 843 * If there's no FPU present, or if the application has already 844 * restricted the allowed set to exclude any CPUs with FPUs, 845 * we'll skip the procedure. 846 */ 847 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 848 cpumask_t tmask; 849 850 current->thread.user_cpus_allowed 851 = current->cpus_allowed; 852 cpus_and(tmask, current->cpus_allowed, 853 mt_fpu_cpumask); 854 set_cpus_allowed(current, tmask); 855 set_thread_flag(TIF_FPUBOUND); 856 } 857 } 858 #endif /* CONFIG_MIPS_MT_FPAFF */ 859 } 860 861 asmlinkage void do_cpu(struct pt_regs *regs) 862 { 863 unsigned int __user *epc; 864 unsigned long old_epc; 865 unsigned int opcode; 866 unsigned int cpid; 867 int status; 868 unsigned long __maybe_unused flags; 869 870 die_if_kernel("do_cpu invoked from kernel context!", regs); 871 872 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 873 874 switch (cpid) { 875 case 0: 876 epc = (unsigned int __user *)exception_epc(regs); 877 old_epc = regs->cp0_epc; 878 opcode = 0; 879 status = -1; 880 881 if (unlikely(compute_return_epc(regs) < 0)) 882 return; 883 884 if (unlikely(get_user(opcode, epc) < 0)) 885 status = SIGSEGV; 886 887 if (!cpu_has_llsc && status < 0) 888 status = simulate_llsc(regs, opcode); 889 890 if (status < 0) 891 status = simulate_rdhwr(regs, opcode); 892 893 if (status < 0) 894 status = SIGILL; 895 896 if (unlikely(status > 0)) { 897 regs->cp0_epc = old_epc; /* Undo skip-over. */ 898 force_sig(status, current); 899 } 900 901 return; 902 903 case 1: 904 if (used_math()) /* Using the FPU again. */ 905 own_fpu(1); 906 else { /* First time FPU user. */ 907 init_fpu(); 908 set_used_math(); 909 } 910 911 if (!raw_cpu_has_fpu) { 912 int sig; 913 sig = fpu_emulator_cop1Handler(regs, 914 ¤t->thread.fpu, 0); 915 if (sig) 916 force_sig(sig, current); 917 else 918 mt_ase_fp_affinity(); 919 } 920 921 return; 922 923 case 2: 924 #ifdef CONFIG_CPU_CAVIUM_OCTEON 925 prefetch(¤t->thread.cp2); 926 local_irq_save(flags); 927 KSTK_STATUS(current) |= ST0_CU2; 928 status = read_c0_status(); 929 write_c0_status(status | ST0_CU2); 930 octeon_cop2_restore(&(current->thread.cp2)); 931 write_c0_status(status & ~ST0_CU2); 932 local_irq_restore(flags); 933 return; 934 #endif 935 case 3: 936 break; 937 } 938 939 force_sig(SIGILL, current); 940 } 941 942 asmlinkage void do_mdmx(struct pt_regs *regs) 943 { 944 force_sig(SIGILL, current); 945 } 946 947 asmlinkage void do_watch(struct pt_regs *regs) 948 { 949 u32 cause; 950 951 /* 952 * Clear WP (bit 22) bit of cause register so we don't loop 953 * forever. 954 */ 955 cause = read_c0_cause(); 956 cause &= ~(1 << 22); 957 write_c0_cause(cause); 958 959 /* 960 * If the current thread has the watch registers loaded, save 961 * their values and send SIGTRAP. Otherwise another thread 962 * left the registers set, clear them and continue. 963 */ 964 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 965 mips_read_watch_registers(); 966 force_sig(SIGTRAP, current); 967 } else 968 mips_clear_watch_registers(); 969 } 970 971 asmlinkage void do_mcheck(struct pt_regs *regs) 972 { 973 const int field = 2 * sizeof(unsigned long); 974 int multi_match = regs->cp0_status & ST0_TS; 975 976 show_regs(regs); 977 978 if (multi_match) { 979 printk("Index : %0x\n", read_c0_index()); 980 printk("Pagemask: %0x\n", read_c0_pagemask()); 981 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 982 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 983 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 984 printk("\n"); 985 dump_tlb_all(); 986 } 987 988 show_code((unsigned int __user *) regs->cp0_epc); 989 990 /* 991 * Some chips may have other causes of machine check (e.g. SB1 992 * graduation timer) 993 */ 994 panic("Caught Machine Check exception - %scaused by multiple " 995 "matching entries in the TLB.", 996 (multi_match) ? "" : "not "); 997 } 998 999 asmlinkage void do_mt(struct pt_regs *regs) 1000 { 1001 int subcode; 1002 1003 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1004 >> VPECONTROL_EXCPT_SHIFT; 1005 switch (subcode) { 1006 case 0: 1007 printk(KERN_DEBUG "Thread Underflow\n"); 1008 break; 1009 case 1: 1010 printk(KERN_DEBUG "Thread Overflow\n"); 1011 break; 1012 case 2: 1013 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1014 break; 1015 case 3: 1016 printk(KERN_DEBUG "Gating Storage Exception\n"); 1017 break; 1018 case 4: 1019 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1020 break; 1021 case 5: 1022 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 1023 break; 1024 default: 1025 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1026 subcode); 1027 break; 1028 } 1029 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1030 1031 force_sig(SIGILL, current); 1032 } 1033 1034 1035 asmlinkage void do_dsp(struct pt_regs *regs) 1036 { 1037 if (cpu_has_dsp) 1038 panic("Unexpected DSP exception\n"); 1039 1040 force_sig(SIGILL, current); 1041 } 1042 1043 asmlinkage void do_reserved(struct pt_regs *regs) 1044 { 1045 /* 1046 * Game over - no way to handle this if it ever occurs. Most probably 1047 * caused by a new unknown cpu type or after another deadly 1048 * hard/software error. 1049 */ 1050 show_regs(regs); 1051 panic("Caught reserved exception %ld - should not happen.", 1052 (regs->cp0_cause & 0x7f) >> 2); 1053 } 1054 1055 static int __initdata l1parity = 1; 1056 static int __init nol1parity(char *s) 1057 { 1058 l1parity = 0; 1059 return 1; 1060 } 1061 __setup("nol1par", nol1parity); 1062 static int __initdata l2parity = 1; 1063 static int __init nol2parity(char *s) 1064 { 1065 l2parity = 0; 1066 return 1; 1067 } 1068 __setup("nol2par", nol2parity); 1069 1070 /* 1071 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1072 * it different ways. 1073 */ 1074 static inline void parity_protection_init(void) 1075 { 1076 switch (current_cpu_type()) { 1077 case CPU_24K: 1078 case CPU_34K: 1079 case CPU_74K: 1080 case CPU_1004K: 1081 { 1082 #define ERRCTL_PE 0x80000000 1083 #define ERRCTL_L2P 0x00800000 1084 unsigned long errctl; 1085 unsigned int l1parity_present, l2parity_present; 1086 1087 errctl = read_c0_ecc(); 1088 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1089 1090 /* probe L1 parity support */ 1091 write_c0_ecc(errctl | ERRCTL_PE); 1092 back_to_back_c0_hazard(); 1093 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1094 1095 /* probe L2 parity support */ 1096 write_c0_ecc(errctl|ERRCTL_L2P); 1097 back_to_back_c0_hazard(); 1098 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1099 1100 if (l1parity_present && l2parity_present) { 1101 if (l1parity) 1102 errctl |= ERRCTL_PE; 1103 if (l1parity ^ l2parity) 1104 errctl |= ERRCTL_L2P; 1105 } else if (l1parity_present) { 1106 if (l1parity) 1107 errctl |= ERRCTL_PE; 1108 } else if (l2parity_present) { 1109 if (l2parity) 1110 errctl |= ERRCTL_L2P; 1111 } else { 1112 /* No parity available */ 1113 } 1114 1115 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1116 1117 write_c0_ecc(errctl); 1118 back_to_back_c0_hazard(); 1119 errctl = read_c0_ecc(); 1120 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1121 1122 if (l1parity_present) 1123 printk(KERN_INFO "Cache parity protection %sabled\n", 1124 (errctl & ERRCTL_PE) ? "en" : "dis"); 1125 1126 if (l2parity_present) { 1127 if (l1parity_present && l1parity) 1128 errctl ^= ERRCTL_L2P; 1129 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1130 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1131 } 1132 } 1133 break; 1134 1135 case CPU_5KC: 1136 write_c0_ecc(0x80000000); 1137 back_to_back_c0_hazard(); 1138 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1139 printk(KERN_INFO "Cache parity protection %sabled\n", 1140 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1141 break; 1142 case CPU_20KC: 1143 case CPU_25KF: 1144 /* Clear the DE bit (bit 16) in the c0_status register. */ 1145 printk(KERN_INFO "Enable cache parity protection for " 1146 "MIPS 20KC/25KF CPUs.\n"); 1147 clear_c0_status(ST0_DE); 1148 break; 1149 default: 1150 break; 1151 } 1152 } 1153 1154 asmlinkage void cache_parity_error(void) 1155 { 1156 const int field = 2 * sizeof(unsigned long); 1157 unsigned int reg_val; 1158 1159 /* For the moment, report the problem and hang. */ 1160 printk("Cache error exception:\n"); 1161 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1162 reg_val = read_c0_cacheerr(); 1163 printk("c0_cacheerr == %08x\n", reg_val); 1164 1165 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1166 reg_val & (1<<30) ? "secondary" : "primary", 1167 reg_val & (1<<31) ? "data" : "insn"); 1168 printk("Error bits: %s%s%s%s%s%s%s\n", 1169 reg_val & (1<<29) ? "ED " : "", 1170 reg_val & (1<<28) ? "ET " : "", 1171 reg_val & (1<<26) ? "EE " : "", 1172 reg_val & (1<<25) ? "EB " : "", 1173 reg_val & (1<<24) ? "EI " : "", 1174 reg_val & (1<<23) ? "E1 " : "", 1175 reg_val & (1<<22) ? "E0 " : ""); 1176 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1177 1178 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1179 if (reg_val & (1<<22)) 1180 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1181 1182 if (reg_val & (1<<23)) 1183 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1184 #endif 1185 1186 panic("Can't handle the cache error!"); 1187 } 1188 1189 /* 1190 * SDBBP EJTAG debug exception handler. 1191 * We skip the instruction and return to the next instruction. 1192 */ 1193 void ejtag_exception_handler(struct pt_regs *regs) 1194 { 1195 const int field = 2 * sizeof(unsigned long); 1196 unsigned long depc, old_epc; 1197 unsigned int debug; 1198 1199 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1200 depc = read_c0_depc(); 1201 debug = read_c0_debug(); 1202 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1203 if (debug & 0x80000000) { 1204 /* 1205 * In branch delay slot. 1206 * We cheat a little bit here and use EPC to calculate the 1207 * debug return address (DEPC). EPC is restored after the 1208 * calculation. 1209 */ 1210 old_epc = regs->cp0_epc; 1211 regs->cp0_epc = depc; 1212 __compute_return_epc(regs); 1213 depc = regs->cp0_epc; 1214 regs->cp0_epc = old_epc; 1215 } else 1216 depc += 4; 1217 write_c0_depc(depc); 1218 1219 #if 0 1220 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1221 write_c0_debug(debug | 0x100); 1222 #endif 1223 } 1224 1225 /* 1226 * NMI exception handler. 1227 */ 1228 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1229 { 1230 bust_spinlocks(1); 1231 printk("NMI taken!!!!\n"); 1232 die("NMI", regs); 1233 } 1234 1235 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1236 1237 unsigned long ebase; 1238 unsigned long exception_handlers[32]; 1239 unsigned long vi_handlers[64]; 1240 1241 /* 1242 * As a side effect of the way this is implemented we're limited 1243 * to interrupt handlers in the address range from 1244 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1245 */ 1246 void *set_except_vector(int n, void *addr) 1247 { 1248 unsigned long handler = (unsigned long) addr; 1249 unsigned long old_handler = exception_handlers[n]; 1250 1251 exception_handlers[n] = handler; 1252 if (n == 0 && cpu_has_divec) { 1253 *(u32 *)(ebase + 0x200) = 0x08000000 | 1254 (0x03ffffff & (handler >> 2)); 1255 local_flush_icache_range(ebase + 0x200, ebase + 0x204); 1256 } 1257 return (void *)old_handler; 1258 } 1259 1260 static asmlinkage void do_default_vi(void) 1261 { 1262 show_regs(get_irq_regs()); 1263 panic("Caught unexpected vectored interrupt."); 1264 } 1265 1266 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1267 { 1268 unsigned long handler; 1269 unsigned long old_handler = vi_handlers[n]; 1270 int srssets = current_cpu_data.srsets; 1271 u32 *w; 1272 unsigned char *b; 1273 1274 if (!cpu_has_veic && !cpu_has_vint) 1275 BUG(); 1276 1277 if (addr == NULL) { 1278 handler = (unsigned long) do_default_vi; 1279 srs = 0; 1280 } else 1281 handler = (unsigned long) addr; 1282 vi_handlers[n] = (unsigned long) addr; 1283 1284 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1285 1286 if (srs >= srssets) 1287 panic("Shadow register set %d not supported", srs); 1288 1289 if (cpu_has_veic) { 1290 if (board_bind_eic_interrupt) 1291 board_bind_eic_interrupt(n, srs); 1292 } else if (cpu_has_vint) { 1293 /* SRSMap is only defined if shadow sets are implemented */ 1294 if (srssets > 1) 1295 change_c0_srsmap(0xf << n*4, srs << n*4); 1296 } 1297 1298 if (srs == 0) { 1299 /* 1300 * If no shadow set is selected then use the default handler 1301 * that does normal register saving and a standard interrupt exit 1302 */ 1303 1304 extern char except_vec_vi, except_vec_vi_lui; 1305 extern char except_vec_vi_ori, except_vec_vi_end; 1306 extern char rollback_except_vec_vi; 1307 char *vec_start = (cpu_wait == r4k_wait) ? 1308 &rollback_except_vec_vi : &except_vec_vi; 1309 #ifdef CONFIG_MIPS_MT_SMTC 1310 /* 1311 * We need to provide the SMTC vectored interrupt handler 1312 * not only with the address of the handler, but with the 1313 * Status.IM bit to be masked before going there. 1314 */ 1315 extern char except_vec_vi_mori; 1316 const int mori_offset = &except_vec_vi_mori - vec_start; 1317 #endif /* CONFIG_MIPS_MT_SMTC */ 1318 const int handler_len = &except_vec_vi_end - vec_start; 1319 const int lui_offset = &except_vec_vi_lui - vec_start; 1320 const int ori_offset = &except_vec_vi_ori - vec_start; 1321 1322 if (handler_len > VECTORSPACING) { 1323 /* 1324 * Sigh... panicing won't help as the console 1325 * is probably not configured :( 1326 */ 1327 panic("VECTORSPACING too small"); 1328 } 1329 1330 memcpy(b, vec_start, handler_len); 1331 #ifdef CONFIG_MIPS_MT_SMTC 1332 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1333 1334 w = (u32 *)(b + mori_offset); 1335 *w = (*w & 0xffff0000) | (0x100 << n); 1336 #endif /* CONFIG_MIPS_MT_SMTC */ 1337 w = (u32 *)(b + lui_offset); 1338 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1339 w = (u32 *)(b + ori_offset); 1340 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1341 local_flush_icache_range((unsigned long)b, 1342 (unsigned long)(b+handler_len)); 1343 } 1344 else { 1345 /* 1346 * In other cases jump directly to the interrupt handler 1347 * 1348 * It is the handlers responsibility to save registers if required 1349 * (eg hi/lo) and return from the exception using "eret" 1350 */ 1351 w = (u32 *)b; 1352 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1353 *w = 0; 1354 local_flush_icache_range((unsigned long)b, 1355 (unsigned long)(b+8)); 1356 } 1357 1358 return (void *)old_handler; 1359 } 1360 1361 void *set_vi_handler(int n, vi_handler_t addr) 1362 { 1363 return set_vi_srs_handler(n, addr, 0); 1364 } 1365 1366 /* 1367 * This is used by native signal handling 1368 */ 1369 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1370 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1371 1372 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1373 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1374 1375 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1376 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1377 1378 #ifdef CONFIG_SMP 1379 static int smp_save_fp_context(struct sigcontext __user *sc) 1380 { 1381 return raw_cpu_has_fpu 1382 ? _save_fp_context(sc) 1383 : fpu_emulator_save_context(sc); 1384 } 1385 1386 static int smp_restore_fp_context(struct sigcontext __user *sc) 1387 { 1388 return raw_cpu_has_fpu 1389 ? _restore_fp_context(sc) 1390 : fpu_emulator_restore_context(sc); 1391 } 1392 #endif 1393 1394 static inline void signal_init(void) 1395 { 1396 #ifdef CONFIG_SMP 1397 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1398 save_fp_context = smp_save_fp_context; 1399 restore_fp_context = smp_restore_fp_context; 1400 #else 1401 if (cpu_has_fpu) { 1402 save_fp_context = _save_fp_context; 1403 restore_fp_context = _restore_fp_context; 1404 } else { 1405 save_fp_context = fpu_emulator_save_context; 1406 restore_fp_context = fpu_emulator_restore_context; 1407 } 1408 #endif 1409 } 1410 1411 #ifdef CONFIG_MIPS32_COMPAT 1412 1413 /* 1414 * This is used by 32-bit signal stuff on the 64-bit kernel 1415 */ 1416 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1417 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1418 1419 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1420 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1421 1422 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1423 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1424 1425 static inline void signal32_init(void) 1426 { 1427 if (cpu_has_fpu) { 1428 save_fp_context32 = _save_fp_context32; 1429 restore_fp_context32 = _restore_fp_context32; 1430 } else { 1431 save_fp_context32 = fpu_emulator_save_context32; 1432 restore_fp_context32 = fpu_emulator_restore_context32; 1433 } 1434 } 1435 #endif 1436 1437 extern void cpu_cache_init(void); 1438 extern void tlb_init(void); 1439 extern void flush_tlb_handlers(void); 1440 1441 /* 1442 * Timer interrupt 1443 */ 1444 int cp0_compare_irq; 1445 1446 /* 1447 * Performance counter IRQ or -1 if shared with timer 1448 */ 1449 int cp0_perfcount_irq; 1450 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1451 1452 static int __cpuinitdata noulri; 1453 1454 static int __init ulri_disable(char *s) 1455 { 1456 pr_info("Disabling ulri\n"); 1457 noulri = 1; 1458 1459 return 1; 1460 } 1461 __setup("noulri", ulri_disable); 1462 1463 void __cpuinit per_cpu_trap_init(void) 1464 { 1465 unsigned int cpu = smp_processor_id(); 1466 unsigned int status_set = ST0_CU0; 1467 #ifdef CONFIG_MIPS_MT_SMTC 1468 int secondaryTC = 0; 1469 int bootTC = (cpu == 0); 1470 1471 /* 1472 * Only do per_cpu_trap_init() for first TC of Each VPE. 1473 * Note that this hack assumes that the SMTC init code 1474 * assigns TCs consecutively and in ascending order. 1475 */ 1476 1477 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1478 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1479 secondaryTC = 1; 1480 #endif /* CONFIG_MIPS_MT_SMTC */ 1481 1482 /* 1483 * Disable coprocessors and select 32-bit or 64-bit addressing 1484 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1485 * flag that some firmware may have left set and the TS bit (for 1486 * IP27). Set XX for ISA IV code to work. 1487 */ 1488 #ifdef CONFIG_64BIT 1489 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1490 #endif 1491 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1492 status_set |= ST0_XX; 1493 if (cpu_has_dsp) 1494 status_set |= ST0_MX; 1495 1496 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1497 status_set); 1498 1499 if (cpu_has_mips_r2) { 1500 unsigned int enable = 0x0000000f; 1501 1502 if (!noulri && cpu_has_userlocal) 1503 enable |= (1 << 29); 1504 1505 write_c0_hwrena(enable); 1506 } 1507 1508 #ifdef CONFIG_CPU_CAVIUM_OCTEON 1509 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */ 1510 #endif 1511 1512 #ifdef CONFIG_MIPS_MT_SMTC 1513 if (!secondaryTC) { 1514 #endif /* CONFIG_MIPS_MT_SMTC */ 1515 1516 if (cpu_has_veic || cpu_has_vint) { 1517 write_c0_ebase(ebase); 1518 /* Setting vector spacing enables EI/VI mode */ 1519 change_c0_intctl(0x3e0, VECTORSPACING); 1520 } 1521 if (cpu_has_divec) { 1522 if (cpu_has_mipsmt) { 1523 unsigned int vpflags = dvpe(); 1524 set_c0_cause(CAUSEF_IV); 1525 evpe(vpflags); 1526 } else 1527 set_c0_cause(CAUSEF_IV); 1528 } 1529 1530 /* 1531 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1532 * 1533 * o read IntCtl.IPTI to determine the timer interrupt 1534 * o read IntCtl.IPPCI to determine the performance counter interrupt 1535 */ 1536 if (cpu_has_mips_r2) { 1537 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1538 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1539 if (cp0_perfcount_irq == cp0_compare_irq) 1540 cp0_perfcount_irq = -1; 1541 } else { 1542 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1543 cp0_perfcount_irq = -1; 1544 } 1545 1546 #ifdef CONFIG_MIPS_MT_SMTC 1547 } 1548 #endif /* CONFIG_MIPS_MT_SMTC */ 1549 1550 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1551 TLBMISS_HANDLER_SETUP(); 1552 1553 atomic_inc(&init_mm.mm_count); 1554 current->active_mm = &init_mm; 1555 BUG_ON(current->mm); 1556 enter_lazy_tlb(&init_mm, current); 1557 1558 #ifdef CONFIG_MIPS_MT_SMTC 1559 if (bootTC) { 1560 #endif /* CONFIG_MIPS_MT_SMTC */ 1561 cpu_cache_init(); 1562 tlb_init(); 1563 #ifdef CONFIG_MIPS_MT_SMTC 1564 } else if (!secondaryTC) { 1565 /* 1566 * First TC in non-boot VPE must do subset of tlb_init() 1567 * for MMU countrol registers. 1568 */ 1569 write_c0_pagemask(PM_DEFAULT_MASK); 1570 write_c0_wired(0); 1571 } 1572 #endif /* CONFIG_MIPS_MT_SMTC */ 1573 } 1574 1575 /* Install CPU exception handler */ 1576 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1577 { 1578 memcpy((void *)(ebase + offset), addr, size); 1579 local_flush_icache_range(ebase + offset, ebase + offset + size); 1580 } 1581 1582 static char panic_null_cerr[] __cpuinitdata = 1583 "Trying to set NULL cache error exception handler"; 1584 1585 /* Install uncached CPU exception handler */ 1586 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1587 unsigned long size) 1588 { 1589 #ifdef CONFIG_32BIT 1590 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1591 #endif 1592 #ifdef CONFIG_64BIT 1593 unsigned long uncached_ebase = TO_UNCAC(ebase); 1594 #endif 1595 if (cpu_has_mips_r2) 1596 ebase += (read_c0_ebase() & 0x3ffff000); 1597 1598 if (!addr) 1599 panic(panic_null_cerr); 1600 1601 memcpy((void *)(uncached_ebase + offset), addr, size); 1602 } 1603 1604 static int __initdata rdhwr_noopt; 1605 static int __init set_rdhwr_noopt(char *str) 1606 { 1607 rdhwr_noopt = 1; 1608 return 1; 1609 } 1610 1611 __setup("rdhwr_noopt", set_rdhwr_noopt); 1612 1613 void __init trap_init(void) 1614 { 1615 extern char except_vec3_generic, except_vec3_r4000; 1616 extern char except_vec4; 1617 unsigned long i; 1618 int rollback; 1619 1620 check_wait(); 1621 rollback = (cpu_wait == r4k_wait); 1622 1623 #if defined(CONFIG_KGDB) 1624 if (kgdb_early_setup) 1625 return; /* Already done */ 1626 #endif 1627 1628 if (cpu_has_veic || cpu_has_vint) 1629 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1630 else { 1631 ebase = CAC_BASE; 1632 if (cpu_has_mips_r2) 1633 ebase += (read_c0_ebase() & 0x3ffff000); 1634 } 1635 1636 per_cpu_trap_init(); 1637 1638 /* 1639 * Copy the generic exception handlers to their final destination. 1640 * This will be overriden later as suitable for a particular 1641 * configuration. 1642 */ 1643 set_handler(0x180, &except_vec3_generic, 0x80); 1644 1645 /* 1646 * Setup default vectors 1647 */ 1648 for (i = 0; i <= 31; i++) 1649 set_except_vector(i, handle_reserved); 1650 1651 /* 1652 * Copy the EJTAG debug exception vector handler code to it's final 1653 * destination. 1654 */ 1655 if (cpu_has_ejtag && board_ejtag_handler_setup) 1656 board_ejtag_handler_setup(); 1657 1658 /* 1659 * Only some CPUs have the watch exceptions. 1660 */ 1661 if (cpu_has_watch) 1662 set_except_vector(23, handle_watch); 1663 1664 /* 1665 * Initialise interrupt handlers 1666 */ 1667 if (cpu_has_veic || cpu_has_vint) { 1668 int nvec = cpu_has_veic ? 64 : 8; 1669 for (i = 0; i < nvec; i++) 1670 set_vi_handler(i, NULL); 1671 } 1672 else if (cpu_has_divec) 1673 set_handler(0x200, &except_vec4, 0x8); 1674 1675 /* 1676 * Some CPUs can enable/disable for cache parity detection, but does 1677 * it different ways. 1678 */ 1679 parity_protection_init(); 1680 1681 /* 1682 * The Data Bus Errors / Instruction Bus Errors are signaled 1683 * by external hardware. Therefore these two exceptions 1684 * may have board specific handlers. 1685 */ 1686 if (board_be_init) 1687 board_be_init(); 1688 1689 set_except_vector(0, rollback ? rollback_handle_int : handle_int); 1690 set_except_vector(1, handle_tlbm); 1691 set_except_vector(2, handle_tlbl); 1692 set_except_vector(3, handle_tlbs); 1693 1694 set_except_vector(4, handle_adel); 1695 set_except_vector(5, handle_ades); 1696 1697 set_except_vector(6, handle_ibe); 1698 set_except_vector(7, handle_dbe); 1699 1700 set_except_vector(8, handle_sys); 1701 set_except_vector(9, handle_bp); 1702 set_except_vector(10, rdhwr_noopt ? handle_ri : 1703 (cpu_has_vtag_icache ? 1704 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1705 set_except_vector(11, handle_cpu); 1706 set_except_vector(12, handle_ov); 1707 set_except_vector(13, handle_tr); 1708 1709 if (current_cpu_type() == CPU_R6000 || 1710 current_cpu_type() == CPU_R6000A) { 1711 /* 1712 * The R6000 is the only R-series CPU that features a machine 1713 * check exception (similar to the R4000 cache error) and 1714 * unaligned ldc1/sdc1 exception. The handlers have not been 1715 * written yet. Well, anyway there is no R6000 machine on the 1716 * current list of targets for Linux/MIPS. 1717 * (Duh, crap, there is someone with a triple R6k machine) 1718 */ 1719 //set_except_vector(14, handle_mc); 1720 //set_except_vector(15, handle_ndc); 1721 } 1722 1723 1724 if (board_nmi_handler_setup) 1725 board_nmi_handler_setup(); 1726 1727 if (cpu_has_fpu && !cpu_has_nofpuex) 1728 set_except_vector(15, handle_fpe); 1729 1730 set_except_vector(22, handle_mdmx); 1731 1732 if (cpu_has_mcheck) 1733 set_except_vector(24, handle_mcheck); 1734 1735 if (cpu_has_mipsmt) 1736 set_except_vector(25, handle_mt); 1737 1738 set_except_vector(26, handle_dsp); 1739 1740 if (cpu_has_vce) 1741 /* Special exception: R4[04]00 uses also the divec space. */ 1742 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); 1743 else if (cpu_has_4kex) 1744 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); 1745 else 1746 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1747 1748 signal_init(); 1749 #ifdef CONFIG_MIPS32_COMPAT 1750 signal32_init(); 1751 #endif 1752 1753 local_flush_icache_range(ebase, ebase + 0x400); 1754 flush_tlb_handlers(); 1755 1756 sort_extable(__start___dbe_table, __stop___dbe_table); 1757 } 1758