1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/compiler.h> 16 #include <linux/init.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/sched.h> 20 #include <linux/smp.h> 21 #include <linux/spinlock.h> 22 #include <linux/kallsyms.h> 23 #include <linux/bootmem.h> 24 #include <linux/interrupt.h> 25 #include <linux/ptrace.h> 26 #include <linux/kgdb.h> 27 #include <linux/kdebug.h> 28 29 #include <asm/bootinfo.h> 30 #include <asm/branch.h> 31 #include <asm/break.h> 32 #include <asm/cpu.h> 33 #include <asm/dsp.h> 34 #include <asm/fpu.h> 35 #include <asm/mipsregs.h> 36 #include <asm/mipsmtregs.h> 37 #include <asm/module.h> 38 #include <asm/pgtable.h> 39 #include <asm/ptrace.h> 40 #include <asm/sections.h> 41 #include <asm/system.h> 42 #include <asm/tlbdebug.h> 43 #include <asm/traps.h> 44 #include <asm/uaccess.h> 45 #include <asm/mmu_context.h> 46 #include <asm/types.h> 47 #include <asm/stacktrace.h> 48 49 extern asmlinkage void handle_int(void); 50 extern asmlinkage void handle_tlbm(void); 51 extern asmlinkage void handle_tlbl(void); 52 extern asmlinkage void handle_tlbs(void); 53 extern asmlinkage void handle_adel(void); 54 extern asmlinkage void handle_ades(void); 55 extern asmlinkage void handle_ibe(void); 56 extern asmlinkage void handle_dbe(void); 57 extern asmlinkage void handle_sys(void); 58 extern asmlinkage void handle_bp(void); 59 extern asmlinkage void handle_ri(void); 60 extern asmlinkage void handle_ri_rdhwr_vivt(void); 61 extern asmlinkage void handle_ri_rdhwr(void); 62 extern asmlinkage void handle_cpu(void); 63 extern asmlinkage void handle_ov(void); 64 extern asmlinkage void handle_tr(void); 65 extern asmlinkage void handle_fpe(void); 66 extern asmlinkage void handle_mdmx(void); 67 extern asmlinkage void handle_watch(void); 68 extern asmlinkage void handle_mt(void); 69 extern asmlinkage void handle_dsp(void); 70 extern asmlinkage void handle_mcheck(void); 71 extern asmlinkage void handle_reserved(void); 72 73 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 74 struct mips_fpu_struct *ctx, int has_fpu); 75 76 void (*board_be_init)(void); 77 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 78 void (*board_nmi_handler_setup)(void); 79 void (*board_ejtag_handler_setup)(void); 80 void (*board_bind_eic_interrupt)(int irq, int regset); 81 82 83 static void show_raw_backtrace(unsigned long reg29) 84 { 85 unsigned long *sp = (unsigned long *)(reg29 & ~3); 86 unsigned long addr; 87 88 printk("Call Trace:"); 89 #ifdef CONFIG_KALLSYMS 90 printk("\n"); 91 #endif 92 while (!kstack_end(sp)) { 93 unsigned long __user *p = 94 (unsigned long __user *)(unsigned long)sp++; 95 if (__get_user(addr, p)) { 96 printk(" (Bad stack address)"); 97 break; 98 } 99 if (__kernel_text_address(addr)) 100 print_ip_sym(addr); 101 } 102 printk("\n"); 103 } 104 105 #ifdef CONFIG_KALLSYMS 106 int raw_show_trace; 107 static int __init set_raw_show_trace(char *str) 108 { 109 raw_show_trace = 1; 110 return 1; 111 } 112 __setup("raw_show_trace", set_raw_show_trace); 113 #endif 114 115 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 116 { 117 unsigned long sp = regs->regs[29]; 118 unsigned long ra = regs->regs[31]; 119 unsigned long pc = regs->cp0_epc; 120 121 if (raw_show_trace || !__kernel_text_address(pc)) { 122 show_raw_backtrace(sp); 123 return; 124 } 125 printk("Call Trace:\n"); 126 do { 127 print_ip_sym(pc); 128 pc = unwind_stack(task, &sp, pc, &ra); 129 } while (pc); 130 printk("\n"); 131 } 132 133 /* 134 * This routine abuses get_user()/put_user() to reference pointers 135 * with at least a bit of error checking ... 136 */ 137 static void show_stacktrace(struct task_struct *task, 138 const struct pt_regs *regs) 139 { 140 const int field = 2 * sizeof(unsigned long); 141 long stackdata; 142 int i; 143 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 144 145 printk("Stack :"); 146 i = 0; 147 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 148 if (i && ((i % (64 / field)) == 0)) 149 printk("\n "); 150 if (i > 39) { 151 printk(" ..."); 152 break; 153 } 154 155 if (__get_user(stackdata, sp++)) { 156 printk(" (Bad stack address)"); 157 break; 158 } 159 160 printk(" %0*lx", field, stackdata); 161 i++; 162 } 163 printk("\n"); 164 show_backtrace(task, regs); 165 } 166 167 void show_stack(struct task_struct *task, unsigned long *sp) 168 { 169 struct pt_regs regs; 170 if (sp) { 171 regs.regs[29] = (unsigned long)sp; 172 regs.regs[31] = 0; 173 regs.cp0_epc = 0; 174 } else { 175 if (task && task != current) { 176 regs.regs[29] = task->thread.reg29; 177 regs.regs[31] = 0; 178 regs.cp0_epc = task->thread.reg31; 179 } else { 180 prepare_frametrace(®s); 181 } 182 } 183 show_stacktrace(task, ®s); 184 } 185 186 /* 187 * The architecture-independent dump_stack generator 188 */ 189 void dump_stack(void) 190 { 191 struct pt_regs regs; 192 193 prepare_frametrace(®s); 194 show_backtrace(current, ®s); 195 } 196 197 EXPORT_SYMBOL(dump_stack); 198 199 static void show_code(unsigned int __user *pc) 200 { 201 long i; 202 unsigned short __user *pc16 = NULL; 203 204 printk("\nCode:"); 205 206 if ((unsigned long)pc & 1) 207 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 208 for(i = -3 ; i < 6 ; i++) { 209 unsigned int insn; 210 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 211 printk(" (Bad address in epc)\n"); 212 break; 213 } 214 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 215 } 216 } 217 218 static void __show_regs(const struct pt_regs *regs) 219 { 220 const int field = 2 * sizeof(unsigned long); 221 unsigned int cause = regs->cp0_cause; 222 int i; 223 224 printk("Cpu %d\n", smp_processor_id()); 225 226 /* 227 * Saved main processor registers 228 */ 229 for (i = 0; i < 32; ) { 230 if ((i % 4) == 0) 231 printk("$%2d :", i); 232 if (i == 0) 233 printk(" %0*lx", field, 0UL); 234 else if (i == 26 || i == 27) 235 printk(" %*s", field, ""); 236 else 237 printk(" %0*lx", field, regs->regs[i]); 238 239 i++; 240 if ((i % 4) == 0) 241 printk("\n"); 242 } 243 244 #ifdef CONFIG_CPU_HAS_SMARTMIPS 245 printk("Acx : %0*lx\n", field, regs->acx); 246 #endif 247 printk("Hi : %0*lx\n", field, regs->hi); 248 printk("Lo : %0*lx\n", field, regs->lo); 249 250 /* 251 * Saved cp0 registers 252 */ 253 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 254 (void *) regs->cp0_epc); 255 printk(" %s\n", print_tainted()); 256 printk("ra : %0*lx %pS\n", field, regs->regs[31], 257 (void *) regs->regs[31]); 258 259 printk("Status: %08x ", (uint32_t) regs->cp0_status); 260 261 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 262 if (regs->cp0_status & ST0_KUO) 263 printk("KUo "); 264 if (regs->cp0_status & ST0_IEO) 265 printk("IEo "); 266 if (regs->cp0_status & ST0_KUP) 267 printk("KUp "); 268 if (regs->cp0_status & ST0_IEP) 269 printk("IEp "); 270 if (regs->cp0_status & ST0_KUC) 271 printk("KUc "); 272 if (regs->cp0_status & ST0_IEC) 273 printk("IEc "); 274 } else { 275 if (regs->cp0_status & ST0_KX) 276 printk("KX "); 277 if (regs->cp0_status & ST0_SX) 278 printk("SX "); 279 if (regs->cp0_status & ST0_UX) 280 printk("UX "); 281 switch (regs->cp0_status & ST0_KSU) { 282 case KSU_USER: 283 printk("USER "); 284 break; 285 case KSU_SUPERVISOR: 286 printk("SUPERVISOR "); 287 break; 288 case KSU_KERNEL: 289 printk("KERNEL "); 290 break; 291 default: 292 printk("BAD_MODE "); 293 break; 294 } 295 if (regs->cp0_status & ST0_ERL) 296 printk("ERL "); 297 if (regs->cp0_status & ST0_EXL) 298 printk("EXL "); 299 if (regs->cp0_status & ST0_IE) 300 printk("IE "); 301 } 302 printk("\n"); 303 304 printk("Cause : %08x\n", cause); 305 306 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 307 if (1 <= cause && cause <= 5) 308 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 309 310 printk("PrId : %08x (%s)\n", read_c0_prid(), 311 cpu_name_string()); 312 } 313 314 /* 315 * FIXME: really the generic show_regs should take a const pointer argument. 316 */ 317 void show_regs(struct pt_regs *regs) 318 { 319 __show_regs((struct pt_regs *)regs); 320 } 321 322 void show_registers(const struct pt_regs *regs) 323 { 324 const int field = 2 * sizeof(unsigned long); 325 326 __show_regs(regs); 327 print_modules(); 328 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 329 current->comm, current->pid, current_thread_info(), current, 330 field, current_thread_info()->tp_value); 331 if (cpu_has_userlocal) { 332 unsigned long tls; 333 334 tls = read_c0_userlocal(); 335 if (tls != current_thread_info()->tp_value) 336 printk("*HwTLS: %0*lx\n", field, tls); 337 } 338 339 show_stacktrace(current, regs); 340 show_code((unsigned int __user *) regs->cp0_epc); 341 printk("\n"); 342 } 343 344 static DEFINE_SPINLOCK(die_lock); 345 346 void __noreturn die(const char * str, const struct pt_regs * regs) 347 { 348 static int die_counter; 349 #ifdef CONFIG_MIPS_MT_SMTC 350 unsigned long dvpret = dvpe(); 351 #endif /* CONFIG_MIPS_MT_SMTC */ 352 353 console_verbose(); 354 spin_lock_irq(&die_lock); 355 bust_spinlocks(1); 356 #ifdef CONFIG_MIPS_MT_SMTC 357 mips_mt_regdump(dvpret); 358 #endif /* CONFIG_MIPS_MT_SMTC */ 359 printk("%s[#%d]:\n", str, ++die_counter); 360 show_registers(regs); 361 add_taint(TAINT_DIE); 362 spin_unlock_irq(&die_lock); 363 364 if (in_interrupt()) 365 panic("Fatal exception in interrupt"); 366 367 if (panic_on_oops) { 368 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 369 ssleep(5); 370 panic("Fatal exception"); 371 } 372 373 do_exit(SIGSEGV); 374 } 375 376 extern const struct exception_table_entry __start___dbe_table[]; 377 extern const struct exception_table_entry __stop___dbe_table[]; 378 379 __asm__( 380 " .section __dbe_table, \"a\"\n" 381 " .previous \n"); 382 383 /* Given an address, look for it in the exception tables. */ 384 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 385 { 386 const struct exception_table_entry *e; 387 388 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 389 if (!e) 390 e = search_module_dbetables(addr); 391 return e; 392 } 393 394 asmlinkage void do_be(struct pt_regs *regs) 395 { 396 const int field = 2 * sizeof(unsigned long); 397 const struct exception_table_entry *fixup = NULL; 398 int data = regs->cp0_cause & 4; 399 int action = MIPS_BE_FATAL; 400 401 /* XXX For now. Fixme, this searches the wrong table ... */ 402 if (data && !user_mode(regs)) 403 fixup = search_dbe_tables(exception_epc(regs)); 404 405 if (fixup) 406 action = MIPS_BE_FIXUP; 407 408 if (board_be_handler) 409 action = board_be_handler(regs, fixup != NULL); 410 411 switch (action) { 412 case MIPS_BE_DISCARD: 413 return; 414 case MIPS_BE_FIXUP: 415 if (fixup) { 416 regs->cp0_epc = fixup->nextinsn; 417 return; 418 } 419 break; 420 default: 421 break; 422 } 423 424 /* 425 * Assume it would be too dangerous to continue ... 426 */ 427 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 428 data ? "Data" : "Instruction", 429 field, regs->cp0_epc, field, regs->regs[31]); 430 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) 431 == NOTIFY_STOP) 432 return; 433 434 die_if_kernel("Oops", regs); 435 force_sig(SIGBUS, current); 436 } 437 438 /* 439 * ll/sc, rdhwr, sync emulation 440 */ 441 442 #define OPCODE 0xfc000000 443 #define BASE 0x03e00000 444 #define RT 0x001f0000 445 #define OFFSET 0x0000ffff 446 #define LL 0xc0000000 447 #define SC 0xe0000000 448 #define SPEC0 0x00000000 449 #define SPEC3 0x7c000000 450 #define RD 0x0000f800 451 #define FUNC 0x0000003f 452 #define SYNC 0x0000000f 453 #define RDHWR 0x0000003b 454 455 /* 456 * The ll_bit is cleared by r*_switch.S 457 */ 458 459 unsigned long ll_bit; 460 461 static struct task_struct *ll_task = NULL; 462 463 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 464 { 465 unsigned long value, __user *vaddr; 466 long offset; 467 468 /* 469 * analyse the ll instruction that just caused a ri exception 470 * and put the referenced address to addr. 471 */ 472 473 /* sign extend offset */ 474 offset = opcode & OFFSET; 475 offset <<= 16; 476 offset >>= 16; 477 478 vaddr = (unsigned long __user *) 479 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 480 481 if ((unsigned long)vaddr & 3) 482 return SIGBUS; 483 if (get_user(value, vaddr)) 484 return SIGSEGV; 485 486 preempt_disable(); 487 488 if (ll_task == NULL || ll_task == current) { 489 ll_bit = 1; 490 } else { 491 ll_bit = 0; 492 } 493 ll_task = current; 494 495 preempt_enable(); 496 497 regs->regs[(opcode & RT) >> 16] = value; 498 499 return 0; 500 } 501 502 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 503 { 504 unsigned long __user *vaddr; 505 unsigned long reg; 506 long offset; 507 508 /* 509 * analyse the sc instruction that just caused a ri exception 510 * and put the referenced address to addr. 511 */ 512 513 /* sign extend offset */ 514 offset = opcode & OFFSET; 515 offset <<= 16; 516 offset >>= 16; 517 518 vaddr = (unsigned long __user *) 519 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 520 reg = (opcode & RT) >> 16; 521 522 if ((unsigned long)vaddr & 3) 523 return SIGBUS; 524 525 preempt_disable(); 526 527 if (ll_bit == 0 || ll_task != current) { 528 regs->regs[reg] = 0; 529 preempt_enable(); 530 return 0; 531 } 532 533 preempt_enable(); 534 535 if (put_user(regs->regs[reg], vaddr)) 536 return SIGSEGV; 537 538 regs->regs[reg] = 1; 539 540 return 0; 541 } 542 543 /* 544 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 545 * opcodes are supposed to result in coprocessor unusable exceptions if 546 * executed on ll/sc-less processors. That's the theory. In practice a 547 * few processors such as NEC's VR4100 throw reserved instruction exceptions 548 * instead, so we're doing the emulation thing in both exception handlers. 549 */ 550 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 551 { 552 if ((opcode & OPCODE) == LL) 553 return simulate_ll(regs, opcode); 554 if ((opcode & OPCODE) == SC) 555 return simulate_sc(regs, opcode); 556 557 return -1; /* Must be something else ... */ 558 } 559 560 /* 561 * Simulate trapping 'rdhwr' instructions to provide user accessible 562 * registers not implemented in hardware. 563 */ 564 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) 565 { 566 struct thread_info *ti = task_thread_info(current); 567 568 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 569 int rd = (opcode & RD) >> 11; 570 int rt = (opcode & RT) >> 16; 571 switch (rd) { 572 case 0: /* CPU number */ 573 regs->regs[rt] = smp_processor_id(); 574 return 0; 575 case 1: /* SYNCI length */ 576 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 577 current_cpu_data.icache.linesz); 578 return 0; 579 case 2: /* Read count register */ 580 regs->regs[rt] = read_c0_count(); 581 return 0; 582 case 3: /* Count register resolution */ 583 switch (current_cpu_data.cputype) { 584 case CPU_20KC: 585 case CPU_25KF: 586 regs->regs[rt] = 1; 587 break; 588 default: 589 regs->regs[rt] = 2; 590 } 591 return 0; 592 case 29: 593 regs->regs[rt] = ti->tp_value; 594 return 0; 595 default: 596 return -1; 597 } 598 } 599 600 /* Not ours. */ 601 return -1; 602 } 603 604 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 605 { 606 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) 607 return 0; 608 609 return -1; /* Must be something else ... */ 610 } 611 612 asmlinkage void do_ov(struct pt_regs *regs) 613 { 614 siginfo_t info; 615 616 die_if_kernel("Integer overflow", regs); 617 618 info.si_code = FPE_INTOVF; 619 info.si_signo = SIGFPE; 620 info.si_errno = 0; 621 info.si_addr = (void __user *) regs->cp0_epc; 622 force_sig_info(SIGFPE, &info, current); 623 } 624 625 /* 626 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 627 */ 628 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 629 { 630 siginfo_t info; 631 632 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) 633 == NOTIFY_STOP) 634 return; 635 die_if_kernel("FP exception in kernel code", regs); 636 637 if (fcr31 & FPU_CSR_UNI_X) { 638 int sig; 639 640 /* 641 * Unimplemented operation exception. If we've got the full 642 * software emulator on-board, let's use it... 643 * 644 * Force FPU to dump state into task/thread context. We're 645 * moving a lot of data here for what is probably a single 646 * instruction, but the alternative is to pre-decode the FP 647 * register operands before invoking the emulator, which seems 648 * a bit extreme for what should be an infrequent event. 649 */ 650 /* Ensure 'resume' not overwrite saved fp context again. */ 651 lose_fpu(1); 652 653 /* Run the emulator */ 654 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 655 656 /* 657 * We can't allow the emulated instruction to leave any of 658 * the cause bit set in $fcr31. 659 */ 660 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 661 662 /* Restore the hardware register state */ 663 own_fpu(1); /* Using the FPU again. */ 664 665 /* If something went wrong, signal */ 666 if (sig) 667 force_sig(sig, current); 668 669 return; 670 } else if (fcr31 & FPU_CSR_INV_X) 671 info.si_code = FPE_FLTINV; 672 else if (fcr31 & FPU_CSR_DIV_X) 673 info.si_code = FPE_FLTDIV; 674 else if (fcr31 & FPU_CSR_OVF_X) 675 info.si_code = FPE_FLTOVF; 676 else if (fcr31 & FPU_CSR_UDF_X) 677 info.si_code = FPE_FLTUND; 678 else if (fcr31 & FPU_CSR_INE_X) 679 info.si_code = FPE_FLTRES; 680 else 681 info.si_code = __SI_FAULT; 682 info.si_signo = SIGFPE; 683 info.si_errno = 0; 684 info.si_addr = (void __user *) regs->cp0_epc; 685 force_sig_info(SIGFPE, &info, current); 686 } 687 688 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 689 const char *str) 690 { 691 siginfo_t info; 692 char b[40]; 693 694 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 695 return; 696 697 /* 698 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 699 * insns, even for trap and break codes that indicate arithmetic 700 * failures. Weird ... 701 * But should we continue the brokenness??? --macro 702 */ 703 switch (code) { 704 case BRK_OVERFLOW: 705 case BRK_DIVZERO: 706 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 707 die_if_kernel(b, regs); 708 if (code == BRK_DIVZERO) 709 info.si_code = FPE_INTDIV; 710 else 711 info.si_code = FPE_INTOVF; 712 info.si_signo = SIGFPE; 713 info.si_errno = 0; 714 info.si_addr = (void __user *) regs->cp0_epc; 715 force_sig_info(SIGFPE, &info, current); 716 break; 717 case BRK_BUG: 718 die_if_kernel("Kernel bug detected", regs); 719 force_sig(SIGTRAP, current); 720 break; 721 default: 722 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 723 die_if_kernel(b, regs); 724 force_sig(SIGTRAP, current); 725 } 726 } 727 728 asmlinkage void do_bp(struct pt_regs *regs) 729 { 730 unsigned int opcode, bcode; 731 732 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 733 goto out_sigsegv; 734 735 /* 736 * There is the ancient bug in the MIPS assemblers that the break 737 * code starts left to bit 16 instead to bit 6 in the opcode. 738 * Gas is bug-compatible, but not always, grrr... 739 * We handle both cases with a simple heuristics. --macro 740 */ 741 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 742 if (bcode >= (1 << 10)) 743 bcode >>= 10; 744 745 do_trap_or_bp(regs, bcode, "Break"); 746 return; 747 748 out_sigsegv: 749 force_sig(SIGSEGV, current); 750 } 751 752 asmlinkage void do_tr(struct pt_regs *regs) 753 { 754 unsigned int opcode, tcode = 0; 755 756 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 757 goto out_sigsegv; 758 759 /* Immediate versions don't provide a code. */ 760 if (!(opcode & OPCODE)) 761 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 762 763 do_trap_or_bp(regs, tcode, "Trap"); 764 return; 765 766 out_sigsegv: 767 force_sig(SIGSEGV, current); 768 } 769 770 asmlinkage void do_ri(struct pt_regs *regs) 771 { 772 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 773 unsigned long old_epc = regs->cp0_epc; 774 unsigned int opcode = 0; 775 int status = -1; 776 777 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) 778 == NOTIFY_STOP) 779 return; 780 781 die_if_kernel("Reserved instruction in kernel code", regs); 782 783 if (unlikely(compute_return_epc(regs) < 0)) 784 return; 785 786 if (unlikely(get_user(opcode, epc) < 0)) 787 status = SIGSEGV; 788 789 if (!cpu_has_llsc && status < 0) 790 status = simulate_llsc(regs, opcode); 791 792 if (status < 0) 793 status = simulate_rdhwr(regs, opcode); 794 795 if (status < 0) 796 status = simulate_sync(regs, opcode); 797 798 if (status < 0) 799 status = SIGILL; 800 801 if (unlikely(status > 0)) { 802 regs->cp0_epc = old_epc; /* Undo skip-over. */ 803 force_sig(status, current); 804 } 805 } 806 807 /* 808 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 809 * emulated more than some threshold number of instructions, force migration to 810 * a "CPU" that has FP support. 811 */ 812 static void mt_ase_fp_affinity(void) 813 { 814 #ifdef CONFIG_MIPS_MT_FPAFF 815 if (mt_fpemul_threshold > 0 && 816 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 817 /* 818 * If there's no FPU present, or if the application has already 819 * restricted the allowed set to exclude any CPUs with FPUs, 820 * we'll skip the procedure. 821 */ 822 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 823 cpumask_t tmask; 824 825 cpus_and(tmask, current->thread.user_cpus_allowed, 826 mt_fpu_cpumask); 827 set_cpus_allowed(current, tmask); 828 set_thread_flag(TIF_FPUBOUND); 829 } 830 } 831 #endif /* CONFIG_MIPS_MT_FPAFF */ 832 } 833 834 asmlinkage void do_cpu(struct pt_regs *regs) 835 { 836 unsigned int __user *epc; 837 unsigned long old_epc; 838 unsigned int opcode; 839 unsigned int cpid; 840 int status; 841 842 die_if_kernel("do_cpu invoked from kernel context!", regs); 843 844 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 845 846 switch (cpid) { 847 case 0: 848 epc = (unsigned int __user *)exception_epc(regs); 849 old_epc = regs->cp0_epc; 850 opcode = 0; 851 status = -1; 852 853 if (unlikely(compute_return_epc(regs) < 0)) 854 return; 855 856 if (unlikely(get_user(opcode, epc) < 0)) 857 status = SIGSEGV; 858 859 if (!cpu_has_llsc && status < 0) 860 status = simulate_llsc(regs, opcode); 861 862 if (status < 0) 863 status = simulate_rdhwr(regs, opcode); 864 865 if (status < 0) 866 status = SIGILL; 867 868 if (unlikely(status > 0)) { 869 regs->cp0_epc = old_epc; /* Undo skip-over. */ 870 force_sig(status, current); 871 } 872 873 return; 874 875 case 1: 876 if (used_math()) /* Using the FPU again. */ 877 own_fpu(1); 878 else { /* First time FPU user. */ 879 init_fpu(); 880 set_used_math(); 881 } 882 883 if (!raw_cpu_has_fpu) { 884 int sig; 885 sig = fpu_emulator_cop1Handler(regs, 886 ¤t->thread.fpu, 0); 887 if (sig) 888 force_sig(sig, current); 889 else 890 mt_ase_fp_affinity(); 891 } 892 893 return; 894 895 case 2: 896 case 3: 897 break; 898 } 899 900 force_sig(SIGILL, current); 901 } 902 903 asmlinkage void do_mdmx(struct pt_regs *regs) 904 { 905 force_sig(SIGILL, current); 906 } 907 908 asmlinkage void do_watch(struct pt_regs *regs) 909 { 910 /* 911 * We use the watch exception where available to detect stack 912 * overflows. 913 */ 914 dump_tlb_all(); 915 show_regs(regs); 916 panic("Caught WATCH exception - probably caused by stack overflow."); 917 } 918 919 asmlinkage void do_mcheck(struct pt_regs *regs) 920 { 921 const int field = 2 * sizeof(unsigned long); 922 int multi_match = regs->cp0_status & ST0_TS; 923 924 show_regs(regs); 925 926 if (multi_match) { 927 printk("Index : %0x\n", read_c0_index()); 928 printk("Pagemask: %0x\n", read_c0_pagemask()); 929 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 930 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 931 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 932 printk("\n"); 933 dump_tlb_all(); 934 } 935 936 show_code((unsigned int __user *) regs->cp0_epc); 937 938 /* 939 * Some chips may have other causes of machine check (e.g. SB1 940 * graduation timer) 941 */ 942 panic("Caught Machine Check exception - %scaused by multiple " 943 "matching entries in the TLB.", 944 (multi_match) ? "" : "not "); 945 } 946 947 asmlinkage void do_mt(struct pt_regs *regs) 948 { 949 int subcode; 950 951 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 952 >> VPECONTROL_EXCPT_SHIFT; 953 switch (subcode) { 954 case 0: 955 printk(KERN_DEBUG "Thread Underflow\n"); 956 break; 957 case 1: 958 printk(KERN_DEBUG "Thread Overflow\n"); 959 break; 960 case 2: 961 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 962 break; 963 case 3: 964 printk(KERN_DEBUG "Gating Storage Exception\n"); 965 break; 966 case 4: 967 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 968 break; 969 case 5: 970 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 971 break; 972 default: 973 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 974 subcode); 975 break; 976 } 977 die_if_kernel("MIPS MT Thread exception in kernel", regs); 978 979 force_sig(SIGILL, current); 980 } 981 982 983 asmlinkage void do_dsp(struct pt_regs *regs) 984 { 985 if (cpu_has_dsp) 986 panic("Unexpected DSP exception\n"); 987 988 force_sig(SIGILL, current); 989 } 990 991 asmlinkage void do_reserved(struct pt_regs *regs) 992 { 993 /* 994 * Game over - no way to handle this if it ever occurs. Most probably 995 * caused by a new unknown cpu type or after another deadly 996 * hard/software error. 997 */ 998 show_regs(regs); 999 panic("Caught reserved exception %ld - should not happen.", 1000 (regs->cp0_cause & 0x7f) >> 2); 1001 } 1002 1003 static int __initdata l1parity = 1; 1004 static int __init nol1parity(char *s) 1005 { 1006 l1parity = 0; 1007 return 1; 1008 } 1009 __setup("nol1par", nol1parity); 1010 static int __initdata l2parity = 1; 1011 static int __init nol2parity(char *s) 1012 { 1013 l2parity = 0; 1014 return 1; 1015 } 1016 __setup("nol2par", nol2parity); 1017 1018 /* 1019 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1020 * it different ways. 1021 */ 1022 static inline void parity_protection_init(void) 1023 { 1024 switch (current_cpu_type()) { 1025 case CPU_24K: 1026 case CPU_34K: 1027 case CPU_74K: 1028 case CPU_1004K: 1029 { 1030 #define ERRCTL_PE 0x80000000 1031 #define ERRCTL_L2P 0x00800000 1032 unsigned long errctl; 1033 unsigned int l1parity_present, l2parity_present; 1034 1035 errctl = read_c0_ecc(); 1036 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1037 1038 /* probe L1 parity support */ 1039 write_c0_ecc(errctl | ERRCTL_PE); 1040 back_to_back_c0_hazard(); 1041 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1042 1043 /* probe L2 parity support */ 1044 write_c0_ecc(errctl|ERRCTL_L2P); 1045 back_to_back_c0_hazard(); 1046 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1047 1048 if (l1parity_present && l2parity_present) { 1049 if (l1parity) 1050 errctl |= ERRCTL_PE; 1051 if (l1parity ^ l2parity) 1052 errctl |= ERRCTL_L2P; 1053 } else if (l1parity_present) { 1054 if (l1parity) 1055 errctl |= ERRCTL_PE; 1056 } else if (l2parity_present) { 1057 if (l2parity) 1058 errctl |= ERRCTL_L2P; 1059 } else { 1060 /* No parity available */ 1061 } 1062 1063 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1064 1065 write_c0_ecc(errctl); 1066 back_to_back_c0_hazard(); 1067 errctl = read_c0_ecc(); 1068 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1069 1070 if (l1parity_present) 1071 printk(KERN_INFO "Cache parity protection %sabled\n", 1072 (errctl & ERRCTL_PE) ? "en" : "dis"); 1073 1074 if (l2parity_present) { 1075 if (l1parity_present && l1parity) 1076 errctl ^= ERRCTL_L2P; 1077 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1078 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1079 } 1080 } 1081 break; 1082 1083 case CPU_5KC: 1084 write_c0_ecc(0x80000000); 1085 back_to_back_c0_hazard(); 1086 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1087 printk(KERN_INFO "Cache parity protection %sabled\n", 1088 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1089 break; 1090 case CPU_20KC: 1091 case CPU_25KF: 1092 /* Clear the DE bit (bit 16) in the c0_status register. */ 1093 printk(KERN_INFO "Enable cache parity protection for " 1094 "MIPS 20KC/25KF CPUs.\n"); 1095 clear_c0_status(ST0_DE); 1096 break; 1097 default: 1098 break; 1099 } 1100 } 1101 1102 asmlinkage void cache_parity_error(void) 1103 { 1104 const int field = 2 * sizeof(unsigned long); 1105 unsigned int reg_val; 1106 1107 /* For the moment, report the problem and hang. */ 1108 printk("Cache error exception:\n"); 1109 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1110 reg_val = read_c0_cacheerr(); 1111 printk("c0_cacheerr == %08x\n", reg_val); 1112 1113 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1114 reg_val & (1<<30) ? "secondary" : "primary", 1115 reg_val & (1<<31) ? "data" : "insn"); 1116 printk("Error bits: %s%s%s%s%s%s%s\n", 1117 reg_val & (1<<29) ? "ED " : "", 1118 reg_val & (1<<28) ? "ET " : "", 1119 reg_val & (1<<26) ? "EE " : "", 1120 reg_val & (1<<25) ? "EB " : "", 1121 reg_val & (1<<24) ? "EI " : "", 1122 reg_val & (1<<23) ? "E1 " : "", 1123 reg_val & (1<<22) ? "E0 " : ""); 1124 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1125 1126 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1127 if (reg_val & (1<<22)) 1128 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1129 1130 if (reg_val & (1<<23)) 1131 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1132 #endif 1133 1134 panic("Can't handle the cache error!"); 1135 } 1136 1137 /* 1138 * SDBBP EJTAG debug exception handler. 1139 * We skip the instruction and return to the next instruction. 1140 */ 1141 void ejtag_exception_handler(struct pt_regs *regs) 1142 { 1143 const int field = 2 * sizeof(unsigned long); 1144 unsigned long depc, old_epc; 1145 unsigned int debug; 1146 1147 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1148 depc = read_c0_depc(); 1149 debug = read_c0_debug(); 1150 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1151 if (debug & 0x80000000) { 1152 /* 1153 * In branch delay slot. 1154 * We cheat a little bit here and use EPC to calculate the 1155 * debug return address (DEPC). EPC is restored after the 1156 * calculation. 1157 */ 1158 old_epc = regs->cp0_epc; 1159 regs->cp0_epc = depc; 1160 __compute_return_epc(regs); 1161 depc = regs->cp0_epc; 1162 regs->cp0_epc = old_epc; 1163 } else 1164 depc += 4; 1165 write_c0_depc(depc); 1166 1167 #if 0 1168 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1169 write_c0_debug(debug | 0x100); 1170 #endif 1171 } 1172 1173 /* 1174 * NMI exception handler. 1175 */ 1176 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1177 { 1178 bust_spinlocks(1); 1179 printk("NMI taken!!!!\n"); 1180 die("NMI", regs); 1181 } 1182 1183 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1184 1185 unsigned long ebase; 1186 unsigned long exception_handlers[32]; 1187 unsigned long vi_handlers[64]; 1188 1189 /* 1190 * As a side effect of the way this is implemented we're limited 1191 * to interrupt handlers in the address range from 1192 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1193 */ 1194 void *set_except_vector(int n, void *addr) 1195 { 1196 unsigned long handler = (unsigned long) addr; 1197 unsigned long old_handler = exception_handlers[n]; 1198 1199 exception_handlers[n] = handler; 1200 if (n == 0 && cpu_has_divec) { 1201 *(u32 *)(ebase + 0x200) = 0x08000000 | 1202 (0x03ffffff & (handler >> 2)); 1203 flush_icache_range(ebase + 0x200, ebase + 0x204); 1204 } 1205 return (void *)old_handler; 1206 } 1207 1208 static asmlinkage void do_default_vi(void) 1209 { 1210 show_regs(get_irq_regs()); 1211 panic("Caught unexpected vectored interrupt."); 1212 } 1213 1214 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1215 { 1216 unsigned long handler; 1217 unsigned long old_handler = vi_handlers[n]; 1218 int srssets = current_cpu_data.srsets; 1219 u32 *w; 1220 unsigned char *b; 1221 1222 if (!cpu_has_veic && !cpu_has_vint) 1223 BUG(); 1224 1225 if (addr == NULL) { 1226 handler = (unsigned long) do_default_vi; 1227 srs = 0; 1228 } else 1229 handler = (unsigned long) addr; 1230 vi_handlers[n] = (unsigned long) addr; 1231 1232 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1233 1234 if (srs >= srssets) 1235 panic("Shadow register set %d not supported", srs); 1236 1237 if (cpu_has_veic) { 1238 if (board_bind_eic_interrupt) 1239 board_bind_eic_interrupt(n, srs); 1240 } else if (cpu_has_vint) { 1241 /* SRSMap is only defined if shadow sets are implemented */ 1242 if (srssets > 1) 1243 change_c0_srsmap(0xf << n*4, srs << n*4); 1244 } 1245 1246 if (srs == 0) { 1247 /* 1248 * If no shadow set is selected then use the default handler 1249 * that does normal register saving and a standard interrupt exit 1250 */ 1251 1252 extern char except_vec_vi, except_vec_vi_lui; 1253 extern char except_vec_vi_ori, except_vec_vi_end; 1254 #ifdef CONFIG_MIPS_MT_SMTC 1255 /* 1256 * We need to provide the SMTC vectored interrupt handler 1257 * not only with the address of the handler, but with the 1258 * Status.IM bit to be masked before going there. 1259 */ 1260 extern char except_vec_vi_mori; 1261 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1262 #endif /* CONFIG_MIPS_MT_SMTC */ 1263 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1264 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1265 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1266 1267 if (handler_len > VECTORSPACING) { 1268 /* 1269 * Sigh... panicing won't help as the console 1270 * is probably not configured :( 1271 */ 1272 panic("VECTORSPACING too small"); 1273 } 1274 1275 memcpy(b, &except_vec_vi, handler_len); 1276 #ifdef CONFIG_MIPS_MT_SMTC 1277 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1278 1279 w = (u32 *)(b + mori_offset); 1280 *w = (*w & 0xffff0000) | (0x100 << n); 1281 #endif /* CONFIG_MIPS_MT_SMTC */ 1282 w = (u32 *)(b + lui_offset); 1283 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1284 w = (u32 *)(b + ori_offset); 1285 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1286 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1287 } 1288 else { 1289 /* 1290 * In other cases jump directly to the interrupt handler 1291 * 1292 * It is the handlers responsibility to save registers if required 1293 * (eg hi/lo) and return from the exception using "eret" 1294 */ 1295 w = (u32 *)b; 1296 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1297 *w = 0; 1298 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1299 } 1300 1301 return (void *)old_handler; 1302 } 1303 1304 void *set_vi_handler(int n, vi_handler_t addr) 1305 { 1306 return set_vi_srs_handler(n, addr, 0); 1307 } 1308 1309 /* 1310 * This is used by native signal handling 1311 */ 1312 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1313 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1314 1315 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1316 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1317 1318 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1319 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1320 1321 #ifdef CONFIG_SMP 1322 static int smp_save_fp_context(struct sigcontext __user *sc) 1323 { 1324 return raw_cpu_has_fpu 1325 ? _save_fp_context(sc) 1326 : fpu_emulator_save_context(sc); 1327 } 1328 1329 static int smp_restore_fp_context(struct sigcontext __user *sc) 1330 { 1331 return raw_cpu_has_fpu 1332 ? _restore_fp_context(sc) 1333 : fpu_emulator_restore_context(sc); 1334 } 1335 #endif 1336 1337 static inline void signal_init(void) 1338 { 1339 #ifdef CONFIG_SMP 1340 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1341 save_fp_context = smp_save_fp_context; 1342 restore_fp_context = smp_restore_fp_context; 1343 #else 1344 if (cpu_has_fpu) { 1345 save_fp_context = _save_fp_context; 1346 restore_fp_context = _restore_fp_context; 1347 } else { 1348 save_fp_context = fpu_emulator_save_context; 1349 restore_fp_context = fpu_emulator_restore_context; 1350 } 1351 #endif 1352 } 1353 1354 #ifdef CONFIG_MIPS32_COMPAT 1355 1356 /* 1357 * This is used by 32-bit signal stuff on the 64-bit kernel 1358 */ 1359 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1360 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1361 1362 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1363 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1364 1365 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1366 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1367 1368 static inline void signal32_init(void) 1369 { 1370 if (cpu_has_fpu) { 1371 save_fp_context32 = _save_fp_context32; 1372 restore_fp_context32 = _restore_fp_context32; 1373 } else { 1374 save_fp_context32 = fpu_emulator_save_context32; 1375 restore_fp_context32 = fpu_emulator_restore_context32; 1376 } 1377 } 1378 #endif 1379 1380 extern void cpu_cache_init(void); 1381 extern void tlb_init(void); 1382 extern void flush_tlb_handlers(void); 1383 1384 /* 1385 * Timer interrupt 1386 */ 1387 int cp0_compare_irq; 1388 1389 /* 1390 * Performance counter IRQ or -1 if shared with timer 1391 */ 1392 int cp0_perfcount_irq; 1393 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1394 1395 static int __cpuinitdata noulri; 1396 1397 static int __init ulri_disable(char *s) 1398 { 1399 pr_info("Disabling ulri\n"); 1400 noulri = 1; 1401 1402 return 1; 1403 } 1404 __setup("noulri", ulri_disable); 1405 1406 void __cpuinit per_cpu_trap_init(void) 1407 { 1408 unsigned int cpu = smp_processor_id(); 1409 unsigned int status_set = ST0_CU0; 1410 #ifdef CONFIG_MIPS_MT_SMTC 1411 int secondaryTC = 0; 1412 int bootTC = (cpu == 0); 1413 1414 /* 1415 * Only do per_cpu_trap_init() for first TC of Each VPE. 1416 * Note that this hack assumes that the SMTC init code 1417 * assigns TCs consecutively and in ascending order. 1418 */ 1419 1420 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1421 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1422 secondaryTC = 1; 1423 #endif /* CONFIG_MIPS_MT_SMTC */ 1424 1425 /* 1426 * Disable coprocessors and select 32-bit or 64-bit addressing 1427 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1428 * flag that some firmware may have left set and the TS bit (for 1429 * IP27). Set XX for ISA IV code to work. 1430 */ 1431 #ifdef CONFIG_64BIT 1432 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1433 #endif 1434 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1435 status_set |= ST0_XX; 1436 if (cpu_has_dsp) 1437 status_set |= ST0_MX; 1438 1439 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1440 status_set); 1441 1442 if (cpu_has_mips_r2) { 1443 unsigned int enable = 0x0000000f; 1444 1445 if (!noulri && cpu_has_userlocal) 1446 enable |= (1 << 29); 1447 1448 write_c0_hwrena(enable); 1449 } 1450 1451 #ifdef CONFIG_MIPS_MT_SMTC 1452 if (!secondaryTC) { 1453 #endif /* CONFIG_MIPS_MT_SMTC */ 1454 1455 if (cpu_has_veic || cpu_has_vint) { 1456 write_c0_ebase(ebase); 1457 /* Setting vector spacing enables EI/VI mode */ 1458 change_c0_intctl(0x3e0, VECTORSPACING); 1459 } 1460 if (cpu_has_divec) { 1461 if (cpu_has_mipsmt) { 1462 unsigned int vpflags = dvpe(); 1463 set_c0_cause(CAUSEF_IV); 1464 evpe(vpflags); 1465 } else 1466 set_c0_cause(CAUSEF_IV); 1467 } 1468 1469 /* 1470 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1471 * 1472 * o read IntCtl.IPTI to determine the timer interrupt 1473 * o read IntCtl.IPPCI to determine the performance counter interrupt 1474 */ 1475 if (cpu_has_mips_r2) { 1476 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1477 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1478 if (cp0_perfcount_irq == cp0_compare_irq) 1479 cp0_perfcount_irq = -1; 1480 } else { 1481 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1482 cp0_perfcount_irq = -1; 1483 } 1484 1485 #ifdef CONFIG_MIPS_MT_SMTC 1486 } 1487 #endif /* CONFIG_MIPS_MT_SMTC */ 1488 1489 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1490 TLBMISS_HANDLER_SETUP(); 1491 1492 atomic_inc(&init_mm.mm_count); 1493 current->active_mm = &init_mm; 1494 BUG_ON(current->mm); 1495 enter_lazy_tlb(&init_mm, current); 1496 1497 #ifdef CONFIG_MIPS_MT_SMTC 1498 if (bootTC) { 1499 #endif /* CONFIG_MIPS_MT_SMTC */ 1500 cpu_cache_init(); 1501 tlb_init(); 1502 #ifdef CONFIG_MIPS_MT_SMTC 1503 } else if (!secondaryTC) { 1504 /* 1505 * First TC in non-boot VPE must do subset of tlb_init() 1506 * for MMU countrol registers. 1507 */ 1508 write_c0_pagemask(PM_DEFAULT_MASK); 1509 write_c0_wired(0); 1510 } 1511 #endif /* CONFIG_MIPS_MT_SMTC */ 1512 } 1513 1514 /* Install CPU exception handler */ 1515 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1516 { 1517 memcpy((void *)(ebase + offset), addr, size); 1518 flush_icache_range(ebase + offset, ebase + offset + size); 1519 } 1520 1521 static char panic_null_cerr[] __cpuinitdata = 1522 "Trying to set NULL cache error exception handler"; 1523 1524 /* Install uncached CPU exception handler */ 1525 void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1526 unsigned long size) 1527 { 1528 #ifdef CONFIG_32BIT 1529 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1530 #endif 1531 #ifdef CONFIG_64BIT 1532 unsigned long uncached_ebase = TO_UNCAC(ebase); 1533 #endif 1534 1535 if (!addr) 1536 panic(panic_null_cerr); 1537 1538 memcpy((void *)(uncached_ebase + offset), addr, size); 1539 } 1540 1541 static int __initdata rdhwr_noopt; 1542 static int __init set_rdhwr_noopt(char *str) 1543 { 1544 rdhwr_noopt = 1; 1545 return 1; 1546 } 1547 1548 __setup("rdhwr_noopt", set_rdhwr_noopt); 1549 1550 void __init trap_init(void) 1551 { 1552 extern char except_vec3_generic, except_vec3_r4000; 1553 extern char except_vec4; 1554 unsigned long i; 1555 1556 #if defined(CONFIG_KGDB) 1557 if (kgdb_early_setup) 1558 return; /* Already done */ 1559 #endif 1560 1561 if (cpu_has_veic || cpu_has_vint) 1562 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1563 else 1564 ebase = CAC_BASE; 1565 1566 per_cpu_trap_init(); 1567 1568 /* 1569 * Copy the generic exception handlers to their final destination. 1570 * This will be overriden later as suitable for a particular 1571 * configuration. 1572 */ 1573 set_handler(0x180, &except_vec3_generic, 0x80); 1574 1575 /* 1576 * Setup default vectors 1577 */ 1578 for (i = 0; i <= 31; i++) 1579 set_except_vector(i, handle_reserved); 1580 1581 /* 1582 * Copy the EJTAG debug exception vector handler code to it's final 1583 * destination. 1584 */ 1585 if (cpu_has_ejtag && board_ejtag_handler_setup) 1586 board_ejtag_handler_setup(); 1587 1588 /* 1589 * Only some CPUs have the watch exceptions. 1590 */ 1591 if (cpu_has_watch) 1592 set_except_vector(23, handle_watch); 1593 1594 /* 1595 * Initialise interrupt handlers 1596 */ 1597 if (cpu_has_veic || cpu_has_vint) { 1598 int nvec = cpu_has_veic ? 64 : 8; 1599 for (i = 0; i < nvec; i++) 1600 set_vi_handler(i, NULL); 1601 } 1602 else if (cpu_has_divec) 1603 set_handler(0x200, &except_vec4, 0x8); 1604 1605 /* 1606 * Some CPUs can enable/disable for cache parity detection, but does 1607 * it different ways. 1608 */ 1609 parity_protection_init(); 1610 1611 /* 1612 * The Data Bus Errors / Instruction Bus Errors are signaled 1613 * by external hardware. Therefore these two exceptions 1614 * may have board specific handlers. 1615 */ 1616 if (board_be_init) 1617 board_be_init(); 1618 1619 set_except_vector(0, handle_int); 1620 set_except_vector(1, handle_tlbm); 1621 set_except_vector(2, handle_tlbl); 1622 set_except_vector(3, handle_tlbs); 1623 1624 set_except_vector(4, handle_adel); 1625 set_except_vector(5, handle_ades); 1626 1627 set_except_vector(6, handle_ibe); 1628 set_except_vector(7, handle_dbe); 1629 1630 set_except_vector(8, handle_sys); 1631 set_except_vector(9, handle_bp); 1632 set_except_vector(10, rdhwr_noopt ? handle_ri : 1633 (cpu_has_vtag_icache ? 1634 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1635 set_except_vector(11, handle_cpu); 1636 set_except_vector(12, handle_ov); 1637 set_except_vector(13, handle_tr); 1638 1639 if (current_cpu_type() == CPU_R6000 || 1640 current_cpu_type() == CPU_R6000A) { 1641 /* 1642 * The R6000 is the only R-series CPU that features a machine 1643 * check exception (similar to the R4000 cache error) and 1644 * unaligned ldc1/sdc1 exception. The handlers have not been 1645 * written yet. Well, anyway there is no R6000 machine on the 1646 * current list of targets for Linux/MIPS. 1647 * (Duh, crap, there is someone with a triple R6k machine) 1648 */ 1649 //set_except_vector(14, handle_mc); 1650 //set_except_vector(15, handle_ndc); 1651 } 1652 1653 1654 if (board_nmi_handler_setup) 1655 board_nmi_handler_setup(); 1656 1657 if (cpu_has_fpu && !cpu_has_nofpuex) 1658 set_except_vector(15, handle_fpe); 1659 1660 set_except_vector(22, handle_mdmx); 1661 1662 if (cpu_has_mcheck) 1663 set_except_vector(24, handle_mcheck); 1664 1665 if (cpu_has_mipsmt) 1666 set_except_vector(25, handle_mt); 1667 1668 set_except_vector(26, handle_dsp); 1669 1670 if (cpu_has_vce) 1671 /* Special exception: R4[04]00 uses also the divec space. */ 1672 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1673 else if (cpu_has_4kex) 1674 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1675 else 1676 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1677 1678 signal_init(); 1679 #ifdef CONFIG_MIPS32_COMPAT 1680 signal32_init(); 1681 #endif 1682 1683 flush_icache_range(ebase, ebase + 0x400); 1684 flush_tlb_handlers(); 1685 } 1686