1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/init.h> 15 #include <linux/mm.h> 16 #include <linux/module.h> 17 #include <linux/sched.h> 18 #include <linux/smp.h> 19 #include <linux/smp_lock.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/bootmem.h> 23 #include <linux/interrupt.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/branch.h> 27 #include <asm/break.h> 28 #include <asm/cpu.h> 29 #include <asm/dsp.h> 30 #include <asm/fpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/module.h> 34 #include <asm/pgtable.h> 35 #include <asm/ptrace.h> 36 #include <asm/sections.h> 37 #include <asm/system.h> 38 #include <asm/tlbdebug.h> 39 #include <asm/traps.h> 40 #include <asm/uaccess.h> 41 #include <asm/mmu_context.h> 42 #include <asm/watch.h> 43 #include <asm/types.h> 44 #include <asm/stacktrace.h> 45 46 extern asmlinkage void handle_int(void); 47 extern asmlinkage void handle_tlbm(void); 48 extern asmlinkage void handle_tlbl(void); 49 extern asmlinkage void handle_tlbs(void); 50 extern asmlinkage void handle_adel(void); 51 extern asmlinkage void handle_ades(void); 52 extern asmlinkage void handle_ibe(void); 53 extern asmlinkage void handle_dbe(void); 54 extern asmlinkage void handle_sys(void); 55 extern asmlinkage void handle_bp(void); 56 extern asmlinkage void handle_ri(void); 57 extern asmlinkage void handle_ri_rdhwr_vivt(void); 58 extern asmlinkage void handle_ri_rdhwr(void); 59 extern asmlinkage void handle_cpu(void); 60 extern asmlinkage void handle_ov(void); 61 extern asmlinkage void handle_tr(void); 62 extern asmlinkage void handle_fpe(void); 63 extern asmlinkage void handle_mdmx(void); 64 extern asmlinkage void handle_watch(void); 65 extern asmlinkage void handle_mt(void); 66 extern asmlinkage void handle_dsp(void); 67 extern asmlinkage void handle_mcheck(void); 68 extern asmlinkage void handle_reserved(void); 69 70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 71 struct mips_fpu_struct *ctx, int has_fpu); 72 73 void (*board_be_init)(void); 74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 75 void (*board_nmi_handler_setup)(void); 76 void (*board_ejtag_handler_setup)(void); 77 void (*board_bind_eic_interrupt)(int irq, int regset); 78 79 80 static void show_raw_backtrace(unsigned long reg29) 81 { 82 unsigned long *sp = (unsigned long *)reg29; 83 unsigned long addr; 84 85 printk("Call Trace:"); 86 #ifdef CONFIG_KALLSYMS 87 printk("\n"); 88 #endif 89 while (!kstack_end(sp)) { 90 addr = *sp++; 91 if (__kernel_text_address(addr)) 92 print_ip_sym(addr); 93 } 94 printk("\n"); 95 } 96 97 #ifdef CONFIG_KALLSYMS 98 int raw_show_trace; 99 static int __init set_raw_show_trace(char *str) 100 { 101 raw_show_trace = 1; 102 return 1; 103 } 104 __setup("raw_show_trace", set_raw_show_trace); 105 #endif 106 107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs) 108 { 109 unsigned long sp = regs->regs[29]; 110 unsigned long ra = regs->regs[31]; 111 unsigned long pc = regs->cp0_epc; 112 113 if (raw_show_trace || !__kernel_text_address(pc)) { 114 show_raw_backtrace(sp); 115 return; 116 } 117 printk("Call Trace:\n"); 118 do { 119 print_ip_sym(pc); 120 pc = unwind_stack(task, &sp, pc, &ra); 121 } while (pc); 122 printk("\n"); 123 } 124 125 /* 126 * This routine abuses get_user()/put_user() to reference pointers 127 * with at least a bit of error checking ... 128 */ 129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) 130 { 131 const int field = 2 * sizeof(unsigned long); 132 long stackdata; 133 int i; 134 unsigned long *sp = (unsigned long *)regs->regs[29]; 135 136 printk("Stack :"); 137 i = 0; 138 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 139 if (i && ((i % (64 / field)) == 0)) 140 printk("\n "); 141 if (i > 39) { 142 printk(" ..."); 143 break; 144 } 145 146 if (__get_user(stackdata, sp++)) { 147 printk(" (Bad stack address)"); 148 break; 149 } 150 151 printk(" %0*lx", field, stackdata); 152 i++; 153 } 154 printk("\n"); 155 show_backtrace(task, regs); 156 } 157 158 void show_stack(struct task_struct *task, unsigned long *sp) 159 { 160 struct pt_regs regs; 161 if (sp) { 162 regs.regs[29] = (unsigned long)sp; 163 regs.regs[31] = 0; 164 regs.cp0_epc = 0; 165 } else { 166 if (task && task != current) { 167 regs.regs[29] = task->thread.reg29; 168 regs.regs[31] = 0; 169 regs.cp0_epc = task->thread.reg31; 170 } else { 171 prepare_frametrace(®s); 172 } 173 } 174 show_stacktrace(task, ®s); 175 } 176 177 /* 178 * The architecture-independent dump_stack generator 179 */ 180 void dump_stack(void) 181 { 182 struct pt_regs regs; 183 184 prepare_frametrace(®s); 185 show_backtrace(current, ®s); 186 } 187 188 EXPORT_SYMBOL(dump_stack); 189 190 void show_code(unsigned int *pc) 191 { 192 long i; 193 194 printk("\nCode:"); 195 196 for(i = -3 ; i < 6 ; i++) { 197 unsigned int insn; 198 if (__get_user(insn, pc + i)) { 199 printk(" (Bad address in epc)\n"); 200 break; 201 } 202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 203 } 204 } 205 206 void show_regs(struct pt_regs *regs) 207 { 208 const int field = 2 * sizeof(unsigned long); 209 unsigned int cause = regs->cp0_cause; 210 int i; 211 212 printk("Cpu %d\n", smp_processor_id()); 213 214 /* 215 * Saved main processor registers 216 */ 217 for (i = 0; i < 32; ) { 218 if ((i % 4) == 0) 219 printk("$%2d :", i); 220 if (i == 0) 221 printk(" %0*lx", field, 0UL); 222 else if (i == 26 || i == 27) 223 printk(" %*s", field, ""); 224 else 225 printk(" %0*lx", field, regs->regs[i]); 226 227 i++; 228 if ((i % 4) == 0) 229 printk("\n"); 230 } 231 232 printk("Hi : %0*lx\n", field, regs->hi); 233 printk("Lo : %0*lx\n", field, regs->lo); 234 235 /* 236 * Saved cp0 registers 237 */ 238 printk("epc : %0*lx ", field, regs->cp0_epc); 239 print_symbol("%s ", regs->cp0_epc); 240 printk(" %s\n", print_tainted()); 241 printk("ra : %0*lx ", field, regs->regs[31]); 242 print_symbol("%s\n", regs->regs[31]); 243 244 printk("Status: %08x ", (uint32_t) regs->cp0_status); 245 246 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 247 if (regs->cp0_status & ST0_KUO) 248 printk("KUo "); 249 if (regs->cp0_status & ST0_IEO) 250 printk("IEo "); 251 if (regs->cp0_status & ST0_KUP) 252 printk("KUp "); 253 if (regs->cp0_status & ST0_IEP) 254 printk("IEp "); 255 if (regs->cp0_status & ST0_KUC) 256 printk("KUc "); 257 if (regs->cp0_status & ST0_IEC) 258 printk("IEc "); 259 } else { 260 if (regs->cp0_status & ST0_KX) 261 printk("KX "); 262 if (regs->cp0_status & ST0_SX) 263 printk("SX "); 264 if (regs->cp0_status & ST0_UX) 265 printk("UX "); 266 switch (regs->cp0_status & ST0_KSU) { 267 case KSU_USER: 268 printk("USER "); 269 break; 270 case KSU_SUPERVISOR: 271 printk("SUPERVISOR "); 272 break; 273 case KSU_KERNEL: 274 printk("KERNEL "); 275 break; 276 default: 277 printk("BAD_MODE "); 278 break; 279 } 280 if (regs->cp0_status & ST0_ERL) 281 printk("ERL "); 282 if (regs->cp0_status & ST0_EXL) 283 printk("EXL "); 284 if (regs->cp0_status & ST0_IE) 285 printk("IE "); 286 } 287 printk("\n"); 288 289 printk("Cause : %08x\n", cause); 290 291 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 292 if (1 <= cause && cause <= 5) 293 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 294 295 printk("PrId : %08x\n", read_c0_prid()); 296 } 297 298 void show_registers(struct pt_regs *regs) 299 { 300 show_regs(regs); 301 print_modules(); 302 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 303 current->comm, current->pid, current_thread_info(), current); 304 show_stacktrace(current, regs); 305 show_code((unsigned int *) regs->cp0_epc); 306 printk("\n"); 307 } 308 309 static DEFINE_SPINLOCK(die_lock); 310 311 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) 312 { 313 static int die_counter; 314 #ifdef CONFIG_MIPS_MT_SMTC 315 unsigned long dvpret = dvpe(); 316 #endif /* CONFIG_MIPS_MT_SMTC */ 317 318 console_verbose(); 319 spin_lock_irq(&die_lock); 320 bust_spinlocks(1); 321 #ifdef CONFIG_MIPS_MT_SMTC 322 mips_mt_regdump(dvpret); 323 #endif /* CONFIG_MIPS_MT_SMTC */ 324 printk("%s[#%d]:\n", str, ++die_counter); 325 show_registers(regs); 326 spin_unlock_irq(&die_lock); 327 328 if (in_interrupt()) 329 panic("Fatal exception in interrupt"); 330 331 if (panic_on_oops) { 332 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 333 ssleep(5); 334 panic("Fatal exception"); 335 } 336 337 do_exit(SIGSEGV); 338 } 339 340 extern const struct exception_table_entry __start___dbe_table[]; 341 extern const struct exception_table_entry __stop___dbe_table[]; 342 343 void __declare_dbe_table(void) 344 { 345 __asm__ __volatile__( 346 ".section\t__dbe_table,\"a\"\n\t" 347 ".previous" 348 ); 349 } 350 351 /* Given an address, look for it in the exception tables. */ 352 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 353 { 354 const struct exception_table_entry *e; 355 356 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 357 if (!e) 358 e = search_module_dbetables(addr); 359 return e; 360 } 361 362 asmlinkage void do_be(struct pt_regs *regs) 363 { 364 const int field = 2 * sizeof(unsigned long); 365 const struct exception_table_entry *fixup = NULL; 366 int data = regs->cp0_cause & 4; 367 int action = MIPS_BE_FATAL; 368 369 /* XXX For now. Fixme, this searches the wrong table ... */ 370 if (data && !user_mode(regs)) 371 fixup = search_dbe_tables(exception_epc(regs)); 372 373 if (fixup) 374 action = MIPS_BE_FIXUP; 375 376 if (board_be_handler) 377 action = board_be_handler(regs, fixup != 0); 378 379 switch (action) { 380 case MIPS_BE_DISCARD: 381 return; 382 case MIPS_BE_FIXUP: 383 if (fixup) { 384 regs->cp0_epc = fixup->nextinsn; 385 return; 386 } 387 break; 388 default: 389 break; 390 } 391 392 /* 393 * Assume it would be too dangerous to continue ... 394 */ 395 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 396 data ? "Data" : "Instruction", 397 field, regs->cp0_epc, field, regs->regs[31]); 398 die_if_kernel("Oops", regs); 399 force_sig(SIGBUS, current); 400 } 401 402 /* 403 * ll/sc emulation 404 */ 405 406 #define OPCODE 0xfc000000 407 #define BASE 0x03e00000 408 #define RT 0x001f0000 409 #define OFFSET 0x0000ffff 410 #define LL 0xc0000000 411 #define SC 0xe0000000 412 #define SPEC3 0x7c000000 413 #define RD 0x0000f800 414 #define FUNC 0x0000003f 415 #define RDHWR 0x0000003b 416 417 /* 418 * The ll_bit is cleared by r*_switch.S 419 */ 420 421 unsigned long ll_bit; 422 423 static struct task_struct *ll_task = NULL; 424 425 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 426 { 427 unsigned long value, __user *vaddr; 428 long offset; 429 int signal = 0; 430 431 /* 432 * analyse the ll instruction that just caused a ri exception 433 * and put the referenced address to addr. 434 */ 435 436 /* sign extend offset */ 437 offset = opcode & OFFSET; 438 offset <<= 16; 439 offset >>= 16; 440 441 vaddr = (unsigned long __user *) 442 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 443 444 if ((unsigned long)vaddr & 3) { 445 signal = SIGBUS; 446 goto sig; 447 } 448 if (get_user(value, vaddr)) { 449 signal = SIGSEGV; 450 goto sig; 451 } 452 453 preempt_disable(); 454 455 if (ll_task == NULL || ll_task == current) { 456 ll_bit = 1; 457 } else { 458 ll_bit = 0; 459 } 460 ll_task = current; 461 462 preempt_enable(); 463 464 compute_return_epc(regs); 465 466 regs->regs[(opcode & RT) >> 16] = value; 467 468 return; 469 470 sig: 471 force_sig(signal, current); 472 } 473 474 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 475 { 476 unsigned long __user *vaddr; 477 unsigned long reg; 478 long offset; 479 int signal = 0; 480 481 /* 482 * analyse the sc instruction that just caused a ri exception 483 * and put the referenced address to addr. 484 */ 485 486 /* sign extend offset */ 487 offset = opcode & OFFSET; 488 offset <<= 16; 489 offset >>= 16; 490 491 vaddr = (unsigned long __user *) 492 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 493 reg = (opcode & RT) >> 16; 494 495 if ((unsigned long)vaddr & 3) { 496 signal = SIGBUS; 497 goto sig; 498 } 499 500 preempt_disable(); 501 502 if (ll_bit == 0 || ll_task != current) { 503 compute_return_epc(regs); 504 regs->regs[reg] = 0; 505 preempt_enable(); 506 return; 507 } 508 509 preempt_enable(); 510 511 if (put_user(regs->regs[reg], vaddr)) { 512 signal = SIGSEGV; 513 goto sig; 514 } 515 516 compute_return_epc(regs); 517 regs->regs[reg] = 1; 518 519 return; 520 521 sig: 522 force_sig(signal, current); 523 } 524 525 /* 526 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 527 * opcodes are supposed to result in coprocessor unusable exceptions if 528 * executed on ll/sc-less processors. That's the theory. In practice a 529 * few processors such as NEC's VR4100 throw reserved instruction exceptions 530 * instead, so we're doing the emulation thing in both exception handlers. 531 */ 532 static inline int simulate_llsc(struct pt_regs *regs) 533 { 534 unsigned int opcode; 535 536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 537 goto out_sigsegv; 538 539 if ((opcode & OPCODE) == LL) { 540 simulate_ll(regs, opcode); 541 return 0; 542 } 543 if ((opcode & OPCODE) == SC) { 544 simulate_sc(regs, opcode); 545 return 0; 546 } 547 548 return -EFAULT; /* Strange things going on ... */ 549 550 out_sigsegv: 551 force_sig(SIGSEGV, current); 552 return -EFAULT; 553 } 554 555 /* 556 * Simulate trapping 'rdhwr' instructions to provide user accessible 557 * registers not implemented in hardware. The only current use of this 558 * is the thread area pointer. 559 */ 560 static inline int simulate_rdhwr(struct pt_regs *regs) 561 { 562 struct thread_info *ti = task_thread_info(current); 563 unsigned int opcode; 564 565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 566 goto out_sigsegv; 567 568 if (unlikely(compute_return_epc(regs))) 569 return -EFAULT; 570 571 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 572 int rd = (opcode & RD) >> 11; 573 int rt = (opcode & RT) >> 16; 574 switch (rd) { 575 case 29: 576 regs->regs[rt] = ti->tp_value; 577 return 0; 578 default: 579 return -EFAULT; 580 } 581 } 582 583 /* Not ours. */ 584 return -EFAULT; 585 586 out_sigsegv: 587 force_sig(SIGSEGV, current); 588 return -EFAULT; 589 } 590 591 asmlinkage void do_ov(struct pt_regs *regs) 592 { 593 siginfo_t info; 594 595 die_if_kernel("Integer overflow", regs); 596 597 info.si_code = FPE_INTOVF; 598 info.si_signo = SIGFPE; 599 info.si_errno = 0; 600 info.si_addr = (void __user *) regs->cp0_epc; 601 force_sig_info(SIGFPE, &info, current); 602 } 603 604 /* 605 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 606 */ 607 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 608 { 609 die_if_kernel("FP exception in kernel code", regs); 610 611 if (fcr31 & FPU_CSR_UNI_X) { 612 int sig; 613 614 preempt_disable(); 615 616 #ifdef CONFIG_PREEMPT 617 if (!is_fpu_owner()) { 618 /* We might lose fpu before disabling preempt... */ 619 own_fpu(); 620 BUG_ON(!used_math()); 621 restore_fp(current); 622 } 623 #endif 624 /* 625 * Unimplemented operation exception. If we've got the full 626 * software emulator on-board, let's use it... 627 * 628 * Force FPU to dump state into task/thread context. We're 629 * moving a lot of data here for what is probably a single 630 * instruction, but the alternative is to pre-decode the FP 631 * register operands before invoking the emulator, which seems 632 * a bit extreme for what should be an infrequent event. 633 */ 634 save_fp(current); 635 /* Ensure 'resume' not overwrite saved fp context again. */ 636 lose_fpu(); 637 638 preempt_enable(); 639 640 /* Run the emulator */ 641 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); 642 643 preempt_disable(); 644 645 own_fpu(); /* Using the FPU again. */ 646 /* 647 * We can't allow the emulated instruction to leave any of 648 * the cause bit set in $fcr31. 649 */ 650 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 651 652 /* Restore the hardware register state */ 653 restore_fp(current); 654 655 preempt_enable(); 656 657 /* If something went wrong, signal */ 658 if (sig) 659 force_sig(sig, current); 660 661 return; 662 } 663 664 force_sig(SIGFPE, current); 665 } 666 667 asmlinkage void do_bp(struct pt_regs *regs) 668 { 669 unsigned int opcode, bcode; 670 siginfo_t info; 671 672 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 673 goto out_sigsegv; 674 675 /* 676 * There is the ancient bug in the MIPS assemblers that the break 677 * code starts left to bit 16 instead to bit 6 in the opcode. 678 * Gas is bug-compatible, but not always, grrr... 679 * We handle both cases with a simple heuristics. --macro 680 */ 681 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 682 if (bcode < (1 << 10)) 683 bcode <<= 10; 684 685 /* 686 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 687 * insns, even for break codes that indicate arithmetic failures. 688 * Weird ...) 689 * But should we continue the brokenness??? --macro 690 */ 691 switch (bcode) { 692 case BRK_OVERFLOW << 10: 693 case BRK_DIVZERO << 10: 694 die_if_kernel("Break instruction in kernel code", regs); 695 if (bcode == (BRK_DIVZERO << 10)) 696 info.si_code = FPE_INTDIV; 697 else 698 info.si_code = FPE_INTOVF; 699 info.si_signo = SIGFPE; 700 info.si_errno = 0; 701 info.si_addr = (void __user *) regs->cp0_epc; 702 force_sig_info(SIGFPE, &info, current); 703 break; 704 case BRK_BUG: 705 die("Kernel bug detected", regs); 706 break; 707 default: 708 die_if_kernel("Break instruction in kernel code", regs); 709 force_sig(SIGTRAP, current); 710 } 711 712 out_sigsegv: 713 force_sig(SIGSEGV, current); 714 } 715 716 asmlinkage void do_tr(struct pt_regs *regs) 717 { 718 unsigned int opcode, tcode = 0; 719 siginfo_t info; 720 721 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 722 goto out_sigsegv; 723 724 /* Immediate versions don't provide a code. */ 725 if (!(opcode & OPCODE)) 726 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 727 728 /* 729 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 730 * insns, even for trap codes that indicate arithmetic failures. 731 * Weird ...) 732 * But should we continue the brokenness??? --macro 733 */ 734 switch (tcode) { 735 case BRK_OVERFLOW: 736 case BRK_DIVZERO: 737 die_if_kernel("Trap instruction in kernel code", regs); 738 if (tcode == BRK_DIVZERO) 739 info.si_code = FPE_INTDIV; 740 else 741 info.si_code = FPE_INTOVF; 742 info.si_signo = SIGFPE; 743 info.si_errno = 0; 744 info.si_addr = (void __user *) regs->cp0_epc; 745 force_sig_info(SIGFPE, &info, current); 746 break; 747 case BRK_BUG: 748 die("Kernel bug detected", regs); 749 break; 750 default: 751 die_if_kernel("Trap instruction in kernel code", regs); 752 force_sig(SIGTRAP, current); 753 } 754 755 out_sigsegv: 756 force_sig(SIGSEGV, current); 757 } 758 759 asmlinkage void do_ri(struct pt_regs *regs) 760 { 761 die_if_kernel("Reserved instruction in kernel code", regs); 762 763 if (!cpu_has_llsc) 764 if (!simulate_llsc(regs)) 765 return; 766 767 if (!simulate_rdhwr(regs)) 768 return; 769 770 force_sig(SIGILL, current); 771 } 772 773 asmlinkage void do_cpu(struct pt_regs *regs) 774 { 775 unsigned int cpid; 776 777 die_if_kernel("do_cpu invoked from kernel context!", regs); 778 779 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 780 781 switch (cpid) { 782 case 0: 783 if (!cpu_has_llsc) 784 if (!simulate_llsc(regs)) 785 return; 786 787 if (!simulate_rdhwr(regs)) 788 return; 789 790 break; 791 792 case 1: 793 preempt_disable(); 794 795 own_fpu(); 796 if (used_math()) { /* Using the FPU again. */ 797 restore_fp(current); 798 } else { /* First time FPU user. */ 799 init_fpu(); 800 set_used_math(); 801 } 802 803 if (cpu_has_fpu) { 804 preempt_enable(); 805 } else { 806 int sig; 807 preempt_enable(); 808 sig = fpu_emulator_cop1Handler(regs, 809 ¤t->thread.fpu, 0); 810 if (sig) 811 force_sig(sig, current); 812 #ifdef CONFIG_MIPS_MT_FPAFF 813 else { 814 /* 815 * MIPS MT processors may have fewer FPU contexts 816 * than CPU threads. If we've emulated more than 817 * some threshold number of instructions, force 818 * migration to a "CPU" that has FP support. 819 */ 820 if(mt_fpemul_threshold > 0 821 && ((current->thread.emulated_fp++ 822 > mt_fpemul_threshold))) { 823 /* 824 * If there's no FPU present, or if the 825 * application has already restricted 826 * the allowed set to exclude any CPUs 827 * with FPUs, we'll skip the procedure. 828 */ 829 if (cpus_intersects(current->cpus_allowed, 830 mt_fpu_cpumask)) { 831 cpumask_t tmask; 832 833 cpus_and(tmask, 834 current->thread.user_cpus_allowed, 835 mt_fpu_cpumask); 836 set_cpus_allowed(current, tmask); 837 current->thread.mflags |= MF_FPUBOUND; 838 } 839 } 840 } 841 #endif /* CONFIG_MIPS_MT_FPAFF */ 842 } 843 844 return; 845 846 case 2: 847 case 3: 848 die_if_kernel("do_cpu invoked from kernel context!", regs); 849 break; 850 } 851 852 force_sig(SIGILL, current); 853 } 854 855 asmlinkage void do_mdmx(struct pt_regs *regs) 856 { 857 force_sig(SIGILL, current); 858 } 859 860 asmlinkage void do_watch(struct pt_regs *regs) 861 { 862 /* 863 * We use the watch exception where available to detect stack 864 * overflows. 865 */ 866 dump_tlb_all(); 867 show_regs(regs); 868 panic("Caught WATCH exception - probably caused by stack overflow."); 869 } 870 871 asmlinkage void do_mcheck(struct pt_regs *regs) 872 { 873 const int field = 2 * sizeof(unsigned long); 874 int multi_match = regs->cp0_status & ST0_TS; 875 876 show_regs(regs); 877 878 if (multi_match) { 879 printk("Index : %0x\n", read_c0_index()); 880 printk("Pagemask: %0x\n", read_c0_pagemask()); 881 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 882 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 883 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 884 printk("\n"); 885 dump_tlb_all(); 886 } 887 888 show_code((unsigned int *) regs->cp0_epc); 889 890 /* 891 * Some chips may have other causes of machine check (e.g. SB1 892 * graduation timer) 893 */ 894 panic("Caught Machine Check exception - %scaused by multiple " 895 "matching entries in the TLB.", 896 (multi_match) ? "" : "not "); 897 } 898 899 asmlinkage void do_mt(struct pt_regs *regs) 900 { 901 int subcode; 902 903 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 904 >> VPECONTROL_EXCPT_SHIFT; 905 switch (subcode) { 906 case 0: 907 printk(KERN_DEBUG "Thread Underflow\n"); 908 break; 909 case 1: 910 printk(KERN_DEBUG "Thread Overflow\n"); 911 break; 912 case 2: 913 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 914 break; 915 case 3: 916 printk(KERN_DEBUG "Gating Storage Exception\n"); 917 break; 918 case 4: 919 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 920 break; 921 case 5: 922 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 923 break; 924 default: 925 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 926 subcode); 927 break; 928 } 929 die_if_kernel("MIPS MT Thread exception in kernel", regs); 930 931 force_sig(SIGILL, current); 932 } 933 934 935 asmlinkage void do_dsp(struct pt_regs *regs) 936 { 937 if (cpu_has_dsp) 938 panic("Unexpected DSP exception\n"); 939 940 force_sig(SIGILL, current); 941 } 942 943 asmlinkage void do_reserved(struct pt_regs *regs) 944 { 945 /* 946 * Game over - no way to handle this if it ever occurs. Most probably 947 * caused by a new unknown cpu type or after another deadly 948 * hard/software error. 949 */ 950 show_regs(regs); 951 panic("Caught reserved exception %ld - should not happen.", 952 (regs->cp0_cause & 0x7f) >> 2); 953 } 954 955 asmlinkage void do_default_vi(struct pt_regs *regs) 956 { 957 show_regs(regs); 958 panic("Caught unexpected vectored interrupt."); 959 } 960 961 /* 962 * Some MIPS CPUs can enable/disable for cache parity detection, but do 963 * it different ways. 964 */ 965 static inline void parity_protection_init(void) 966 { 967 switch (current_cpu_data.cputype) { 968 case CPU_24K: 969 case CPU_34K: 970 case CPU_5KC: 971 write_c0_ecc(0x80000000); 972 back_to_back_c0_hazard(); 973 /* Set the PE bit (bit 31) in the c0_errctl register. */ 974 printk(KERN_INFO "Cache parity protection %sabled\n", 975 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 976 break; 977 case CPU_20KC: 978 case CPU_25KF: 979 /* Clear the DE bit (bit 16) in the c0_status register. */ 980 printk(KERN_INFO "Enable cache parity protection for " 981 "MIPS 20KC/25KF CPUs.\n"); 982 clear_c0_status(ST0_DE); 983 break; 984 default: 985 break; 986 } 987 } 988 989 asmlinkage void cache_parity_error(void) 990 { 991 const int field = 2 * sizeof(unsigned long); 992 unsigned int reg_val; 993 994 /* For the moment, report the problem and hang. */ 995 printk("Cache error exception:\n"); 996 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 997 reg_val = read_c0_cacheerr(); 998 printk("c0_cacheerr == %08x\n", reg_val); 999 1000 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1001 reg_val & (1<<30) ? "secondary" : "primary", 1002 reg_val & (1<<31) ? "data" : "insn"); 1003 printk("Error bits: %s%s%s%s%s%s%s\n", 1004 reg_val & (1<<29) ? "ED " : "", 1005 reg_val & (1<<28) ? "ET " : "", 1006 reg_val & (1<<26) ? "EE " : "", 1007 reg_val & (1<<25) ? "EB " : "", 1008 reg_val & (1<<24) ? "EI " : "", 1009 reg_val & (1<<23) ? "E1 " : "", 1010 reg_val & (1<<22) ? "E0 " : ""); 1011 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1012 1013 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1014 if (reg_val & (1<<22)) 1015 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1016 1017 if (reg_val & (1<<23)) 1018 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1019 #endif 1020 1021 panic("Can't handle the cache error!"); 1022 } 1023 1024 /* 1025 * SDBBP EJTAG debug exception handler. 1026 * We skip the instruction and return to the next instruction. 1027 */ 1028 void ejtag_exception_handler(struct pt_regs *regs) 1029 { 1030 const int field = 2 * sizeof(unsigned long); 1031 unsigned long depc, old_epc; 1032 unsigned int debug; 1033 1034 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1035 depc = read_c0_depc(); 1036 debug = read_c0_debug(); 1037 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1038 if (debug & 0x80000000) { 1039 /* 1040 * In branch delay slot. 1041 * We cheat a little bit here and use EPC to calculate the 1042 * debug return address (DEPC). EPC is restored after the 1043 * calculation. 1044 */ 1045 old_epc = regs->cp0_epc; 1046 regs->cp0_epc = depc; 1047 __compute_return_epc(regs); 1048 depc = regs->cp0_epc; 1049 regs->cp0_epc = old_epc; 1050 } else 1051 depc += 4; 1052 write_c0_depc(depc); 1053 1054 #if 0 1055 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1056 write_c0_debug(debug | 0x100); 1057 #endif 1058 } 1059 1060 /* 1061 * NMI exception handler. 1062 */ 1063 void nmi_exception_handler(struct pt_regs *regs) 1064 { 1065 #ifdef CONFIG_MIPS_MT_SMTC 1066 unsigned long dvpret = dvpe(); 1067 bust_spinlocks(1); 1068 printk("NMI taken!!!!\n"); 1069 mips_mt_regdump(dvpret); 1070 #else 1071 bust_spinlocks(1); 1072 printk("NMI taken!!!!\n"); 1073 #endif /* CONFIG_MIPS_MT_SMTC */ 1074 die("NMI", regs); 1075 while(1) ; 1076 } 1077 1078 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1079 1080 unsigned long ebase; 1081 unsigned long exception_handlers[32]; 1082 unsigned long vi_handlers[64]; 1083 1084 /* 1085 * As a side effect of the way this is implemented we're limited 1086 * to interrupt handlers in the address range from 1087 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1088 */ 1089 void *set_except_vector(int n, void *addr) 1090 { 1091 unsigned long handler = (unsigned long) addr; 1092 unsigned long old_handler = exception_handlers[n]; 1093 1094 exception_handlers[n] = handler; 1095 if (n == 0 && cpu_has_divec) { 1096 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1097 (0x03ffffff & (handler >> 2)); 1098 flush_icache_range(ebase + 0x200, ebase + 0x204); 1099 } 1100 return (void *)old_handler; 1101 } 1102 1103 #ifdef CONFIG_CPU_MIPSR2_SRS 1104 /* 1105 * MIPSR2 shadow register set allocation 1106 * FIXME: SMP... 1107 */ 1108 1109 static struct shadow_registers { 1110 /* 1111 * Number of shadow register sets supported 1112 */ 1113 unsigned long sr_supported; 1114 /* 1115 * Bitmap of allocated shadow registers 1116 */ 1117 unsigned long sr_allocated; 1118 } shadow_registers; 1119 1120 static void mips_srs_init(void) 1121 { 1122 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1123 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1124 shadow_registers.sr_supported); 1125 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1126 } 1127 1128 int mips_srs_max(void) 1129 { 1130 return shadow_registers.sr_supported; 1131 } 1132 1133 int mips_srs_alloc(void) 1134 { 1135 struct shadow_registers *sr = &shadow_registers; 1136 int set; 1137 1138 again: 1139 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1140 if (set >= sr->sr_supported) 1141 return -1; 1142 1143 if (test_and_set_bit(set, &sr->sr_allocated)) 1144 goto again; 1145 1146 return set; 1147 } 1148 1149 void mips_srs_free(int set) 1150 { 1151 struct shadow_registers *sr = &shadow_registers; 1152 1153 clear_bit(set, &sr->sr_allocated); 1154 } 1155 1156 static void *set_vi_srs_handler(int n, void *addr, int srs) 1157 { 1158 unsigned long handler; 1159 unsigned long old_handler = vi_handlers[n]; 1160 u32 *w; 1161 unsigned char *b; 1162 1163 if (!cpu_has_veic && !cpu_has_vint) 1164 BUG(); 1165 1166 if (addr == NULL) { 1167 handler = (unsigned long) do_default_vi; 1168 srs = 0; 1169 } else 1170 handler = (unsigned long) addr; 1171 vi_handlers[n] = (unsigned long) addr; 1172 1173 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1174 1175 if (srs >= mips_srs_max()) 1176 panic("Shadow register set %d not supported", srs); 1177 1178 if (cpu_has_veic) { 1179 if (board_bind_eic_interrupt) 1180 board_bind_eic_interrupt (n, srs); 1181 } else if (cpu_has_vint) { 1182 /* SRSMap is only defined if shadow sets are implemented */ 1183 if (mips_srs_max() > 1) 1184 change_c0_srsmap (0xf << n*4, srs << n*4); 1185 } 1186 1187 if (srs == 0) { 1188 /* 1189 * If no shadow set is selected then use the default handler 1190 * that does normal register saving and a standard interrupt exit 1191 */ 1192 1193 extern char except_vec_vi, except_vec_vi_lui; 1194 extern char except_vec_vi_ori, except_vec_vi_end; 1195 #ifdef CONFIG_MIPS_MT_SMTC 1196 /* 1197 * We need to provide the SMTC vectored interrupt handler 1198 * not only with the address of the handler, but with the 1199 * Status.IM bit to be masked before going there. 1200 */ 1201 extern char except_vec_vi_mori; 1202 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1203 #endif /* CONFIG_MIPS_MT_SMTC */ 1204 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1205 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1206 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1207 1208 if (handler_len > VECTORSPACING) { 1209 /* 1210 * Sigh... panicing won't help as the console 1211 * is probably not configured :( 1212 */ 1213 panic ("VECTORSPACING too small"); 1214 } 1215 1216 memcpy (b, &except_vec_vi, handler_len); 1217 #ifdef CONFIG_MIPS_MT_SMTC 1218 if (n > 7) 1219 printk("Vector index %d exceeds SMTC maximum\n", n); 1220 w = (u32 *)(b + mori_offset); 1221 *w = (*w & 0xffff0000) | (0x100 << n); 1222 #endif /* CONFIG_MIPS_MT_SMTC */ 1223 w = (u32 *)(b + lui_offset); 1224 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1225 w = (u32 *)(b + ori_offset); 1226 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1227 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1228 } 1229 else { 1230 /* 1231 * In other cases jump directly to the interrupt handler 1232 * 1233 * It is the handlers responsibility to save registers if required 1234 * (eg hi/lo) and return from the exception using "eret" 1235 */ 1236 w = (u32 *)b; 1237 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1238 *w = 0; 1239 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1240 } 1241 1242 return (void *)old_handler; 1243 } 1244 1245 void *set_vi_handler(int n, void *addr) 1246 { 1247 return set_vi_srs_handler(n, addr, 0); 1248 } 1249 1250 #else 1251 1252 static inline void mips_srs_init(void) 1253 { 1254 } 1255 1256 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1257 1258 /* 1259 * This is used by native signal handling 1260 */ 1261 asmlinkage int (*save_fp_context)(struct sigcontext *sc); 1262 asmlinkage int (*restore_fp_context)(struct sigcontext *sc); 1263 1264 extern asmlinkage int _save_fp_context(struct sigcontext *sc); 1265 extern asmlinkage int _restore_fp_context(struct sigcontext *sc); 1266 1267 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); 1268 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); 1269 1270 #ifdef CONFIG_SMP 1271 static int smp_save_fp_context(struct sigcontext *sc) 1272 { 1273 return cpu_has_fpu 1274 ? _save_fp_context(sc) 1275 : fpu_emulator_save_context(sc); 1276 } 1277 1278 static int smp_restore_fp_context(struct sigcontext *sc) 1279 { 1280 return cpu_has_fpu 1281 ? _restore_fp_context(sc) 1282 : fpu_emulator_restore_context(sc); 1283 } 1284 #endif 1285 1286 static inline void signal_init(void) 1287 { 1288 #ifdef CONFIG_SMP 1289 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1290 save_fp_context = smp_save_fp_context; 1291 restore_fp_context = smp_restore_fp_context; 1292 #else 1293 if (cpu_has_fpu) { 1294 save_fp_context = _save_fp_context; 1295 restore_fp_context = _restore_fp_context; 1296 } else { 1297 save_fp_context = fpu_emulator_save_context; 1298 restore_fp_context = fpu_emulator_restore_context; 1299 } 1300 #endif 1301 } 1302 1303 #ifdef CONFIG_MIPS32_COMPAT 1304 1305 /* 1306 * This is used by 32-bit signal stuff on the 64-bit kernel 1307 */ 1308 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); 1309 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); 1310 1311 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); 1312 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); 1313 1314 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); 1315 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); 1316 1317 static inline void signal32_init(void) 1318 { 1319 if (cpu_has_fpu) { 1320 save_fp_context32 = _save_fp_context32; 1321 restore_fp_context32 = _restore_fp_context32; 1322 } else { 1323 save_fp_context32 = fpu_emulator_save_context32; 1324 restore_fp_context32 = fpu_emulator_restore_context32; 1325 } 1326 } 1327 #endif 1328 1329 extern void cpu_cache_init(void); 1330 extern void tlb_init(void); 1331 extern void flush_tlb_handlers(void); 1332 1333 void __init per_cpu_trap_init(void) 1334 { 1335 unsigned int cpu = smp_processor_id(); 1336 unsigned int status_set = ST0_CU0; 1337 #ifdef CONFIG_MIPS_MT_SMTC 1338 int secondaryTC = 0; 1339 int bootTC = (cpu == 0); 1340 1341 /* 1342 * Only do per_cpu_trap_init() for first TC of Each VPE. 1343 * Note that this hack assumes that the SMTC init code 1344 * assigns TCs consecutively and in ascending order. 1345 */ 1346 1347 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1348 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1349 secondaryTC = 1; 1350 #endif /* CONFIG_MIPS_MT_SMTC */ 1351 1352 /* 1353 * Disable coprocessors and select 32-bit or 64-bit addressing 1354 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1355 * flag that some firmware may have left set and the TS bit (for 1356 * IP27). Set XX for ISA IV code to work. 1357 */ 1358 #ifdef CONFIG_64BIT 1359 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1360 #endif 1361 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1362 status_set |= ST0_XX; 1363 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1364 status_set); 1365 1366 if (cpu_has_dsp) 1367 set_c0_status(ST0_MX); 1368 1369 #ifdef CONFIG_CPU_MIPSR2 1370 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ 1371 #endif 1372 1373 #ifdef CONFIG_MIPS_MT_SMTC 1374 if (!secondaryTC) { 1375 #endif /* CONFIG_MIPS_MT_SMTC */ 1376 1377 /* 1378 * Interrupt handling. 1379 */ 1380 if (cpu_has_veic || cpu_has_vint) { 1381 write_c0_ebase (ebase); 1382 /* Setting vector spacing enables EI/VI mode */ 1383 change_c0_intctl (0x3e0, VECTORSPACING); 1384 } 1385 if (cpu_has_divec) { 1386 if (cpu_has_mipsmt) { 1387 unsigned int vpflags = dvpe(); 1388 set_c0_cause(CAUSEF_IV); 1389 evpe(vpflags); 1390 } else 1391 set_c0_cause(CAUSEF_IV); 1392 } 1393 #ifdef CONFIG_MIPS_MT_SMTC 1394 } 1395 #endif /* CONFIG_MIPS_MT_SMTC */ 1396 1397 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1398 TLBMISS_HANDLER_SETUP(); 1399 1400 atomic_inc(&init_mm.mm_count); 1401 current->active_mm = &init_mm; 1402 BUG_ON(current->mm); 1403 enter_lazy_tlb(&init_mm, current); 1404 1405 #ifdef CONFIG_MIPS_MT_SMTC 1406 if (bootTC) { 1407 #endif /* CONFIG_MIPS_MT_SMTC */ 1408 cpu_cache_init(); 1409 tlb_init(); 1410 #ifdef CONFIG_MIPS_MT_SMTC 1411 } 1412 #endif /* CONFIG_MIPS_MT_SMTC */ 1413 } 1414 1415 /* Install CPU exception handler */ 1416 void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1417 { 1418 memcpy((void *)(ebase + offset), addr, size); 1419 flush_icache_range(ebase + offset, ebase + offset + size); 1420 } 1421 1422 /* Install uncached CPU exception handler */ 1423 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1424 { 1425 #ifdef CONFIG_32BIT 1426 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1427 #endif 1428 #ifdef CONFIG_64BIT 1429 unsigned long uncached_ebase = TO_UNCAC(ebase); 1430 #endif 1431 1432 memcpy((void *)(uncached_ebase + offset), addr, size); 1433 } 1434 1435 static int __initdata rdhwr_noopt; 1436 static int __init set_rdhwr_noopt(char *str) 1437 { 1438 rdhwr_noopt = 1; 1439 return 1; 1440 } 1441 1442 __setup("rdhwr_noopt", set_rdhwr_noopt); 1443 1444 void __init trap_init(void) 1445 { 1446 extern char except_vec3_generic, except_vec3_r4000; 1447 extern char except_vec4; 1448 unsigned long i; 1449 1450 if (cpu_has_veic || cpu_has_vint) 1451 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1452 else 1453 ebase = CAC_BASE; 1454 1455 mips_srs_init(); 1456 1457 per_cpu_trap_init(); 1458 1459 /* 1460 * Copy the generic exception handlers to their final destination. 1461 * This will be overriden later as suitable for a particular 1462 * configuration. 1463 */ 1464 set_handler(0x180, &except_vec3_generic, 0x80); 1465 1466 /* 1467 * Setup default vectors 1468 */ 1469 for (i = 0; i <= 31; i++) 1470 set_except_vector(i, handle_reserved); 1471 1472 /* 1473 * Copy the EJTAG debug exception vector handler code to it's final 1474 * destination. 1475 */ 1476 if (cpu_has_ejtag && board_ejtag_handler_setup) 1477 board_ejtag_handler_setup (); 1478 1479 /* 1480 * Only some CPUs have the watch exceptions. 1481 */ 1482 if (cpu_has_watch) 1483 set_except_vector(23, handle_watch); 1484 1485 /* 1486 * Initialise interrupt handlers 1487 */ 1488 if (cpu_has_veic || cpu_has_vint) { 1489 int nvec = cpu_has_veic ? 64 : 8; 1490 for (i = 0; i < nvec; i++) 1491 set_vi_handler(i, NULL); 1492 } 1493 else if (cpu_has_divec) 1494 set_handler(0x200, &except_vec4, 0x8); 1495 1496 /* 1497 * Some CPUs can enable/disable for cache parity detection, but does 1498 * it different ways. 1499 */ 1500 parity_protection_init(); 1501 1502 /* 1503 * The Data Bus Errors / Instruction Bus Errors are signaled 1504 * by external hardware. Therefore these two exceptions 1505 * may have board specific handlers. 1506 */ 1507 if (board_be_init) 1508 board_be_init(); 1509 1510 set_except_vector(0, handle_int); 1511 set_except_vector(1, handle_tlbm); 1512 set_except_vector(2, handle_tlbl); 1513 set_except_vector(3, handle_tlbs); 1514 1515 set_except_vector(4, handle_adel); 1516 set_except_vector(5, handle_ades); 1517 1518 set_except_vector(6, handle_ibe); 1519 set_except_vector(7, handle_dbe); 1520 1521 set_except_vector(8, handle_sys); 1522 set_except_vector(9, handle_bp); 1523 set_except_vector(10, rdhwr_noopt ? handle_ri : 1524 (cpu_has_vtag_icache ? 1525 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1526 set_except_vector(11, handle_cpu); 1527 set_except_vector(12, handle_ov); 1528 set_except_vector(13, handle_tr); 1529 1530 if (current_cpu_data.cputype == CPU_R6000 || 1531 current_cpu_data.cputype == CPU_R6000A) { 1532 /* 1533 * The R6000 is the only R-series CPU that features a machine 1534 * check exception (similar to the R4000 cache error) and 1535 * unaligned ldc1/sdc1 exception. The handlers have not been 1536 * written yet. Well, anyway there is no R6000 machine on the 1537 * current list of targets for Linux/MIPS. 1538 * (Duh, crap, there is someone with a triple R6k machine) 1539 */ 1540 //set_except_vector(14, handle_mc); 1541 //set_except_vector(15, handle_ndc); 1542 } 1543 1544 1545 if (board_nmi_handler_setup) 1546 board_nmi_handler_setup(); 1547 1548 if (cpu_has_fpu && !cpu_has_nofpuex) 1549 set_except_vector(15, handle_fpe); 1550 1551 set_except_vector(22, handle_mdmx); 1552 1553 if (cpu_has_mcheck) 1554 set_except_vector(24, handle_mcheck); 1555 1556 if (cpu_has_mipsmt) 1557 set_except_vector(25, handle_mt); 1558 1559 if (cpu_has_dsp) 1560 set_except_vector(26, handle_dsp); 1561 1562 if (cpu_has_vce) 1563 /* Special exception: R4[04]00 uses also the divec space. */ 1564 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1565 else if (cpu_has_4kex) 1566 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1567 else 1568 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1569 1570 signal_init(); 1571 #ifdef CONFIG_MIPS32_COMPAT 1572 signal32_init(); 1573 #endif 1574 1575 flush_icache_range(ebase, ebase + 0x400); 1576 flush_tlb_handlers(); 1577 } 1578