1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/compiler.h> 18 #include <linux/context_tracking.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/kexec.h> 21 #include <linux/init.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/smp.h> 27 #include <linux/spinlock.h> 28 #include <linux/kallsyms.h> 29 #include <linux/bootmem.h> 30 #include <linux/interrupt.h> 31 #include <linux/ptrace.h> 32 #include <linux/kgdb.h> 33 #include <linux/kdebug.h> 34 #include <linux/kprobes.h> 35 #include <linux/notifier.h> 36 #include <linux/kdb.h> 37 #include <linux/irq.h> 38 #include <linux/perf_event.h> 39 40 #include <asm/bootinfo.h> 41 #include <asm/branch.h> 42 #include <asm/break.h> 43 #include <asm/cop2.h> 44 #include <asm/cpu.h> 45 #include <asm/cpu-type.h> 46 #include <asm/dsp.h> 47 #include <asm/fpu.h> 48 #include <asm/fpu_emulator.h> 49 #include <asm/idle.h> 50 #include <asm/mips-r2-to-r6-emul.h> 51 #include <asm/mipsregs.h> 52 #include <asm/mipsmtregs.h> 53 #include <asm/module.h> 54 #include <asm/msa.h> 55 #include <asm/pgtable.h> 56 #include <asm/ptrace.h> 57 #include <asm/sections.h> 58 #include <asm/tlbdebug.h> 59 #include <asm/traps.h> 60 #include <asm/uaccess.h> 61 #include <asm/watch.h> 62 #include <asm/mmu_context.h> 63 #include <asm/types.h> 64 #include <asm/stacktrace.h> 65 #include <asm/uasm.h> 66 67 extern void check_wait(void); 68 extern asmlinkage void rollback_handle_int(void); 69 extern asmlinkage void handle_int(void); 70 extern u32 handle_tlbl[]; 71 extern u32 handle_tlbs[]; 72 extern u32 handle_tlbm[]; 73 extern asmlinkage void handle_adel(void); 74 extern asmlinkage void handle_ades(void); 75 extern asmlinkage void handle_ibe(void); 76 extern asmlinkage void handle_dbe(void); 77 extern asmlinkage void handle_sys(void); 78 extern asmlinkage void handle_bp(void); 79 extern asmlinkage void handle_ri(void); 80 extern asmlinkage void handle_ri_rdhwr_vivt(void); 81 extern asmlinkage void handle_ri_rdhwr(void); 82 extern asmlinkage void handle_cpu(void); 83 extern asmlinkage void handle_ov(void); 84 extern asmlinkage void handle_tr(void); 85 extern asmlinkage void handle_msa_fpe(void); 86 extern asmlinkage void handle_fpe(void); 87 extern asmlinkage void handle_ftlb(void); 88 extern asmlinkage void handle_msa(void); 89 extern asmlinkage void handle_mdmx(void); 90 extern asmlinkage void handle_watch(void); 91 extern asmlinkage void handle_mt(void); 92 extern asmlinkage void handle_dsp(void); 93 extern asmlinkage void handle_mcheck(void); 94 extern asmlinkage void handle_reserved(void); 95 extern void tlb_do_page_fault_0(void); 96 97 void (*board_be_init)(void); 98 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 99 void (*board_nmi_handler_setup)(void); 100 void (*board_ejtag_handler_setup)(void); 101 void (*board_bind_eic_interrupt)(int irq, int regset); 102 void (*board_ebase_setup)(void); 103 void(*board_cache_error_setup)(void); 104 105 static void show_raw_backtrace(unsigned long reg29) 106 { 107 unsigned long *sp = (unsigned long *)(reg29 & ~3); 108 unsigned long addr; 109 110 printk("Call Trace:"); 111 #ifdef CONFIG_KALLSYMS 112 printk("\n"); 113 #endif 114 while (!kstack_end(sp)) { 115 unsigned long __user *p = 116 (unsigned long __user *)(unsigned long)sp++; 117 if (__get_user(addr, p)) { 118 printk(" (Bad stack address)"); 119 break; 120 } 121 if (__kernel_text_address(addr)) 122 print_ip_sym(addr); 123 } 124 printk("\n"); 125 } 126 127 #ifdef CONFIG_KALLSYMS 128 int raw_show_trace; 129 static int __init set_raw_show_trace(char *str) 130 { 131 raw_show_trace = 1; 132 return 1; 133 } 134 __setup("raw_show_trace", set_raw_show_trace); 135 #endif 136 137 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 138 { 139 unsigned long sp = regs->regs[29]; 140 unsigned long ra = regs->regs[31]; 141 unsigned long pc = regs->cp0_epc; 142 143 if (!task) 144 task = current; 145 146 if (raw_show_trace || !__kernel_text_address(pc)) { 147 show_raw_backtrace(sp); 148 return; 149 } 150 printk("Call Trace:\n"); 151 do { 152 print_ip_sym(pc); 153 pc = unwind_stack(task, &sp, pc, &ra); 154 } while (pc); 155 printk("\n"); 156 } 157 158 /* 159 * This routine abuses get_user()/put_user() to reference pointers 160 * with at least a bit of error checking ... 161 */ 162 static void show_stacktrace(struct task_struct *task, 163 const struct pt_regs *regs) 164 { 165 const int field = 2 * sizeof(unsigned long); 166 long stackdata; 167 int i; 168 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 169 170 printk("Stack :"); 171 i = 0; 172 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 173 if (i && ((i % (64 / field)) == 0)) 174 printk("\n "); 175 if (i > 39) { 176 printk(" ..."); 177 break; 178 } 179 180 if (__get_user(stackdata, sp++)) { 181 printk(" (Bad stack address)"); 182 break; 183 } 184 185 printk(" %0*lx", field, stackdata); 186 i++; 187 } 188 printk("\n"); 189 show_backtrace(task, regs); 190 } 191 192 void show_stack(struct task_struct *task, unsigned long *sp) 193 { 194 struct pt_regs regs; 195 if (sp) { 196 regs.regs[29] = (unsigned long)sp; 197 regs.regs[31] = 0; 198 regs.cp0_epc = 0; 199 } else { 200 if (task && task != current) { 201 regs.regs[29] = task->thread.reg29; 202 regs.regs[31] = 0; 203 regs.cp0_epc = task->thread.reg31; 204 #ifdef CONFIG_KGDB_KDB 205 } else if (atomic_read(&kgdb_active) != -1 && 206 kdb_current_regs) { 207 memcpy(®s, kdb_current_regs, sizeof(regs)); 208 #endif /* CONFIG_KGDB_KDB */ 209 } else { 210 prepare_frametrace(®s); 211 } 212 } 213 show_stacktrace(task, ®s); 214 } 215 216 static void show_code(unsigned int __user *pc) 217 { 218 long i; 219 unsigned short __user *pc16 = NULL; 220 221 printk("\nCode:"); 222 223 if ((unsigned long)pc & 1) 224 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 225 for(i = -3 ; i < 6 ; i++) { 226 unsigned int insn; 227 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 228 printk(" (Bad address in epc)\n"); 229 break; 230 } 231 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 232 } 233 } 234 235 static void __show_regs(const struct pt_regs *regs) 236 { 237 const int field = 2 * sizeof(unsigned long); 238 unsigned int cause = regs->cp0_cause; 239 int i; 240 241 show_regs_print_info(KERN_DEFAULT); 242 243 /* 244 * Saved main processor registers 245 */ 246 for (i = 0; i < 32; ) { 247 if ((i % 4) == 0) 248 printk("$%2d :", i); 249 if (i == 0) 250 printk(" %0*lx", field, 0UL); 251 else if (i == 26 || i == 27) 252 printk(" %*s", field, ""); 253 else 254 printk(" %0*lx", field, regs->regs[i]); 255 256 i++; 257 if ((i % 4) == 0) 258 printk("\n"); 259 } 260 261 #ifdef CONFIG_CPU_HAS_SMARTMIPS 262 printk("Acx : %0*lx\n", field, regs->acx); 263 #endif 264 printk("Hi : %0*lx\n", field, regs->hi); 265 printk("Lo : %0*lx\n", field, regs->lo); 266 267 /* 268 * Saved cp0 registers 269 */ 270 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 271 (void *) regs->cp0_epc); 272 printk(" %s\n", print_tainted()); 273 printk("ra : %0*lx %pS\n", field, regs->regs[31], 274 (void *) regs->regs[31]); 275 276 printk("Status: %08x ", (uint32_t) regs->cp0_status); 277 278 if (cpu_has_3kex) { 279 if (regs->cp0_status & ST0_KUO) 280 printk("KUo "); 281 if (regs->cp0_status & ST0_IEO) 282 printk("IEo "); 283 if (regs->cp0_status & ST0_KUP) 284 printk("KUp "); 285 if (regs->cp0_status & ST0_IEP) 286 printk("IEp "); 287 if (regs->cp0_status & ST0_KUC) 288 printk("KUc "); 289 if (regs->cp0_status & ST0_IEC) 290 printk("IEc "); 291 } else if (cpu_has_4kex) { 292 if (regs->cp0_status & ST0_KX) 293 printk("KX "); 294 if (regs->cp0_status & ST0_SX) 295 printk("SX "); 296 if (regs->cp0_status & ST0_UX) 297 printk("UX "); 298 switch (regs->cp0_status & ST0_KSU) { 299 case KSU_USER: 300 printk("USER "); 301 break; 302 case KSU_SUPERVISOR: 303 printk("SUPERVISOR "); 304 break; 305 case KSU_KERNEL: 306 printk("KERNEL "); 307 break; 308 default: 309 printk("BAD_MODE "); 310 break; 311 } 312 if (regs->cp0_status & ST0_ERL) 313 printk("ERL "); 314 if (regs->cp0_status & ST0_EXL) 315 printk("EXL "); 316 if (regs->cp0_status & ST0_IE) 317 printk("IE "); 318 } 319 printk("\n"); 320 321 printk("Cause : %08x\n", cause); 322 323 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 324 if (1 <= cause && cause <= 5) 325 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 326 327 printk("PrId : %08x (%s)\n", read_c0_prid(), 328 cpu_name_string()); 329 } 330 331 /* 332 * FIXME: really the generic show_regs should take a const pointer argument. 333 */ 334 void show_regs(struct pt_regs *regs) 335 { 336 __show_regs((struct pt_regs *)regs); 337 } 338 339 void show_registers(struct pt_regs *regs) 340 { 341 const int field = 2 * sizeof(unsigned long); 342 mm_segment_t old_fs = get_fs(); 343 344 __show_regs(regs); 345 print_modules(); 346 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 347 current->comm, current->pid, current_thread_info(), current, 348 field, current_thread_info()->tp_value); 349 if (cpu_has_userlocal) { 350 unsigned long tls; 351 352 tls = read_c0_userlocal(); 353 if (tls != current_thread_info()->tp_value) 354 printk("*HwTLS: %0*lx\n", field, tls); 355 } 356 357 if (!user_mode(regs)) 358 /* Necessary for getting the correct stack content */ 359 set_fs(KERNEL_DS); 360 show_stacktrace(current, regs); 361 show_code((unsigned int __user *) regs->cp0_epc); 362 printk("\n"); 363 set_fs(old_fs); 364 } 365 366 static int regs_to_trapnr(struct pt_regs *regs) 367 { 368 return (regs->cp0_cause >> 2) & 0x1f; 369 } 370 371 static DEFINE_RAW_SPINLOCK(die_lock); 372 373 void __noreturn die(const char *str, struct pt_regs *regs) 374 { 375 static int die_counter; 376 int sig = SIGSEGV; 377 378 oops_enter(); 379 380 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), 381 SIGSEGV) == NOTIFY_STOP) 382 sig = 0; 383 384 console_verbose(); 385 raw_spin_lock_irq(&die_lock); 386 bust_spinlocks(1); 387 388 printk("%s[#%d]:\n", str, ++die_counter); 389 show_registers(regs); 390 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 391 raw_spin_unlock_irq(&die_lock); 392 393 oops_exit(); 394 395 if (in_interrupt()) 396 panic("Fatal exception in interrupt"); 397 398 if (panic_on_oops) { 399 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 400 ssleep(5); 401 panic("Fatal exception"); 402 } 403 404 if (regs && kexec_should_crash(current)) 405 crash_kexec(regs); 406 407 do_exit(sig); 408 } 409 410 extern struct exception_table_entry __start___dbe_table[]; 411 extern struct exception_table_entry __stop___dbe_table[]; 412 413 __asm__( 414 " .section __dbe_table, \"a\"\n" 415 " .previous \n"); 416 417 /* Given an address, look for it in the exception tables. */ 418 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 419 { 420 const struct exception_table_entry *e; 421 422 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 423 if (!e) 424 e = search_module_dbetables(addr); 425 return e; 426 } 427 428 asmlinkage void do_be(struct pt_regs *regs) 429 { 430 const int field = 2 * sizeof(unsigned long); 431 const struct exception_table_entry *fixup = NULL; 432 int data = regs->cp0_cause & 4; 433 int action = MIPS_BE_FATAL; 434 enum ctx_state prev_state; 435 436 prev_state = exception_enter(); 437 /* XXX For now. Fixme, this searches the wrong table ... */ 438 if (data && !user_mode(regs)) 439 fixup = search_dbe_tables(exception_epc(regs)); 440 441 if (fixup) 442 action = MIPS_BE_FIXUP; 443 444 if (board_be_handler) 445 action = board_be_handler(regs, fixup != NULL); 446 447 switch (action) { 448 case MIPS_BE_DISCARD: 449 goto out; 450 case MIPS_BE_FIXUP: 451 if (fixup) { 452 regs->cp0_epc = fixup->nextinsn; 453 goto out; 454 } 455 break; 456 default: 457 break; 458 } 459 460 /* 461 * Assume it would be too dangerous to continue ... 462 */ 463 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 464 data ? "Data" : "Instruction", 465 field, regs->cp0_epc, field, regs->regs[31]); 466 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), 467 SIGBUS) == NOTIFY_STOP) 468 goto out; 469 470 die_if_kernel("Oops", regs); 471 force_sig(SIGBUS, current); 472 473 out: 474 exception_exit(prev_state); 475 } 476 477 /* 478 * ll/sc, rdhwr, sync emulation 479 */ 480 481 #define OPCODE 0xfc000000 482 #define BASE 0x03e00000 483 #define RT 0x001f0000 484 #define OFFSET 0x0000ffff 485 #define LL 0xc0000000 486 #define SC 0xe0000000 487 #define SPEC0 0x00000000 488 #define SPEC3 0x7c000000 489 #define RD 0x0000f800 490 #define FUNC 0x0000003f 491 #define SYNC 0x0000000f 492 #define RDHWR 0x0000003b 493 494 /* microMIPS definitions */ 495 #define MM_POOL32A_FUNC 0xfc00ffff 496 #define MM_RDHWR 0x00006b3c 497 #define MM_RS 0x001f0000 498 #define MM_RT 0x03e00000 499 500 /* 501 * The ll_bit is cleared by r*_switch.S 502 */ 503 504 unsigned int ll_bit; 505 struct task_struct *ll_task; 506 507 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 508 { 509 unsigned long value, __user *vaddr; 510 long offset; 511 512 /* 513 * analyse the ll instruction that just caused a ri exception 514 * and put the referenced address to addr. 515 */ 516 517 /* sign extend offset */ 518 offset = opcode & OFFSET; 519 offset <<= 16; 520 offset >>= 16; 521 522 vaddr = (unsigned long __user *) 523 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 524 525 if ((unsigned long)vaddr & 3) 526 return SIGBUS; 527 if (get_user(value, vaddr)) 528 return SIGSEGV; 529 530 preempt_disable(); 531 532 if (ll_task == NULL || ll_task == current) { 533 ll_bit = 1; 534 } else { 535 ll_bit = 0; 536 } 537 ll_task = current; 538 539 preempt_enable(); 540 541 regs->regs[(opcode & RT) >> 16] = value; 542 543 return 0; 544 } 545 546 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 547 { 548 unsigned long __user *vaddr; 549 unsigned long reg; 550 long offset; 551 552 /* 553 * analyse the sc instruction that just caused a ri exception 554 * and put the referenced address to addr. 555 */ 556 557 /* sign extend offset */ 558 offset = opcode & OFFSET; 559 offset <<= 16; 560 offset >>= 16; 561 562 vaddr = (unsigned long __user *) 563 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 564 reg = (opcode & RT) >> 16; 565 566 if ((unsigned long)vaddr & 3) 567 return SIGBUS; 568 569 preempt_disable(); 570 571 if (ll_bit == 0 || ll_task != current) { 572 regs->regs[reg] = 0; 573 preempt_enable(); 574 return 0; 575 } 576 577 preempt_enable(); 578 579 if (put_user(regs->regs[reg], vaddr)) 580 return SIGSEGV; 581 582 regs->regs[reg] = 1; 583 584 return 0; 585 } 586 587 /* 588 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 589 * opcodes are supposed to result in coprocessor unusable exceptions if 590 * executed on ll/sc-less processors. That's the theory. In practice a 591 * few processors such as NEC's VR4100 throw reserved instruction exceptions 592 * instead, so we're doing the emulation thing in both exception handlers. 593 */ 594 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 595 { 596 if ((opcode & OPCODE) == LL) { 597 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 598 1, regs, 0); 599 return simulate_ll(regs, opcode); 600 } 601 if ((opcode & OPCODE) == SC) { 602 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 603 1, regs, 0); 604 return simulate_sc(regs, opcode); 605 } 606 607 return -1; /* Must be something else ... */ 608 } 609 610 /* 611 * Simulate trapping 'rdhwr' instructions to provide user accessible 612 * registers not implemented in hardware. 613 */ 614 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 615 { 616 struct thread_info *ti = task_thread_info(current); 617 618 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 619 1, regs, 0); 620 switch (rd) { 621 case 0: /* CPU number */ 622 regs->regs[rt] = smp_processor_id(); 623 return 0; 624 case 1: /* SYNCI length */ 625 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 626 current_cpu_data.icache.linesz); 627 return 0; 628 case 2: /* Read count register */ 629 regs->regs[rt] = read_c0_count(); 630 return 0; 631 case 3: /* Count register resolution */ 632 switch (current_cpu_type()) { 633 case CPU_20KC: 634 case CPU_25KF: 635 regs->regs[rt] = 1; 636 break; 637 default: 638 regs->regs[rt] = 2; 639 } 640 return 0; 641 case 29: 642 regs->regs[rt] = ti->tp_value; 643 return 0; 644 default: 645 return -1; 646 } 647 } 648 649 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 650 { 651 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 652 int rd = (opcode & RD) >> 11; 653 int rt = (opcode & RT) >> 16; 654 655 simulate_rdhwr(regs, rd, rt); 656 return 0; 657 } 658 659 /* Not ours. */ 660 return -1; 661 } 662 663 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 664 { 665 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 666 int rd = (opcode & MM_RS) >> 16; 667 int rt = (opcode & MM_RT) >> 21; 668 simulate_rdhwr(regs, rd, rt); 669 return 0; 670 } 671 672 /* Not ours. */ 673 return -1; 674 } 675 676 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 677 { 678 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 679 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 680 1, regs, 0); 681 return 0; 682 } 683 684 return -1; /* Must be something else ... */ 685 } 686 687 asmlinkage void do_ov(struct pt_regs *regs) 688 { 689 enum ctx_state prev_state; 690 siginfo_t info; 691 692 prev_state = exception_enter(); 693 die_if_kernel("Integer overflow", regs); 694 695 info.si_code = FPE_INTOVF; 696 info.si_signo = SIGFPE; 697 info.si_errno = 0; 698 info.si_addr = (void __user *) regs->cp0_epc; 699 force_sig_info(SIGFPE, &info, current); 700 exception_exit(prev_state); 701 } 702 703 int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 704 { 705 struct siginfo si = { 0 }; 706 707 switch (sig) { 708 case 0: 709 return 0; 710 711 case SIGFPE: 712 si.si_addr = fault_addr; 713 si.si_signo = sig; 714 /* 715 * Inexact can happen together with Overflow or Underflow. 716 * Respect the mask to deliver the correct exception. 717 */ 718 fcr31 &= (fcr31 & FPU_CSR_ALL_E) << 719 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)); 720 if (fcr31 & FPU_CSR_INV_X) 721 si.si_code = FPE_FLTINV; 722 else if (fcr31 & FPU_CSR_DIV_X) 723 si.si_code = FPE_FLTDIV; 724 else if (fcr31 & FPU_CSR_OVF_X) 725 si.si_code = FPE_FLTOVF; 726 else if (fcr31 & FPU_CSR_UDF_X) 727 si.si_code = FPE_FLTUND; 728 else if (fcr31 & FPU_CSR_INE_X) 729 si.si_code = FPE_FLTRES; 730 else 731 si.si_code = __SI_FAULT; 732 force_sig_info(sig, &si, current); 733 return 1; 734 735 case SIGBUS: 736 si.si_addr = fault_addr; 737 si.si_signo = sig; 738 si.si_code = BUS_ADRERR; 739 force_sig_info(sig, &si, current); 740 return 1; 741 742 case SIGSEGV: 743 si.si_addr = fault_addr; 744 si.si_signo = sig; 745 down_read(¤t->mm->mmap_sem); 746 if (find_vma(current->mm, (unsigned long)fault_addr)) 747 si.si_code = SEGV_ACCERR; 748 else 749 si.si_code = SEGV_MAPERR; 750 up_read(¤t->mm->mmap_sem); 751 force_sig_info(sig, &si, current); 752 return 1; 753 754 default: 755 force_sig(sig, current); 756 return 1; 757 } 758 } 759 760 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 761 unsigned long old_epc, unsigned long old_ra) 762 { 763 union mips_instruction inst = { .word = opcode }; 764 void __user *fault_addr; 765 unsigned long fcr31; 766 int sig; 767 768 /* If it's obviously not an FP instruction, skip it */ 769 switch (inst.i_format.opcode) { 770 case cop1_op: 771 case cop1x_op: 772 case lwc1_op: 773 case ldc1_op: 774 case swc1_op: 775 case sdc1_op: 776 break; 777 778 default: 779 return -1; 780 } 781 782 /* 783 * do_ri skipped over the instruction via compute_return_epc, undo 784 * that for the FPU emulator. 785 */ 786 regs->cp0_epc = old_epc; 787 regs->regs[31] = old_ra; 788 789 /* Save the FP context to struct thread_struct */ 790 lose_fpu(1); 791 792 /* Run the emulator */ 793 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 794 &fault_addr); 795 fcr31 = current->thread.fpu.fcr31; 796 797 /* 798 * We can't allow the emulated instruction to leave any of 799 * the cause bits set in $fcr31. 800 */ 801 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 802 803 /* Restore the hardware register state */ 804 own_fpu(1); 805 806 /* Send a signal if required. */ 807 process_fpemu_return(sig, fault_addr, fcr31); 808 809 return 0; 810 } 811 812 /* 813 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 814 */ 815 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 816 { 817 enum ctx_state prev_state; 818 void __user *fault_addr; 819 int sig; 820 821 prev_state = exception_enter(); 822 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 823 SIGFPE) == NOTIFY_STOP) 824 goto out; 825 die_if_kernel("FP exception in kernel code", regs); 826 827 if (fcr31 & FPU_CSR_UNI_X) { 828 /* 829 * Unimplemented operation exception. If we've got the full 830 * software emulator on-board, let's use it... 831 * 832 * Force FPU to dump state into task/thread context. We're 833 * moving a lot of data here for what is probably a single 834 * instruction, but the alternative is to pre-decode the FP 835 * register operands before invoking the emulator, which seems 836 * a bit extreme for what should be an infrequent event. 837 */ 838 /* Ensure 'resume' not overwrite saved fp context again. */ 839 lose_fpu(1); 840 841 /* Run the emulator */ 842 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 843 &fault_addr); 844 fcr31 = current->thread.fpu.fcr31; 845 846 /* 847 * We can't allow the emulated instruction to leave any of 848 * the cause bits set in $fcr31. 849 */ 850 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 851 852 /* Restore the hardware register state */ 853 own_fpu(1); /* Using the FPU again. */ 854 } else { 855 sig = SIGFPE; 856 fault_addr = (void __user *) regs->cp0_epc; 857 } 858 859 /* Send a signal if required. */ 860 process_fpemu_return(sig, fault_addr, fcr31); 861 862 out: 863 exception_exit(prev_state); 864 } 865 866 void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 867 const char *str) 868 { 869 siginfo_t info; 870 char b[40]; 871 872 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 873 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 874 return; 875 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 876 877 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), 878 SIGTRAP) == NOTIFY_STOP) 879 return; 880 881 /* 882 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 883 * insns, even for trap and break codes that indicate arithmetic 884 * failures. Weird ... 885 * But should we continue the brokenness??? --macro 886 */ 887 switch (code) { 888 case BRK_OVERFLOW: 889 case BRK_DIVZERO: 890 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 891 die_if_kernel(b, regs); 892 if (code == BRK_DIVZERO) 893 info.si_code = FPE_INTDIV; 894 else 895 info.si_code = FPE_INTOVF; 896 info.si_signo = SIGFPE; 897 info.si_errno = 0; 898 info.si_addr = (void __user *) regs->cp0_epc; 899 force_sig_info(SIGFPE, &info, current); 900 break; 901 case BRK_BUG: 902 die_if_kernel("Kernel bug detected", regs); 903 force_sig(SIGTRAP, current); 904 break; 905 case BRK_MEMU: 906 /* 907 * This breakpoint code is used by the FPU emulator to retake 908 * control of the CPU after executing the instruction from the 909 * delay slot of an emulated branch. 910 * 911 * Terminate if exception was recognized as a delay slot return 912 * otherwise handle as normal. 913 */ 914 if (do_dsemulret(regs)) 915 return; 916 917 die_if_kernel("Math emu break/trap", regs); 918 force_sig(SIGTRAP, current); 919 break; 920 default: 921 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 922 die_if_kernel(b, regs); 923 force_sig(SIGTRAP, current); 924 } 925 } 926 927 asmlinkage void do_bp(struct pt_regs *regs) 928 { 929 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 930 unsigned int opcode, bcode; 931 enum ctx_state prev_state; 932 mm_segment_t seg; 933 934 seg = get_fs(); 935 if (!user_mode(regs)) 936 set_fs(KERNEL_DS); 937 938 prev_state = exception_enter(); 939 if (get_isa16_mode(regs->cp0_epc)) { 940 u16 instr[2]; 941 942 if (__get_user(instr[0], (u16 __user *)epc)) 943 goto out_sigsegv; 944 945 if (!cpu_has_mmips) { 946 /* MIPS16e mode */ 947 bcode = (instr[0] >> 5) & 0x3f; 948 } else if (mm_insn_16bit(instr[0])) { 949 /* 16-bit microMIPS BREAK */ 950 bcode = instr[0] & 0xf; 951 } else { 952 /* 32-bit microMIPS BREAK */ 953 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 954 goto out_sigsegv; 955 opcode = (instr[0] << 16) | instr[1]; 956 bcode = (opcode >> 6) & ((1 << 20) - 1); 957 } 958 } else { 959 if (__get_user(opcode, (unsigned int __user *)epc)) 960 goto out_sigsegv; 961 bcode = (opcode >> 6) & ((1 << 20) - 1); 962 } 963 964 /* 965 * There is the ancient bug in the MIPS assemblers that the break 966 * code starts left to bit 16 instead to bit 6 in the opcode. 967 * Gas is bug-compatible, but not always, grrr... 968 * We handle both cases with a simple heuristics. --macro 969 */ 970 if (bcode >= (1 << 10)) 971 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 972 973 /* 974 * notify the kprobe handlers, if instruction is likely to 975 * pertain to them. 976 */ 977 switch (bcode) { 978 case BRK_KPROBE_BP: 979 if (notify_die(DIE_BREAK, "debug", regs, bcode, 980 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 981 goto out; 982 else 983 break; 984 case BRK_KPROBE_SSTEPBP: 985 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 986 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 987 goto out; 988 else 989 break; 990 default: 991 break; 992 } 993 994 do_trap_or_bp(regs, bcode, "Break"); 995 996 out: 997 set_fs(seg); 998 exception_exit(prev_state); 999 return; 1000 1001 out_sigsegv: 1002 force_sig(SIGSEGV, current); 1003 goto out; 1004 } 1005 1006 asmlinkage void do_tr(struct pt_regs *regs) 1007 { 1008 u32 opcode, tcode = 0; 1009 enum ctx_state prev_state; 1010 u16 instr[2]; 1011 mm_segment_t seg; 1012 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1013 1014 seg = get_fs(); 1015 if (!user_mode(regs)) 1016 set_fs(get_ds()); 1017 1018 prev_state = exception_enter(); 1019 if (get_isa16_mode(regs->cp0_epc)) { 1020 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1021 __get_user(instr[1], (u16 __user *)(epc + 2))) 1022 goto out_sigsegv; 1023 opcode = (instr[0] << 16) | instr[1]; 1024 /* Immediate versions don't provide a code. */ 1025 if (!(opcode & OPCODE)) 1026 tcode = (opcode >> 12) & ((1 << 4) - 1); 1027 } else { 1028 if (__get_user(opcode, (u32 __user *)epc)) 1029 goto out_sigsegv; 1030 /* Immediate versions don't provide a code. */ 1031 if (!(opcode & OPCODE)) 1032 tcode = (opcode >> 6) & ((1 << 10) - 1); 1033 } 1034 1035 do_trap_or_bp(regs, tcode, "Trap"); 1036 1037 out: 1038 set_fs(seg); 1039 exception_exit(prev_state); 1040 return; 1041 1042 out_sigsegv: 1043 force_sig(SIGSEGV, current); 1044 goto out; 1045 } 1046 1047 asmlinkage void do_ri(struct pt_regs *regs) 1048 { 1049 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1050 unsigned long old_epc = regs->cp0_epc; 1051 unsigned long old31 = regs->regs[31]; 1052 enum ctx_state prev_state; 1053 unsigned int opcode = 0; 1054 int status = -1; 1055 1056 /* 1057 * Avoid any kernel code. Just emulate the R2 instruction 1058 * as quickly as possible. 1059 */ 1060 if (mipsr2_emulation && cpu_has_mips_r6 && 1061 likely(user_mode(regs)) && 1062 likely(get_user(opcode, epc) >= 0)) { 1063 unsigned long fcr31 = 0; 1064 1065 status = mipsr2_decoder(regs, opcode, &fcr31); 1066 switch (status) { 1067 case 0: 1068 case SIGEMT: 1069 task_thread_info(current)->r2_emul_return = 1; 1070 return; 1071 case SIGILL: 1072 goto no_r2_instr; 1073 default: 1074 process_fpemu_return(status, 1075 ¤t->thread.cp0_baduaddr, 1076 fcr31); 1077 task_thread_info(current)->r2_emul_return = 1; 1078 return; 1079 } 1080 } 1081 1082 no_r2_instr: 1083 1084 prev_state = exception_enter(); 1085 1086 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 1087 SIGILL) == NOTIFY_STOP) 1088 goto out; 1089 1090 die_if_kernel("Reserved instruction in kernel code", regs); 1091 1092 if (unlikely(compute_return_epc(regs) < 0)) 1093 goto out; 1094 1095 if (get_isa16_mode(regs->cp0_epc)) { 1096 unsigned short mmop[2] = { 0 }; 1097 1098 if (unlikely(get_user(mmop[0], epc) < 0)) 1099 status = SIGSEGV; 1100 if (unlikely(get_user(mmop[1], epc) < 0)) 1101 status = SIGSEGV; 1102 opcode = (mmop[0] << 16) | mmop[1]; 1103 1104 if (status < 0) 1105 status = simulate_rdhwr_mm(regs, opcode); 1106 } else { 1107 if (unlikely(get_user(opcode, epc) < 0)) 1108 status = SIGSEGV; 1109 1110 if (!cpu_has_llsc && status < 0) 1111 status = simulate_llsc(regs, opcode); 1112 1113 if (status < 0) 1114 status = simulate_rdhwr_normal(regs, opcode); 1115 1116 if (status < 0) 1117 status = simulate_sync(regs, opcode); 1118 1119 if (status < 0) 1120 status = simulate_fp(regs, opcode, old_epc, old31); 1121 } 1122 1123 if (status < 0) 1124 status = SIGILL; 1125 1126 if (unlikely(status > 0)) { 1127 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1128 regs->regs[31] = old31; 1129 force_sig(status, current); 1130 } 1131 1132 out: 1133 exception_exit(prev_state); 1134 } 1135 1136 /* 1137 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1138 * emulated more than some threshold number of instructions, force migration to 1139 * a "CPU" that has FP support. 1140 */ 1141 static void mt_ase_fp_affinity(void) 1142 { 1143 #ifdef CONFIG_MIPS_MT_FPAFF 1144 if (mt_fpemul_threshold > 0 && 1145 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1146 /* 1147 * If there's no FPU present, or if the application has already 1148 * restricted the allowed set to exclude any CPUs with FPUs, 1149 * we'll skip the procedure. 1150 */ 1151 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 1152 cpumask_t tmask; 1153 1154 current->thread.user_cpus_allowed 1155 = current->cpus_allowed; 1156 cpus_and(tmask, current->cpus_allowed, 1157 mt_fpu_cpumask); 1158 set_cpus_allowed_ptr(current, &tmask); 1159 set_thread_flag(TIF_FPUBOUND); 1160 } 1161 } 1162 #endif /* CONFIG_MIPS_MT_FPAFF */ 1163 } 1164 1165 /* 1166 * No lock; only written during early bootup by CPU 0. 1167 */ 1168 static RAW_NOTIFIER_HEAD(cu2_chain); 1169 1170 int __ref register_cu2_notifier(struct notifier_block *nb) 1171 { 1172 return raw_notifier_chain_register(&cu2_chain, nb); 1173 } 1174 1175 int cu2_notifier_call_chain(unsigned long val, void *v) 1176 { 1177 return raw_notifier_call_chain(&cu2_chain, val, v); 1178 } 1179 1180 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1181 void *data) 1182 { 1183 struct pt_regs *regs = data; 1184 1185 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1186 "instruction", regs); 1187 force_sig(SIGILL, current); 1188 1189 return NOTIFY_OK; 1190 } 1191 1192 static int wait_on_fp_mode_switch(atomic_t *p) 1193 { 1194 /* 1195 * The FP mode for this task is currently being switched. That may 1196 * involve modifications to the format of this tasks FP context which 1197 * make it unsafe to proceed with execution for the moment. Instead, 1198 * schedule some other task. 1199 */ 1200 schedule(); 1201 return 0; 1202 } 1203 1204 static int enable_restore_fp_context(int msa) 1205 { 1206 int err, was_fpu_owner, prior_msa; 1207 1208 /* 1209 * If an FP mode switch is currently underway, wait for it to 1210 * complete before proceeding. 1211 */ 1212 wait_on_atomic_t(¤t->mm->context.fp_mode_switching, 1213 wait_on_fp_mode_switch, TASK_KILLABLE); 1214 1215 if (!used_math()) { 1216 /* First time FP context user. */ 1217 preempt_disable(); 1218 err = init_fpu(); 1219 if (msa && !err) { 1220 enable_msa(); 1221 _init_msa_upper(); 1222 set_thread_flag(TIF_USEDMSA); 1223 set_thread_flag(TIF_MSA_CTX_LIVE); 1224 } 1225 preempt_enable(); 1226 if (!err) 1227 set_used_math(); 1228 return err; 1229 } 1230 1231 /* 1232 * This task has formerly used the FP context. 1233 * 1234 * If this thread has no live MSA vector context then we can simply 1235 * restore the scalar FP context. If it has live MSA vector context 1236 * (that is, it has or may have used MSA since last performing a 1237 * function call) then we'll need to restore the vector context. This 1238 * applies even if we're currently only executing a scalar FP 1239 * instruction. This is because if we were to later execute an MSA 1240 * instruction then we'd either have to: 1241 * 1242 * - Restore the vector context & clobber any registers modified by 1243 * scalar FP instructions between now & then. 1244 * 1245 * or 1246 * 1247 * - Not restore the vector context & lose the most significant bits 1248 * of all vector registers. 1249 * 1250 * Neither of those options is acceptable. We cannot restore the least 1251 * significant bits of the registers now & only restore the most 1252 * significant bits later because the most significant bits of any 1253 * vector registers whose aliased FP register is modified now will have 1254 * been zeroed. We'd have no way to know that when restoring the vector 1255 * context & thus may load an outdated value for the most significant 1256 * bits of a vector register. 1257 */ 1258 if (!msa && !thread_msa_context_live()) 1259 return own_fpu(1); 1260 1261 /* 1262 * This task is using or has previously used MSA. Thus we require 1263 * that Status.FR == 1. 1264 */ 1265 preempt_disable(); 1266 was_fpu_owner = is_fpu_owner(); 1267 err = own_fpu_inatomic(0); 1268 if (err) 1269 goto out; 1270 1271 enable_msa(); 1272 write_msa_csr(current->thread.fpu.msacsr); 1273 set_thread_flag(TIF_USEDMSA); 1274 1275 /* 1276 * If this is the first time that the task is using MSA and it has 1277 * previously used scalar FP in this time slice then we already nave 1278 * FP context which we shouldn't clobber. We do however need to clear 1279 * the upper 64b of each vector register so that this task has no 1280 * opportunity to see data left behind by another. 1281 */ 1282 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1283 if (!prior_msa && was_fpu_owner) { 1284 _init_msa_upper(); 1285 1286 goto out; 1287 } 1288 1289 if (!prior_msa) { 1290 /* 1291 * Restore the least significant 64b of each vector register 1292 * from the existing scalar FP context. 1293 */ 1294 _restore_fp(current); 1295 1296 /* 1297 * The task has not formerly used MSA, so clear the upper 64b 1298 * of each vector register such that it cannot see data left 1299 * behind by another task. 1300 */ 1301 _init_msa_upper(); 1302 } else { 1303 /* We need to restore the vector context. */ 1304 restore_msa(current); 1305 1306 /* Restore the scalar FP control & status register */ 1307 if (!was_fpu_owner) 1308 write_32bit_cp1_register(CP1_STATUS, 1309 current->thread.fpu.fcr31); 1310 } 1311 1312 out: 1313 preempt_enable(); 1314 1315 return 0; 1316 } 1317 1318 asmlinkage void do_cpu(struct pt_regs *regs) 1319 { 1320 enum ctx_state prev_state; 1321 unsigned int __user *epc; 1322 unsigned long old_epc, old31; 1323 void __user *fault_addr; 1324 unsigned int opcode; 1325 unsigned long fcr31; 1326 unsigned int cpid; 1327 int status, err; 1328 unsigned long __maybe_unused flags; 1329 int sig; 1330 1331 prev_state = exception_enter(); 1332 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1333 1334 if (cpid != 2) 1335 die_if_kernel("do_cpu invoked from kernel context!", regs); 1336 1337 switch (cpid) { 1338 case 0: 1339 epc = (unsigned int __user *)exception_epc(regs); 1340 old_epc = regs->cp0_epc; 1341 old31 = regs->regs[31]; 1342 opcode = 0; 1343 status = -1; 1344 1345 if (unlikely(compute_return_epc(regs) < 0)) 1346 break; 1347 1348 if (get_isa16_mode(regs->cp0_epc)) { 1349 unsigned short mmop[2] = { 0 }; 1350 1351 if (unlikely(get_user(mmop[0], epc) < 0)) 1352 status = SIGSEGV; 1353 if (unlikely(get_user(mmop[1], epc) < 0)) 1354 status = SIGSEGV; 1355 opcode = (mmop[0] << 16) | mmop[1]; 1356 1357 if (status < 0) 1358 status = simulate_rdhwr_mm(regs, opcode); 1359 } else { 1360 if (unlikely(get_user(opcode, epc) < 0)) 1361 status = SIGSEGV; 1362 1363 if (!cpu_has_llsc && status < 0) 1364 status = simulate_llsc(regs, opcode); 1365 1366 if (status < 0) 1367 status = simulate_rdhwr_normal(regs, opcode); 1368 } 1369 1370 if (status < 0) 1371 status = SIGILL; 1372 1373 if (unlikely(status > 0)) { 1374 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1375 regs->regs[31] = old31; 1376 force_sig(status, current); 1377 } 1378 1379 break; 1380 1381 case 3: 1382 /* 1383 * The COP3 opcode space and consequently the CP0.Status.CU3 1384 * bit and the CP0.Cause.CE=3 encoding have been removed as 1385 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1386 * up the space has been reused for COP1X instructions, that 1387 * are enabled by the CP0.Status.CU1 bit and consequently 1388 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1389 * exceptions. Some FPU-less processors that implement one 1390 * of these ISAs however use this code erroneously for COP1X 1391 * instructions. Therefore we redirect this trap to the FP 1392 * emulator too. 1393 */ 1394 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1395 force_sig(SIGILL, current); 1396 break; 1397 } 1398 /* Fall through. */ 1399 1400 case 1: 1401 err = enable_restore_fp_context(0); 1402 1403 if (raw_cpu_has_fpu && !err) 1404 break; 1405 1406 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1407 &fault_addr); 1408 fcr31 = current->thread.fpu.fcr31; 1409 1410 /* 1411 * We can't allow the emulated instruction to leave 1412 * any of the cause bits set in $fcr31. 1413 */ 1414 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 1415 1416 /* Send a signal if required. */ 1417 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1418 mt_ase_fp_affinity(); 1419 1420 break; 1421 1422 case 2: 1423 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1424 break; 1425 } 1426 1427 exception_exit(prev_state); 1428 } 1429 1430 asmlinkage void do_msa_fpe(struct pt_regs *regs) 1431 { 1432 enum ctx_state prev_state; 1433 1434 prev_state = exception_enter(); 1435 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1436 force_sig(SIGFPE, current); 1437 exception_exit(prev_state); 1438 } 1439 1440 asmlinkage void do_msa(struct pt_regs *regs) 1441 { 1442 enum ctx_state prev_state; 1443 int err; 1444 1445 prev_state = exception_enter(); 1446 1447 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1448 force_sig(SIGILL, current); 1449 goto out; 1450 } 1451 1452 die_if_kernel("do_msa invoked from kernel context!", regs); 1453 1454 err = enable_restore_fp_context(1); 1455 if (err) 1456 force_sig(SIGILL, current); 1457 out: 1458 exception_exit(prev_state); 1459 } 1460 1461 asmlinkage void do_mdmx(struct pt_regs *regs) 1462 { 1463 enum ctx_state prev_state; 1464 1465 prev_state = exception_enter(); 1466 force_sig(SIGILL, current); 1467 exception_exit(prev_state); 1468 } 1469 1470 /* 1471 * Called with interrupts disabled. 1472 */ 1473 asmlinkage void do_watch(struct pt_regs *regs) 1474 { 1475 enum ctx_state prev_state; 1476 u32 cause; 1477 1478 prev_state = exception_enter(); 1479 /* 1480 * Clear WP (bit 22) bit of cause register so we don't loop 1481 * forever. 1482 */ 1483 cause = read_c0_cause(); 1484 cause &= ~(1 << 22); 1485 write_c0_cause(cause); 1486 1487 /* 1488 * If the current thread has the watch registers loaded, save 1489 * their values and send SIGTRAP. Otherwise another thread 1490 * left the registers set, clear them and continue. 1491 */ 1492 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1493 mips_read_watch_registers(); 1494 local_irq_enable(); 1495 force_sig(SIGTRAP, current); 1496 } else { 1497 mips_clear_watch_registers(); 1498 local_irq_enable(); 1499 } 1500 exception_exit(prev_state); 1501 } 1502 1503 asmlinkage void do_mcheck(struct pt_regs *regs) 1504 { 1505 const int field = 2 * sizeof(unsigned long); 1506 int multi_match = regs->cp0_status & ST0_TS; 1507 enum ctx_state prev_state; 1508 1509 prev_state = exception_enter(); 1510 show_regs(regs); 1511 1512 if (multi_match) { 1513 pr_err("Index : %0x\n", read_c0_index()); 1514 pr_err("Pagemask: %0x\n", read_c0_pagemask()); 1515 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1516 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1517 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1518 pr_err("Wired : %0x\n", read_c0_wired()); 1519 pr_err("Pagegrain: %0x\n", read_c0_pagegrain()); 1520 if (cpu_has_htw) { 1521 pr_err("PWField : %0*lx\n", field, read_c0_pwfield()); 1522 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize()); 1523 pr_err("PWCtl : %0x\n", read_c0_pwctl()); 1524 } 1525 pr_err("\n"); 1526 dump_tlb_all(); 1527 } 1528 1529 show_code((unsigned int __user *) regs->cp0_epc); 1530 1531 /* 1532 * Some chips may have other causes of machine check (e.g. SB1 1533 * graduation timer) 1534 */ 1535 panic("Caught Machine Check exception - %scaused by multiple " 1536 "matching entries in the TLB.", 1537 (multi_match) ? "" : "not "); 1538 } 1539 1540 asmlinkage void do_mt(struct pt_regs *regs) 1541 { 1542 int subcode; 1543 1544 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1545 >> VPECONTROL_EXCPT_SHIFT; 1546 switch (subcode) { 1547 case 0: 1548 printk(KERN_DEBUG "Thread Underflow\n"); 1549 break; 1550 case 1: 1551 printk(KERN_DEBUG "Thread Overflow\n"); 1552 break; 1553 case 2: 1554 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1555 break; 1556 case 3: 1557 printk(KERN_DEBUG "Gating Storage Exception\n"); 1558 break; 1559 case 4: 1560 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1561 break; 1562 case 5: 1563 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1564 break; 1565 default: 1566 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1567 subcode); 1568 break; 1569 } 1570 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1571 1572 force_sig(SIGILL, current); 1573 } 1574 1575 1576 asmlinkage void do_dsp(struct pt_regs *regs) 1577 { 1578 if (cpu_has_dsp) 1579 panic("Unexpected DSP exception"); 1580 1581 force_sig(SIGILL, current); 1582 } 1583 1584 asmlinkage void do_reserved(struct pt_regs *regs) 1585 { 1586 /* 1587 * Game over - no way to handle this if it ever occurs. Most probably 1588 * caused by a new unknown cpu type or after another deadly 1589 * hard/software error. 1590 */ 1591 show_regs(regs); 1592 panic("Caught reserved exception %ld - should not happen.", 1593 (regs->cp0_cause & 0x7f) >> 2); 1594 } 1595 1596 static int __initdata l1parity = 1; 1597 static int __init nol1parity(char *s) 1598 { 1599 l1parity = 0; 1600 return 1; 1601 } 1602 __setup("nol1par", nol1parity); 1603 static int __initdata l2parity = 1; 1604 static int __init nol2parity(char *s) 1605 { 1606 l2parity = 0; 1607 return 1; 1608 } 1609 __setup("nol2par", nol2parity); 1610 1611 /* 1612 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1613 * it different ways. 1614 */ 1615 static inline void parity_protection_init(void) 1616 { 1617 switch (current_cpu_type()) { 1618 case CPU_24K: 1619 case CPU_34K: 1620 case CPU_74K: 1621 case CPU_1004K: 1622 case CPU_1074K: 1623 case CPU_INTERAPTIV: 1624 case CPU_PROAPTIV: 1625 case CPU_P5600: 1626 case CPU_QEMU_GENERIC: 1627 { 1628 #define ERRCTL_PE 0x80000000 1629 #define ERRCTL_L2P 0x00800000 1630 unsigned long errctl; 1631 unsigned int l1parity_present, l2parity_present; 1632 1633 errctl = read_c0_ecc(); 1634 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1635 1636 /* probe L1 parity support */ 1637 write_c0_ecc(errctl | ERRCTL_PE); 1638 back_to_back_c0_hazard(); 1639 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1640 1641 /* probe L2 parity support */ 1642 write_c0_ecc(errctl|ERRCTL_L2P); 1643 back_to_back_c0_hazard(); 1644 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1645 1646 if (l1parity_present && l2parity_present) { 1647 if (l1parity) 1648 errctl |= ERRCTL_PE; 1649 if (l1parity ^ l2parity) 1650 errctl |= ERRCTL_L2P; 1651 } else if (l1parity_present) { 1652 if (l1parity) 1653 errctl |= ERRCTL_PE; 1654 } else if (l2parity_present) { 1655 if (l2parity) 1656 errctl |= ERRCTL_L2P; 1657 } else { 1658 /* No parity available */ 1659 } 1660 1661 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1662 1663 write_c0_ecc(errctl); 1664 back_to_back_c0_hazard(); 1665 errctl = read_c0_ecc(); 1666 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1667 1668 if (l1parity_present) 1669 printk(KERN_INFO "Cache parity protection %sabled\n", 1670 (errctl & ERRCTL_PE) ? "en" : "dis"); 1671 1672 if (l2parity_present) { 1673 if (l1parity_present && l1parity) 1674 errctl ^= ERRCTL_L2P; 1675 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1676 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1677 } 1678 } 1679 break; 1680 1681 case CPU_5KC: 1682 case CPU_5KE: 1683 case CPU_LOONGSON1: 1684 write_c0_ecc(0x80000000); 1685 back_to_back_c0_hazard(); 1686 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1687 printk(KERN_INFO "Cache parity protection %sabled\n", 1688 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1689 break; 1690 case CPU_20KC: 1691 case CPU_25KF: 1692 /* Clear the DE bit (bit 16) in the c0_status register. */ 1693 printk(KERN_INFO "Enable cache parity protection for " 1694 "MIPS 20KC/25KF CPUs.\n"); 1695 clear_c0_status(ST0_DE); 1696 break; 1697 default: 1698 break; 1699 } 1700 } 1701 1702 asmlinkage void cache_parity_error(void) 1703 { 1704 const int field = 2 * sizeof(unsigned long); 1705 unsigned int reg_val; 1706 1707 /* For the moment, report the problem and hang. */ 1708 printk("Cache error exception:\n"); 1709 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1710 reg_val = read_c0_cacheerr(); 1711 printk("c0_cacheerr == %08x\n", reg_val); 1712 1713 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1714 reg_val & (1<<30) ? "secondary" : "primary", 1715 reg_val & (1<<31) ? "data" : "insn"); 1716 if ((cpu_has_mips_r2_r6) && 1717 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1718 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1719 reg_val & (1<<29) ? "ED " : "", 1720 reg_val & (1<<28) ? "ET " : "", 1721 reg_val & (1<<27) ? "ES " : "", 1722 reg_val & (1<<26) ? "EE " : "", 1723 reg_val & (1<<25) ? "EB " : "", 1724 reg_val & (1<<24) ? "EI " : "", 1725 reg_val & (1<<23) ? "E1 " : "", 1726 reg_val & (1<<22) ? "E0 " : ""); 1727 } else { 1728 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1729 reg_val & (1<<29) ? "ED " : "", 1730 reg_val & (1<<28) ? "ET " : "", 1731 reg_val & (1<<26) ? "EE " : "", 1732 reg_val & (1<<25) ? "EB " : "", 1733 reg_val & (1<<24) ? "EI " : "", 1734 reg_val & (1<<23) ? "E1 " : "", 1735 reg_val & (1<<22) ? "E0 " : ""); 1736 } 1737 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1738 1739 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1740 if (reg_val & (1<<22)) 1741 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1742 1743 if (reg_val & (1<<23)) 1744 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1745 #endif 1746 1747 panic("Can't handle the cache error!"); 1748 } 1749 1750 asmlinkage void do_ftlb(void) 1751 { 1752 const int field = 2 * sizeof(unsigned long); 1753 unsigned int reg_val; 1754 1755 /* For the moment, report the problem and hang. */ 1756 if ((cpu_has_mips_r2_r6) && 1757 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1758 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1759 read_c0_ecc()); 1760 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1761 reg_val = read_c0_cacheerr(); 1762 pr_err("c0_cacheerr == %08x\n", reg_val); 1763 1764 if ((reg_val & 0xc0000000) == 0xc0000000) { 1765 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1766 } else { 1767 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1768 reg_val & (1<<30) ? "secondary" : "primary", 1769 reg_val & (1<<31) ? "data" : "insn"); 1770 } 1771 } else { 1772 pr_err("FTLB error exception\n"); 1773 } 1774 /* Just print the cacheerr bits for now */ 1775 cache_parity_error(); 1776 } 1777 1778 /* 1779 * SDBBP EJTAG debug exception handler. 1780 * We skip the instruction and return to the next instruction. 1781 */ 1782 void ejtag_exception_handler(struct pt_regs *regs) 1783 { 1784 const int field = 2 * sizeof(unsigned long); 1785 unsigned long depc, old_epc, old_ra; 1786 unsigned int debug; 1787 1788 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1789 depc = read_c0_depc(); 1790 debug = read_c0_debug(); 1791 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1792 if (debug & 0x80000000) { 1793 /* 1794 * In branch delay slot. 1795 * We cheat a little bit here and use EPC to calculate the 1796 * debug return address (DEPC). EPC is restored after the 1797 * calculation. 1798 */ 1799 old_epc = regs->cp0_epc; 1800 old_ra = regs->regs[31]; 1801 regs->cp0_epc = depc; 1802 compute_return_epc(regs); 1803 depc = regs->cp0_epc; 1804 regs->cp0_epc = old_epc; 1805 regs->regs[31] = old_ra; 1806 } else 1807 depc += 4; 1808 write_c0_depc(depc); 1809 1810 #if 0 1811 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1812 write_c0_debug(debug | 0x100); 1813 #endif 1814 } 1815 1816 /* 1817 * NMI exception handler. 1818 * No lock; only written during early bootup by CPU 0. 1819 */ 1820 static RAW_NOTIFIER_HEAD(nmi_chain); 1821 1822 int register_nmi_notifier(struct notifier_block *nb) 1823 { 1824 return raw_notifier_chain_register(&nmi_chain, nb); 1825 } 1826 1827 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1828 { 1829 char str[100]; 1830 1831 raw_notifier_call_chain(&nmi_chain, 0, regs); 1832 bust_spinlocks(1); 1833 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1834 smp_processor_id(), regs->cp0_epc); 1835 regs->cp0_epc = read_c0_errorepc(); 1836 die(str, regs); 1837 } 1838 1839 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1840 1841 unsigned long ebase; 1842 unsigned long exception_handlers[32]; 1843 unsigned long vi_handlers[64]; 1844 1845 void __init *set_except_vector(int n, void *addr) 1846 { 1847 unsigned long handler = (unsigned long) addr; 1848 unsigned long old_handler; 1849 1850 #ifdef CONFIG_CPU_MICROMIPS 1851 /* 1852 * Only the TLB handlers are cache aligned with an even 1853 * address. All other handlers are on an odd address and 1854 * require no modification. Otherwise, MIPS32 mode will 1855 * be entered when handling any TLB exceptions. That 1856 * would be bad...since we must stay in microMIPS mode. 1857 */ 1858 if (!(handler & 0x1)) 1859 handler |= 1; 1860 #endif 1861 old_handler = xchg(&exception_handlers[n], handler); 1862 1863 if (n == 0 && cpu_has_divec) { 1864 #ifdef CONFIG_CPU_MICROMIPS 1865 unsigned long jump_mask = ~((1 << 27) - 1); 1866 #else 1867 unsigned long jump_mask = ~((1 << 28) - 1); 1868 #endif 1869 u32 *buf = (u32 *)(ebase + 0x200); 1870 unsigned int k0 = 26; 1871 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1872 uasm_i_j(&buf, handler & ~jump_mask); 1873 uasm_i_nop(&buf); 1874 } else { 1875 UASM_i_LA(&buf, k0, handler); 1876 uasm_i_jr(&buf, k0); 1877 uasm_i_nop(&buf); 1878 } 1879 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1880 } 1881 return (void *)old_handler; 1882 } 1883 1884 static void do_default_vi(void) 1885 { 1886 show_regs(get_irq_regs()); 1887 panic("Caught unexpected vectored interrupt."); 1888 } 1889 1890 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1891 { 1892 unsigned long handler; 1893 unsigned long old_handler = vi_handlers[n]; 1894 int srssets = current_cpu_data.srsets; 1895 u16 *h; 1896 unsigned char *b; 1897 1898 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1899 1900 if (addr == NULL) { 1901 handler = (unsigned long) do_default_vi; 1902 srs = 0; 1903 } else 1904 handler = (unsigned long) addr; 1905 vi_handlers[n] = handler; 1906 1907 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1908 1909 if (srs >= srssets) 1910 panic("Shadow register set %d not supported", srs); 1911 1912 if (cpu_has_veic) { 1913 if (board_bind_eic_interrupt) 1914 board_bind_eic_interrupt(n, srs); 1915 } else if (cpu_has_vint) { 1916 /* SRSMap is only defined if shadow sets are implemented */ 1917 if (srssets > 1) 1918 change_c0_srsmap(0xf << n*4, srs << n*4); 1919 } 1920 1921 if (srs == 0) { 1922 /* 1923 * If no shadow set is selected then use the default handler 1924 * that does normal register saving and standard interrupt exit 1925 */ 1926 extern char except_vec_vi, except_vec_vi_lui; 1927 extern char except_vec_vi_ori, except_vec_vi_end; 1928 extern char rollback_except_vec_vi; 1929 char *vec_start = using_rollback_handler() ? 1930 &rollback_except_vec_vi : &except_vec_vi; 1931 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1932 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1933 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1934 #else 1935 const int lui_offset = &except_vec_vi_lui - vec_start; 1936 const int ori_offset = &except_vec_vi_ori - vec_start; 1937 #endif 1938 const int handler_len = &except_vec_vi_end - vec_start; 1939 1940 if (handler_len > VECTORSPACING) { 1941 /* 1942 * Sigh... panicing won't help as the console 1943 * is probably not configured :( 1944 */ 1945 panic("VECTORSPACING too small"); 1946 } 1947 1948 set_handler(((unsigned long)b - ebase), vec_start, 1949 #ifdef CONFIG_CPU_MICROMIPS 1950 (handler_len - 1)); 1951 #else 1952 handler_len); 1953 #endif 1954 h = (u16 *)(b + lui_offset); 1955 *h = (handler >> 16) & 0xffff; 1956 h = (u16 *)(b + ori_offset); 1957 *h = (handler & 0xffff); 1958 local_flush_icache_range((unsigned long)b, 1959 (unsigned long)(b+handler_len)); 1960 } 1961 else { 1962 /* 1963 * In other cases jump directly to the interrupt handler. It 1964 * is the handler's responsibility to save registers if required 1965 * (eg hi/lo) and return from the exception using "eret". 1966 */ 1967 u32 insn; 1968 1969 h = (u16 *)b; 1970 /* j handler */ 1971 #ifdef CONFIG_CPU_MICROMIPS 1972 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 1973 #else 1974 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 1975 #endif 1976 h[0] = (insn >> 16) & 0xffff; 1977 h[1] = insn & 0xffff; 1978 h[2] = 0; 1979 h[3] = 0; 1980 local_flush_icache_range((unsigned long)b, 1981 (unsigned long)(b+8)); 1982 } 1983 1984 return (void *)old_handler; 1985 } 1986 1987 void *set_vi_handler(int n, vi_handler_t addr) 1988 { 1989 return set_vi_srs_handler(n, addr, 0); 1990 } 1991 1992 extern void tlb_init(void); 1993 1994 /* 1995 * Timer interrupt 1996 */ 1997 int cp0_compare_irq; 1998 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1999 int cp0_compare_irq_shift; 2000 2001 /* 2002 * Performance counter IRQ or -1 if shared with timer 2003 */ 2004 int cp0_perfcount_irq; 2005 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2006 2007 /* 2008 * Fast debug channel IRQ or -1 if not present 2009 */ 2010 int cp0_fdc_irq; 2011 EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2012 2013 static int noulri; 2014 2015 static int __init ulri_disable(char *s) 2016 { 2017 pr_info("Disabling ulri\n"); 2018 noulri = 1; 2019 2020 return 1; 2021 } 2022 __setup("noulri", ulri_disable); 2023 2024 /* configure STATUS register */ 2025 static void configure_status(void) 2026 { 2027 /* 2028 * Disable coprocessors and select 32-bit or 64-bit addressing 2029 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2030 * flag that some firmware may have left set and the TS bit (for 2031 * IP27). Set XX for ISA IV code to work. 2032 */ 2033 unsigned int status_set = ST0_CU0; 2034 #ifdef CONFIG_64BIT 2035 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2036 #endif 2037 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2038 status_set |= ST0_XX; 2039 if (cpu_has_dsp) 2040 status_set |= ST0_MX; 2041 2042 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2043 status_set); 2044 } 2045 2046 /* configure HWRENA register */ 2047 static void configure_hwrena(void) 2048 { 2049 unsigned int hwrena = cpu_hwrena_impl_bits; 2050 2051 if (cpu_has_mips_r2_r6) 2052 hwrena |= 0x0000000f; 2053 2054 if (!noulri && cpu_has_userlocal) 2055 hwrena |= (1 << 29); 2056 2057 if (hwrena) 2058 write_c0_hwrena(hwrena); 2059 } 2060 2061 static void configure_exception_vector(void) 2062 { 2063 if (cpu_has_veic || cpu_has_vint) { 2064 unsigned long sr = set_c0_status(ST0_BEV); 2065 write_c0_ebase(ebase); 2066 write_c0_status(sr); 2067 /* Setting vector spacing enables EI/VI mode */ 2068 change_c0_intctl(0x3e0, VECTORSPACING); 2069 } 2070 if (cpu_has_divec) { 2071 if (cpu_has_mipsmt) { 2072 unsigned int vpflags = dvpe(); 2073 set_c0_cause(CAUSEF_IV); 2074 evpe(vpflags); 2075 } else 2076 set_c0_cause(CAUSEF_IV); 2077 } 2078 } 2079 2080 void per_cpu_trap_init(bool is_boot_cpu) 2081 { 2082 unsigned int cpu = smp_processor_id(); 2083 2084 configure_status(); 2085 configure_hwrena(); 2086 2087 configure_exception_vector(); 2088 2089 /* 2090 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2091 * 2092 * o read IntCtl.IPTI to determine the timer interrupt 2093 * o read IntCtl.IPPCI to determine the performance counter interrupt 2094 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2095 */ 2096 if (cpu_has_mips_r2_r6) { 2097 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2098 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2099 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2100 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2101 if (!cp0_fdc_irq) 2102 cp0_fdc_irq = -1; 2103 2104 } else { 2105 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2106 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2107 cp0_perfcount_irq = -1; 2108 cp0_fdc_irq = -1; 2109 } 2110 2111 if (!cpu_data[cpu].asid_cache) 2112 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 2113 2114 atomic_inc(&init_mm.mm_count); 2115 current->active_mm = &init_mm; 2116 BUG_ON(current->mm); 2117 enter_lazy_tlb(&init_mm, current); 2118 2119 /* Boot CPU's cache setup in setup_arch(). */ 2120 if (!is_boot_cpu) 2121 cpu_cache_init(); 2122 tlb_init(); 2123 TLBMISS_HANDLER_SETUP(); 2124 } 2125 2126 /* Install CPU exception handler */ 2127 void set_handler(unsigned long offset, void *addr, unsigned long size) 2128 { 2129 #ifdef CONFIG_CPU_MICROMIPS 2130 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2131 #else 2132 memcpy((void *)(ebase + offset), addr, size); 2133 #endif 2134 local_flush_icache_range(ebase + offset, ebase + offset + size); 2135 } 2136 2137 static char panic_null_cerr[] = 2138 "Trying to set NULL cache error exception handler"; 2139 2140 /* 2141 * Install uncached CPU exception handler. 2142 * This is suitable only for the cache error exception which is the only 2143 * exception handler that is being run uncached. 2144 */ 2145 void set_uncached_handler(unsigned long offset, void *addr, 2146 unsigned long size) 2147 { 2148 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2149 2150 if (!addr) 2151 panic(panic_null_cerr); 2152 2153 memcpy((void *)(uncached_ebase + offset), addr, size); 2154 } 2155 2156 static int __initdata rdhwr_noopt; 2157 static int __init set_rdhwr_noopt(char *str) 2158 { 2159 rdhwr_noopt = 1; 2160 return 1; 2161 } 2162 2163 __setup("rdhwr_noopt", set_rdhwr_noopt); 2164 2165 void __init trap_init(void) 2166 { 2167 extern char except_vec3_generic; 2168 extern char except_vec4; 2169 extern char except_vec3_r4000; 2170 unsigned long i; 2171 2172 check_wait(); 2173 2174 #if defined(CONFIG_KGDB) 2175 if (kgdb_early_setup) 2176 return; /* Already done */ 2177 #endif 2178 2179 if (cpu_has_veic || cpu_has_vint) { 2180 unsigned long size = 0x200 + VECTORSPACING*64; 2181 ebase = (unsigned long) 2182 __alloc_bootmem(size, 1 << fls(size), 0); 2183 } else { 2184 #ifdef CONFIG_KVM_GUEST 2185 #define KVM_GUEST_KSEG0 0x40000000 2186 ebase = KVM_GUEST_KSEG0; 2187 #else 2188 ebase = CKSEG0; 2189 #endif 2190 if (cpu_has_mips_r2_r6) 2191 ebase += (read_c0_ebase() & 0x3ffff000); 2192 } 2193 2194 if (cpu_has_mmips) { 2195 unsigned int config3 = read_c0_config3(); 2196 2197 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2198 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2199 else 2200 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2201 } 2202 2203 if (board_ebase_setup) 2204 board_ebase_setup(); 2205 per_cpu_trap_init(true); 2206 2207 /* 2208 * Copy the generic exception handlers to their final destination. 2209 * This will be overriden later as suitable for a particular 2210 * configuration. 2211 */ 2212 set_handler(0x180, &except_vec3_generic, 0x80); 2213 2214 /* 2215 * Setup default vectors 2216 */ 2217 for (i = 0; i <= 31; i++) 2218 set_except_vector(i, handle_reserved); 2219 2220 /* 2221 * Copy the EJTAG debug exception vector handler code to it's final 2222 * destination. 2223 */ 2224 if (cpu_has_ejtag && board_ejtag_handler_setup) 2225 board_ejtag_handler_setup(); 2226 2227 /* 2228 * Only some CPUs have the watch exceptions. 2229 */ 2230 if (cpu_has_watch) 2231 set_except_vector(23, handle_watch); 2232 2233 /* 2234 * Initialise interrupt handlers 2235 */ 2236 if (cpu_has_veic || cpu_has_vint) { 2237 int nvec = cpu_has_veic ? 64 : 8; 2238 for (i = 0; i < nvec; i++) 2239 set_vi_handler(i, NULL); 2240 } 2241 else if (cpu_has_divec) 2242 set_handler(0x200, &except_vec4, 0x8); 2243 2244 /* 2245 * Some CPUs can enable/disable for cache parity detection, but does 2246 * it different ways. 2247 */ 2248 parity_protection_init(); 2249 2250 /* 2251 * The Data Bus Errors / Instruction Bus Errors are signaled 2252 * by external hardware. Therefore these two exceptions 2253 * may have board specific handlers. 2254 */ 2255 if (board_be_init) 2256 board_be_init(); 2257 2258 set_except_vector(0, using_rollback_handler() ? rollback_handle_int 2259 : handle_int); 2260 set_except_vector(1, handle_tlbm); 2261 set_except_vector(2, handle_tlbl); 2262 set_except_vector(3, handle_tlbs); 2263 2264 set_except_vector(4, handle_adel); 2265 set_except_vector(5, handle_ades); 2266 2267 set_except_vector(6, handle_ibe); 2268 set_except_vector(7, handle_dbe); 2269 2270 set_except_vector(8, handle_sys); 2271 set_except_vector(9, handle_bp); 2272 set_except_vector(10, rdhwr_noopt ? handle_ri : 2273 (cpu_has_vtag_icache ? 2274 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 2275 set_except_vector(11, handle_cpu); 2276 set_except_vector(12, handle_ov); 2277 set_except_vector(13, handle_tr); 2278 set_except_vector(14, handle_msa_fpe); 2279 2280 if (current_cpu_type() == CPU_R6000 || 2281 current_cpu_type() == CPU_R6000A) { 2282 /* 2283 * The R6000 is the only R-series CPU that features a machine 2284 * check exception (similar to the R4000 cache error) and 2285 * unaligned ldc1/sdc1 exception. The handlers have not been 2286 * written yet. Well, anyway there is no R6000 machine on the 2287 * current list of targets for Linux/MIPS. 2288 * (Duh, crap, there is someone with a triple R6k machine) 2289 */ 2290 //set_except_vector(14, handle_mc); 2291 //set_except_vector(15, handle_ndc); 2292 } 2293 2294 2295 if (board_nmi_handler_setup) 2296 board_nmi_handler_setup(); 2297 2298 if (cpu_has_fpu && !cpu_has_nofpuex) 2299 set_except_vector(15, handle_fpe); 2300 2301 set_except_vector(16, handle_ftlb); 2302 2303 if (cpu_has_rixiex) { 2304 set_except_vector(19, tlb_do_page_fault_0); 2305 set_except_vector(20, tlb_do_page_fault_0); 2306 } 2307 2308 set_except_vector(21, handle_msa); 2309 set_except_vector(22, handle_mdmx); 2310 2311 if (cpu_has_mcheck) 2312 set_except_vector(24, handle_mcheck); 2313 2314 if (cpu_has_mipsmt) 2315 set_except_vector(25, handle_mt); 2316 2317 set_except_vector(26, handle_dsp); 2318 2319 if (board_cache_error_setup) 2320 board_cache_error_setup(); 2321 2322 if (cpu_has_vce) 2323 /* Special exception: R4[04]00 uses also the divec space. */ 2324 set_handler(0x180, &except_vec3_r4000, 0x100); 2325 else if (cpu_has_4kex) 2326 set_handler(0x180, &except_vec3_generic, 0x80); 2327 else 2328 set_handler(0x080, &except_vec3_generic, 0x80); 2329 2330 local_flush_icache_range(ebase, ebase + 0x400); 2331 2332 sort_extable(__start___dbe_table, __stop___dbe_table); 2333 2334 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2335 } 2336 2337 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2338 void *v) 2339 { 2340 switch (cmd) { 2341 case CPU_PM_ENTER_FAILED: 2342 case CPU_PM_EXIT: 2343 configure_status(); 2344 configure_hwrena(); 2345 configure_exception_vector(); 2346 2347 /* Restore register with CPU number for TLB handlers */ 2348 TLBMISS_HANDLER_RESTORE(); 2349 2350 break; 2351 } 2352 2353 return NOTIFY_OK; 2354 } 2355 2356 static struct notifier_block trap_pm_notifier_block = { 2357 .notifier_call = trap_pm_notifier, 2358 }; 2359 2360 static int __init trap_pm_init(void) 2361 { 2362 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2363 } 2364 arch_initcall(trap_pm_init); 2365