1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15 #include <linux/bug.h> 16 #include <linux/compiler.h> 17 #include <linux/context_tracking.h> 18 #include <linux/cpu_pm.h> 19 #include <linux/kexec.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mm.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/spinlock.h> 27 #include <linux/kallsyms.h> 28 #include <linux/bootmem.h> 29 #include <linux/interrupt.h> 30 #include <linux/ptrace.h> 31 #include <linux/kgdb.h> 32 #include <linux/kdebug.h> 33 #include <linux/kprobes.h> 34 #include <linux/notifier.h> 35 #include <linux/kdb.h> 36 #include <linux/irq.h> 37 #include <linux/perf_event.h> 38 39 #include <asm/bootinfo.h> 40 #include <asm/branch.h> 41 #include <asm/break.h> 42 #include <asm/cop2.h> 43 #include <asm/cpu.h> 44 #include <asm/cpu-type.h> 45 #include <asm/dsp.h> 46 #include <asm/fpu.h> 47 #include <asm/fpu_emulator.h> 48 #include <asm/idle.h> 49 #include <asm/mipsregs.h> 50 #include <asm/mipsmtregs.h> 51 #include <asm/module.h> 52 #include <asm/msa.h> 53 #include <asm/pgtable.h> 54 #include <asm/ptrace.h> 55 #include <asm/sections.h> 56 #include <asm/tlbdebug.h> 57 #include <asm/traps.h> 58 #include <asm/uaccess.h> 59 #include <asm/watch.h> 60 #include <asm/mmu_context.h> 61 #include <asm/types.h> 62 #include <asm/stacktrace.h> 63 #include <asm/uasm.h> 64 65 extern void check_wait(void); 66 extern asmlinkage void rollback_handle_int(void); 67 extern asmlinkage void handle_int(void); 68 extern u32 handle_tlbl[]; 69 extern u32 handle_tlbs[]; 70 extern u32 handle_tlbm[]; 71 extern asmlinkage void handle_adel(void); 72 extern asmlinkage void handle_ades(void); 73 extern asmlinkage void handle_ibe(void); 74 extern asmlinkage void handle_dbe(void); 75 extern asmlinkage void handle_sys(void); 76 extern asmlinkage void handle_bp(void); 77 extern asmlinkage void handle_ri(void); 78 extern asmlinkage void handle_ri_rdhwr_vivt(void); 79 extern asmlinkage void handle_ri_rdhwr(void); 80 extern asmlinkage void handle_cpu(void); 81 extern asmlinkage void handle_ov(void); 82 extern asmlinkage void handle_tr(void); 83 extern asmlinkage void handle_msa_fpe(void); 84 extern asmlinkage void handle_fpe(void); 85 extern asmlinkage void handle_ftlb(void); 86 extern asmlinkage void handle_msa(void); 87 extern asmlinkage void handle_mdmx(void); 88 extern asmlinkage void handle_watch(void); 89 extern asmlinkage void handle_mt(void); 90 extern asmlinkage void handle_dsp(void); 91 extern asmlinkage void handle_mcheck(void); 92 extern asmlinkage void handle_reserved(void); 93 94 void (*board_be_init)(void); 95 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 96 void (*board_nmi_handler_setup)(void); 97 void (*board_ejtag_handler_setup)(void); 98 void (*board_bind_eic_interrupt)(int irq, int regset); 99 void (*board_ebase_setup)(void); 100 void(*board_cache_error_setup)(void); 101 102 static void show_raw_backtrace(unsigned long reg29) 103 { 104 unsigned long *sp = (unsigned long *)(reg29 & ~3); 105 unsigned long addr; 106 107 printk("Call Trace:"); 108 #ifdef CONFIG_KALLSYMS 109 printk("\n"); 110 #endif 111 while (!kstack_end(sp)) { 112 unsigned long __user *p = 113 (unsigned long __user *)(unsigned long)sp++; 114 if (__get_user(addr, p)) { 115 printk(" (Bad stack address)"); 116 break; 117 } 118 if (__kernel_text_address(addr)) 119 print_ip_sym(addr); 120 } 121 printk("\n"); 122 } 123 124 #ifdef CONFIG_KALLSYMS 125 int raw_show_trace; 126 static int __init set_raw_show_trace(char *str) 127 { 128 raw_show_trace = 1; 129 return 1; 130 } 131 __setup("raw_show_trace", set_raw_show_trace); 132 #endif 133 134 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 135 { 136 unsigned long sp = regs->regs[29]; 137 unsigned long ra = regs->regs[31]; 138 unsigned long pc = regs->cp0_epc; 139 140 if (!task) 141 task = current; 142 143 if (raw_show_trace || !__kernel_text_address(pc)) { 144 show_raw_backtrace(sp); 145 return; 146 } 147 printk("Call Trace:\n"); 148 do { 149 print_ip_sym(pc); 150 pc = unwind_stack(task, &sp, pc, &ra); 151 } while (pc); 152 printk("\n"); 153 } 154 155 /* 156 * This routine abuses get_user()/put_user() to reference pointers 157 * with at least a bit of error checking ... 158 */ 159 static void show_stacktrace(struct task_struct *task, 160 const struct pt_regs *regs) 161 { 162 const int field = 2 * sizeof(unsigned long); 163 long stackdata; 164 int i; 165 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 166 167 printk("Stack :"); 168 i = 0; 169 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 170 if (i && ((i % (64 / field)) == 0)) 171 printk("\n "); 172 if (i > 39) { 173 printk(" ..."); 174 break; 175 } 176 177 if (__get_user(stackdata, sp++)) { 178 printk(" (Bad stack address)"); 179 break; 180 } 181 182 printk(" %0*lx", field, stackdata); 183 i++; 184 } 185 printk("\n"); 186 show_backtrace(task, regs); 187 } 188 189 void show_stack(struct task_struct *task, unsigned long *sp) 190 { 191 struct pt_regs regs; 192 if (sp) { 193 regs.regs[29] = (unsigned long)sp; 194 regs.regs[31] = 0; 195 regs.cp0_epc = 0; 196 } else { 197 if (task && task != current) { 198 regs.regs[29] = task->thread.reg29; 199 regs.regs[31] = 0; 200 regs.cp0_epc = task->thread.reg31; 201 #ifdef CONFIG_KGDB_KDB 202 } else if (atomic_read(&kgdb_active) != -1 && 203 kdb_current_regs) { 204 memcpy(®s, kdb_current_regs, sizeof(regs)); 205 #endif /* CONFIG_KGDB_KDB */ 206 } else { 207 prepare_frametrace(®s); 208 } 209 } 210 show_stacktrace(task, ®s); 211 } 212 213 static void show_code(unsigned int __user *pc) 214 { 215 long i; 216 unsigned short __user *pc16 = NULL; 217 218 printk("\nCode:"); 219 220 if ((unsigned long)pc & 1) 221 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 222 for(i = -3 ; i < 6 ; i++) { 223 unsigned int insn; 224 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 225 printk(" (Bad address in epc)\n"); 226 break; 227 } 228 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 229 } 230 } 231 232 static void __show_regs(const struct pt_regs *regs) 233 { 234 const int field = 2 * sizeof(unsigned long); 235 unsigned int cause = regs->cp0_cause; 236 int i; 237 238 show_regs_print_info(KERN_DEFAULT); 239 240 /* 241 * Saved main processor registers 242 */ 243 for (i = 0; i < 32; ) { 244 if ((i % 4) == 0) 245 printk("$%2d :", i); 246 if (i == 0) 247 printk(" %0*lx", field, 0UL); 248 else if (i == 26 || i == 27) 249 printk(" %*s", field, ""); 250 else 251 printk(" %0*lx", field, regs->regs[i]); 252 253 i++; 254 if ((i % 4) == 0) 255 printk("\n"); 256 } 257 258 #ifdef CONFIG_CPU_HAS_SMARTMIPS 259 printk("Acx : %0*lx\n", field, regs->acx); 260 #endif 261 printk("Hi : %0*lx\n", field, regs->hi); 262 printk("Lo : %0*lx\n", field, regs->lo); 263 264 /* 265 * Saved cp0 registers 266 */ 267 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 268 (void *) regs->cp0_epc); 269 printk(" %s\n", print_tainted()); 270 printk("ra : %0*lx %pS\n", field, regs->regs[31], 271 (void *) regs->regs[31]); 272 273 printk("Status: %08x ", (uint32_t) regs->cp0_status); 274 275 if (cpu_has_3kex) { 276 if (regs->cp0_status & ST0_KUO) 277 printk("KUo "); 278 if (regs->cp0_status & ST0_IEO) 279 printk("IEo "); 280 if (regs->cp0_status & ST0_KUP) 281 printk("KUp "); 282 if (regs->cp0_status & ST0_IEP) 283 printk("IEp "); 284 if (regs->cp0_status & ST0_KUC) 285 printk("KUc "); 286 if (regs->cp0_status & ST0_IEC) 287 printk("IEc "); 288 } else if (cpu_has_4kex) { 289 if (regs->cp0_status & ST0_KX) 290 printk("KX "); 291 if (regs->cp0_status & ST0_SX) 292 printk("SX "); 293 if (regs->cp0_status & ST0_UX) 294 printk("UX "); 295 switch (regs->cp0_status & ST0_KSU) { 296 case KSU_USER: 297 printk("USER "); 298 break; 299 case KSU_SUPERVISOR: 300 printk("SUPERVISOR "); 301 break; 302 case KSU_KERNEL: 303 printk("KERNEL "); 304 break; 305 default: 306 printk("BAD_MODE "); 307 break; 308 } 309 if (regs->cp0_status & ST0_ERL) 310 printk("ERL "); 311 if (regs->cp0_status & ST0_EXL) 312 printk("EXL "); 313 if (regs->cp0_status & ST0_IE) 314 printk("IE "); 315 } 316 printk("\n"); 317 318 printk("Cause : %08x\n", cause); 319 320 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 321 if (1 <= cause && cause <= 5) 322 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 323 324 printk("PrId : %08x (%s)\n", read_c0_prid(), 325 cpu_name_string()); 326 } 327 328 /* 329 * FIXME: really the generic show_regs should take a const pointer argument. 330 */ 331 void show_regs(struct pt_regs *regs) 332 { 333 __show_regs((struct pt_regs *)regs); 334 } 335 336 void show_registers(struct pt_regs *regs) 337 { 338 const int field = 2 * sizeof(unsigned long); 339 mm_segment_t old_fs = get_fs(); 340 341 __show_regs(regs); 342 print_modules(); 343 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 344 current->comm, current->pid, current_thread_info(), current, 345 field, current_thread_info()->tp_value); 346 if (cpu_has_userlocal) { 347 unsigned long tls; 348 349 tls = read_c0_userlocal(); 350 if (tls != current_thread_info()->tp_value) 351 printk("*HwTLS: %0*lx\n", field, tls); 352 } 353 354 if (!user_mode(regs)) 355 /* Necessary for getting the correct stack content */ 356 set_fs(KERNEL_DS); 357 show_stacktrace(current, regs); 358 show_code((unsigned int __user *) regs->cp0_epc); 359 printk("\n"); 360 set_fs(old_fs); 361 } 362 363 static int regs_to_trapnr(struct pt_regs *regs) 364 { 365 return (regs->cp0_cause >> 2) & 0x1f; 366 } 367 368 static DEFINE_RAW_SPINLOCK(die_lock); 369 370 void __noreturn die(const char *str, struct pt_regs *regs) 371 { 372 static int die_counter; 373 int sig = SIGSEGV; 374 375 oops_enter(); 376 377 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), 378 SIGSEGV) == NOTIFY_STOP) 379 sig = 0; 380 381 console_verbose(); 382 raw_spin_lock_irq(&die_lock); 383 bust_spinlocks(1); 384 385 printk("%s[#%d]:\n", str, ++die_counter); 386 show_registers(regs); 387 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 388 raw_spin_unlock_irq(&die_lock); 389 390 oops_exit(); 391 392 if (in_interrupt()) 393 panic("Fatal exception in interrupt"); 394 395 if (panic_on_oops) { 396 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 397 ssleep(5); 398 panic("Fatal exception"); 399 } 400 401 if (regs && kexec_should_crash(current)) 402 crash_kexec(regs); 403 404 do_exit(sig); 405 } 406 407 extern struct exception_table_entry __start___dbe_table[]; 408 extern struct exception_table_entry __stop___dbe_table[]; 409 410 __asm__( 411 " .section __dbe_table, \"a\"\n" 412 " .previous \n"); 413 414 /* Given an address, look for it in the exception tables. */ 415 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 416 { 417 const struct exception_table_entry *e; 418 419 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 420 if (!e) 421 e = search_module_dbetables(addr); 422 return e; 423 } 424 425 asmlinkage void do_be(struct pt_regs *regs) 426 { 427 const int field = 2 * sizeof(unsigned long); 428 const struct exception_table_entry *fixup = NULL; 429 int data = regs->cp0_cause & 4; 430 int action = MIPS_BE_FATAL; 431 enum ctx_state prev_state; 432 433 prev_state = exception_enter(); 434 /* XXX For now. Fixme, this searches the wrong table ... */ 435 if (data && !user_mode(regs)) 436 fixup = search_dbe_tables(exception_epc(regs)); 437 438 if (fixup) 439 action = MIPS_BE_FIXUP; 440 441 if (board_be_handler) 442 action = board_be_handler(regs, fixup != NULL); 443 444 switch (action) { 445 case MIPS_BE_DISCARD: 446 goto out; 447 case MIPS_BE_FIXUP: 448 if (fixup) { 449 regs->cp0_epc = fixup->nextinsn; 450 goto out; 451 } 452 break; 453 default: 454 break; 455 } 456 457 /* 458 * Assume it would be too dangerous to continue ... 459 */ 460 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 461 data ? "Data" : "Instruction", 462 field, regs->cp0_epc, field, regs->regs[31]); 463 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), 464 SIGBUS) == NOTIFY_STOP) 465 goto out; 466 467 die_if_kernel("Oops", regs); 468 force_sig(SIGBUS, current); 469 470 out: 471 exception_exit(prev_state); 472 } 473 474 /* 475 * ll/sc, rdhwr, sync emulation 476 */ 477 478 #define OPCODE 0xfc000000 479 #define BASE 0x03e00000 480 #define RT 0x001f0000 481 #define OFFSET 0x0000ffff 482 #define LL 0xc0000000 483 #define SC 0xe0000000 484 #define SPEC0 0x00000000 485 #define SPEC3 0x7c000000 486 #define RD 0x0000f800 487 #define FUNC 0x0000003f 488 #define SYNC 0x0000000f 489 #define RDHWR 0x0000003b 490 491 /* microMIPS definitions */ 492 #define MM_POOL32A_FUNC 0xfc00ffff 493 #define MM_RDHWR 0x00006b3c 494 #define MM_RS 0x001f0000 495 #define MM_RT 0x03e00000 496 497 /* 498 * The ll_bit is cleared by r*_switch.S 499 */ 500 501 unsigned int ll_bit; 502 struct task_struct *ll_task; 503 504 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 505 { 506 unsigned long value, __user *vaddr; 507 long offset; 508 509 /* 510 * analyse the ll instruction that just caused a ri exception 511 * and put the referenced address to addr. 512 */ 513 514 /* sign extend offset */ 515 offset = opcode & OFFSET; 516 offset <<= 16; 517 offset >>= 16; 518 519 vaddr = (unsigned long __user *) 520 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 521 522 if ((unsigned long)vaddr & 3) 523 return SIGBUS; 524 if (get_user(value, vaddr)) 525 return SIGSEGV; 526 527 preempt_disable(); 528 529 if (ll_task == NULL || ll_task == current) { 530 ll_bit = 1; 531 } else { 532 ll_bit = 0; 533 } 534 ll_task = current; 535 536 preempt_enable(); 537 538 regs->regs[(opcode & RT) >> 16] = value; 539 540 return 0; 541 } 542 543 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 544 { 545 unsigned long __user *vaddr; 546 unsigned long reg; 547 long offset; 548 549 /* 550 * analyse the sc instruction that just caused a ri exception 551 * and put the referenced address to addr. 552 */ 553 554 /* sign extend offset */ 555 offset = opcode & OFFSET; 556 offset <<= 16; 557 offset >>= 16; 558 559 vaddr = (unsigned long __user *) 560 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 561 reg = (opcode & RT) >> 16; 562 563 if ((unsigned long)vaddr & 3) 564 return SIGBUS; 565 566 preempt_disable(); 567 568 if (ll_bit == 0 || ll_task != current) { 569 regs->regs[reg] = 0; 570 preempt_enable(); 571 return 0; 572 } 573 574 preempt_enable(); 575 576 if (put_user(regs->regs[reg], vaddr)) 577 return SIGSEGV; 578 579 regs->regs[reg] = 1; 580 581 return 0; 582 } 583 584 /* 585 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 586 * opcodes are supposed to result in coprocessor unusable exceptions if 587 * executed on ll/sc-less processors. That's the theory. In practice a 588 * few processors such as NEC's VR4100 throw reserved instruction exceptions 589 * instead, so we're doing the emulation thing in both exception handlers. 590 */ 591 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 592 { 593 if ((opcode & OPCODE) == LL) { 594 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 595 1, regs, 0); 596 return simulate_ll(regs, opcode); 597 } 598 if ((opcode & OPCODE) == SC) { 599 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 600 1, regs, 0); 601 return simulate_sc(regs, opcode); 602 } 603 604 return -1; /* Must be something else ... */ 605 } 606 607 /* 608 * Simulate trapping 'rdhwr' instructions to provide user accessible 609 * registers not implemented in hardware. 610 */ 611 static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 612 { 613 struct thread_info *ti = task_thread_info(current); 614 615 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 616 1, regs, 0); 617 switch (rd) { 618 case 0: /* CPU number */ 619 regs->regs[rt] = smp_processor_id(); 620 return 0; 621 case 1: /* SYNCI length */ 622 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 623 current_cpu_data.icache.linesz); 624 return 0; 625 case 2: /* Read count register */ 626 regs->regs[rt] = read_c0_count(); 627 return 0; 628 case 3: /* Count register resolution */ 629 switch (current_cpu_type()) { 630 case CPU_20KC: 631 case CPU_25KF: 632 regs->regs[rt] = 1; 633 break; 634 default: 635 regs->regs[rt] = 2; 636 } 637 return 0; 638 case 29: 639 regs->regs[rt] = ti->tp_value; 640 return 0; 641 default: 642 return -1; 643 } 644 } 645 646 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 647 { 648 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 649 int rd = (opcode & RD) >> 11; 650 int rt = (opcode & RT) >> 16; 651 652 simulate_rdhwr(regs, rd, rt); 653 return 0; 654 } 655 656 /* Not ours. */ 657 return -1; 658 } 659 660 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 661 { 662 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 663 int rd = (opcode & MM_RS) >> 16; 664 int rt = (opcode & MM_RT) >> 21; 665 simulate_rdhwr(regs, rd, rt); 666 return 0; 667 } 668 669 /* Not ours. */ 670 return -1; 671 } 672 673 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 674 { 675 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 676 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 677 1, regs, 0); 678 return 0; 679 } 680 681 return -1; /* Must be something else ... */ 682 } 683 684 asmlinkage void do_ov(struct pt_regs *regs) 685 { 686 enum ctx_state prev_state; 687 siginfo_t info; 688 689 prev_state = exception_enter(); 690 die_if_kernel("Integer overflow", regs); 691 692 info.si_code = FPE_INTOVF; 693 info.si_signo = SIGFPE; 694 info.si_errno = 0; 695 info.si_addr = (void __user *) regs->cp0_epc; 696 force_sig_info(SIGFPE, &info, current); 697 exception_exit(prev_state); 698 } 699 700 int process_fpemu_return(int sig, void __user *fault_addr) 701 { 702 if (sig == SIGSEGV || sig == SIGBUS) { 703 struct siginfo si = {0}; 704 si.si_addr = fault_addr; 705 si.si_signo = sig; 706 if (sig == SIGSEGV) { 707 if (find_vma(current->mm, (unsigned long)fault_addr)) 708 si.si_code = SEGV_ACCERR; 709 else 710 si.si_code = SEGV_MAPERR; 711 } else { 712 si.si_code = BUS_ADRERR; 713 } 714 force_sig_info(sig, &si, current); 715 return 1; 716 } else if (sig) { 717 force_sig(sig, current); 718 return 1; 719 } else { 720 return 0; 721 } 722 } 723 724 /* 725 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 726 */ 727 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 728 { 729 enum ctx_state prev_state; 730 siginfo_t info = {0}; 731 732 prev_state = exception_enter(); 733 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 734 SIGFPE) == NOTIFY_STOP) 735 goto out; 736 die_if_kernel("FP exception in kernel code", regs); 737 738 if (fcr31 & FPU_CSR_UNI_X) { 739 int sig; 740 void __user *fault_addr = NULL; 741 742 /* 743 * Unimplemented operation exception. If we've got the full 744 * software emulator on-board, let's use it... 745 * 746 * Force FPU to dump state into task/thread context. We're 747 * moving a lot of data here for what is probably a single 748 * instruction, but the alternative is to pre-decode the FP 749 * register operands before invoking the emulator, which seems 750 * a bit extreme for what should be an infrequent event. 751 */ 752 /* Ensure 'resume' not overwrite saved fp context again. */ 753 lose_fpu(1); 754 755 /* Run the emulator */ 756 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 757 &fault_addr); 758 759 /* 760 * We can't allow the emulated instruction to leave any of 761 * the cause bit set in $fcr31. 762 */ 763 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 764 765 /* Restore the hardware register state */ 766 own_fpu(1); /* Using the FPU again. */ 767 768 /* If something went wrong, signal */ 769 process_fpemu_return(sig, fault_addr); 770 771 goto out; 772 } else if (fcr31 & FPU_CSR_INV_X) 773 info.si_code = FPE_FLTINV; 774 else if (fcr31 & FPU_CSR_DIV_X) 775 info.si_code = FPE_FLTDIV; 776 else if (fcr31 & FPU_CSR_OVF_X) 777 info.si_code = FPE_FLTOVF; 778 else if (fcr31 & FPU_CSR_UDF_X) 779 info.si_code = FPE_FLTUND; 780 else if (fcr31 & FPU_CSR_INE_X) 781 info.si_code = FPE_FLTRES; 782 else 783 info.si_code = __SI_FAULT; 784 info.si_signo = SIGFPE; 785 info.si_errno = 0; 786 info.si_addr = (void __user *) regs->cp0_epc; 787 force_sig_info(SIGFPE, &info, current); 788 789 out: 790 exception_exit(prev_state); 791 } 792 793 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 794 const char *str) 795 { 796 siginfo_t info; 797 char b[40]; 798 799 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 800 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 801 return; 802 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 803 804 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), 805 SIGTRAP) == NOTIFY_STOP) 806 return; 807 808 /* 809 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 810 * insns, even for trap and break codes that indicate arithmetic 811 * failures. Weird ... 812 * But should we continue the brokenness??? --macro 813 */ 814 switch (code) { 815 case BRK_OVERFLOW: 816 case BRK_DIVZERO: 817 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 818 die_if_kernel(b, regs); 819 if (code == BRK_DIVZERO) 820 info.si_code = FPE_INTDIV; 821 else 822 info.si_code = FPE_INTOVF; 823 info.si_signo = SIGFPE; 824 info.si_errno = 0; 825 info.si_addr = (void __user *) regs->cp0_epc; 826 force_sig_info(SIGFPE, &info, current); 827 break; 828 case BRK_BUG: 829 die_if_kernel("Kernel bug detected", regs); 830 force_sig(SIGTRAP, current); 831 break; 832 case BRK_MEMU: 833 /* 834 * Address errors may be deliberately induced by the FPU 835 * emulator to retake control of the CPU after executing the 836 * instruction in the delay slot of an emulated branch. 837 * 838 * Terminate if exception was recognized as a delay slot return 839 * otherwise handle as normal. 840 */ 841 if (do_dsemulret(regs)) 842 return; 843 844 die_if_kernel("Math emu break/trap", regs); 845 force_sig(SIGTRAP, current); 846 break; 847 default: 848 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 849 die_if_kernel(b, regs); 850 force_sig(SIGTRAP, current); 851 } 852 } 853 854 asmlinkage void do_bp(struct pt_regs *regs) 855 { 856 unsigned int opcode, bcode; 857 enum ctx_state prev_state; 858 unsigned long epc; 859 u16 instr[2]; 860 mm_segment_t seg; 861 862 seg = get_fs(); 863 if (!user_mode(regs)) 864 set_fs(KERNEL_DS); 865 866 prev_state = exception_enter(); 867 if (get_isa16_mode(regs->cp0_epc)) { 868 /* Calculate EPC. */ 869 epc = exception_epc(regs); 870 if (cpu_has_mmips) { 871 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || 872 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) 873 goto out_sigsegv; 874 opcode = (instr[0] << 16) | instr[1]; 875 } else { 876 /* MIPS16e mode */ 877 if (__get_user(instr[0], 878 (u16 __user *)msk_isa16_mode(epc))) 879 goto out_sigsegv; 880 bcode = (instr[0] >> 6) & 0x3f; 881 do_trap_or_bp(regs, bcode, "Break"); 882 goto out; 883 } 884 } else { 885 if (__get_user(opcode, 886 (unsigned int __user *) exception_epc(regs))) 887 goto out_sigsegv; 888 } 889 890 /* 891 * There is the ancient bug in the MIPS assemblers that the break 892 * code starts left to bit 16 instead to bit 6 in the opcode. 893 * Gas is bug-compatible, but not always, grrr... 894 * We handle both cases with a simple heuristics. --macro 895 */ 896 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 897 if (bcode >= (1 << 10)) 898 bcode >>= 10; 899 900 /* 901 * notify the kprobe handlers, if instruction is likely to 902 * pertain to them. 903 */ 904 switch (bcode) { 905 case BRK_KPROBE_BP: 906 if (notify_die(DIE_BREAK, "debug", regs, bcode, 907 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 908 goto out; 909 else 910 break; 911 case BRK_KPROBE_SSTEPBP: 912 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 913 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 914 goto out; 915 else 916 break; 917 default: 918 break; 919 } 920 921 do_trap_or_bp(regs, bcode, "Break"); 922 923 out: 924 set_fs(seg); 925 exception_exit(prev_state); 926 return; 927 928 out_sigsegv: 929 force_sig(SIGSEGV, current); 930 goto out; 931 } 932 933 asmlinkage void do_tr(struct pt_regs *regs) 934 { 935 u32 opcode, tcode = 0; 936 enum ctx_state prev_state; 937 u16 instr[2]; 938 mm_segment_t seg; 939 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 940 941 seg = get_fs(); 942 if (!user_mode(regs)) 943 set_fs(get_ds()); 944 945 prev_state = exception_enter(); 946 if (get_isa16_mode(regs->cp0_epc)) { 947 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 948 __get_user(instr[1], (u16 __user *)(epc + 2))) 949 goto out_sigsegv; 950 opcode = (instr[0] << 16) | instr[1]; 951 /* Immediate versions don't provide a code. */ 952 if (!(opcode & OPCODE)) 953 tcode = (opcode >> 12) & ((1 << 4) - 1); 954 } else { 955 if (__get_user(opcode, (u32 __user *)epc)) 956 goto out_sigsegv; 957 /* Immediate versions don't provide a code. */ 958 if (!(opcode & OPCODE)) 959 tcode = (opcode >> 6) & ((1 << 10) - 1); 960 } 961 962 do_trap_or_bp(regs, tcode, "Trap"); 963 964 out: 965 set_fs(seg); 966 exception_exit(prev_state); 967 return; 968 969 out_sigsegv: 970 force_sig(SIGSEGV, current); 971 goto out; 972 } 973 974 asmlinkage void do_ri(struct pt_regs *regs) 975 { 976 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 977 unsigned long old_epc = regs->cp0_epc; 978 unsigned long old31 = regs->regs[31]; 979 enum ctx_state prev_state; 980 unsigned int opcode = 0; 981 int status = -1; 982 983 prev_state = exception_enter(); 984 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 985 SIGILL) == NOTIFY_STOP) 986 goto out; 987 988 die_if_kernel("Reserved instruction in kernel code", regs); 989 990 if (unlikely(compute_return_epc(regs) < 0)) 991 goto out; 992 993 if (get_isa16_mode(regs->cp0_epc)) { 994 unsigned short mmop[2] = { 0 }; 995 996 if (unlikely(get_user(mmop[0], epc) < 0)) 997 status = SIGSEGV; 998 if (unlikely(get_user(mmop[1], epc) < 0)) 999 status = SIGSEGV; 1000 opcode = (mmop[0] << 16) | mmop[1]; 1001 1002 if (status < 0) 1003 status = simulate_rdhwr_mm(regs, opcode); 1004 } else { 1005 if (unlikely(get_user(opcode, epc) < 0)) 1006 status = SIGSEGV; 1007 1008 if (!cpu_has_llsc && status < 0) 1009 status = simulate_llsc(regs, opcode); 1010 1011 if (status < 0) 1012 status = simulate_rdhwr_normal(regs, opcode); 1013 1014 if (status < 0) 1015 status = simulate_sync(regs, opcode); 1016 } 1017 1018 if (status < 0) 1019 status = SIGILL; 1020 1021 if (unlikely(status > 0)) { 1022 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1023 regs->regs[31] = old31; 1024 force_sig(status, current); 1025 } 1026 1027 out: 1028 exception_exit(prev_state); 1029 } 1030 1031 /* 1032 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1033 * emulated more than some threshold number of instructions, force migration to 1034 * a "CPU" that has FP support. 1035 */ 1036 static void mt_ase_fp_affinity(void) 1037 { 1038 #ifdef CONFIG_MIPS_MT_FPAFF 1039 if (mt_fpemul_threshold > 0 && 1040 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1041 /* 1042 * If there's no FPU present, or if the application has already 1043 * restricted the allowed set to exclude any CPUs with FPUs, 1044 * we'll skip the procedure. 1045 */ 1046 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 1047 cpumask_t tmask; 1048 1049 current->thread.user_cpus_allowed 1050 = current->cpus_allowed; 1051 cpus_and(tmask, current->cpus_allowed, 1052 mt_fpu_cpumask); 1053 set_cpus_allowed_ptr(current, &tmask); 1054 set_thread_flag(TIF_FPUBOUND); 1055 } 1056 } 1057 #endif /* CONFIG_MIPS_MT_FPAFF */ 1058 } 1059 1060 /* 1061 * No lock; only written during early bootup by CPU 0. 1062 */ 1063 static RAW_NOTIFIER_HEAD(cu2_chain); 1064 1065 int __ref register_cu2_notifier(struct notifier_block *nb) 1066 { 1067 return raw_notifier_chain_register(&cu2_chain, nb); 1068 } 1069 1070 int cu2_notifier_call_chain(unsigned long val, void *v) 1071 { 1072 return raw_notifier_call_chain(&cu2_chain, val, v); 1073 } 1074 1075 static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1076 void *data) 1077 { 1078 struct pt_regs *regs = data; 1079 1080 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1081 "instruction", regs); 1082 force_sig(SIGILL, current); 1083 1084 return NOTIFY_OK; 1085 } 1086 1087 static int enable_restore_fp_context(int msa) 1088 { 1089 int err, was_fpu_owner; 1090 1091 if (!used_math()) { 1092 /* First time FP context user. */ 1093 err = init_fpu(); 1094 if (msa && !err) 1095 enable_msa(); 1096 if (!err) 1097 set_used_math(); 1098 return err; 1099 } 1100 1101 /* 1102 * This task has formerly used the FP context. 1103 * 1104 * If this thread has no live MSA vector context then we can simply 1105 * restore the scalar FP context. If it has live MSA vector context 1106 * (that is, it has or may have used MSA since last performing a 1107 * function call) then we'll need to restore the vector context. This 1108 * applies even if we're currently only executing a scalar FP 1109 * instruction. This is because if we were to later execute an MSA 1110 * instruction then we'd either have to: 1111 * 1112 * - Restore the vector context & clobber any registers modified by 1113 * scalar FP instructions between now & then. 1114 * 1115 * or 1116 * 1117 * - Not restore the vector context & lose the most significant bits 1118 * of all vector registers. 1119 * 1120 * Neither of those options is acceptable. We cannot restore the least 1121 * significant bits of the registers now & only restore the most 1122 * significant bits later because the most significant bits of any 1123 * vector registers whose aliased FP register is modified now will have 1124 * been zeroed. We'd have no way to know that when restoring the vector 1125 * context & thus may load an outdated value for the most significant 1126 * bits of a vector register. 1127 */ 1128 if (!msa && !thread_msa_context_live()) 1129 return own_fpu(1); 1130 1131 /* 1132 * This task is using or has previously used MSA. Thus we require 1133 * that Status.FR == 1. 1134 */ 1135 was_fpu_owner = is_fpu_owner(); 1136 err = own_fpu(0); 1137 if (err) 1138 return err; 1139 1140 enable_msa(); 1141 write_msa_csr(current->thread.fpu.msacsr); 1142 set_thread_flag(TIF_USEDMSA); 1143 1144 /* 1145 * If this is the first time that the task is using MSA and it has 1146 * previously used scalar FP in this time slice then we already nave 1147 * FP context which we shouldn't clobber. 1148 */ 1149 if (!test_and_set_thread_flag(TIF_MSA_CTX_LIVE) && was_fpu_owner) 1150 return 0; 1151 1152 /* We need to restore the vector context. */ 1153 restore_msa(current); 1154 return 0; 1155 } 1156 1157 asmlinkage void do_cpu(struct pt_regs *regs) 1158 { 1159 enum ctx_state prev_state; 1160 unsigned int __user *epc; 1161 unsigned long old_epc, old31; 1162 unsigned int opcode; 1163 unsigned int cpid; 1164 int status, err; 1165 unsigned long __maybe_unused flags; 1166 1167 prev_state = exception_enter(); 1168 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1169 1170 if (cpid != 2) 1171 die_if_kernel("do_cpu invoked from kernel context!", regs); 1172 1173 switch (cpid) { 1174 case 0: 1175 epc = (unsigned int __user *)exception_epc(regs); 1176 old_epc = regs->cp0_epc; 1177 old31 = regs->regs[31]; 1178 opcode = 0; 1179 status = -1; 1180 1181 if (unlikely(compute_return_epc(regs) < 0)) 1182 goto out; 1183 1184 if (get_isa16_mode(regs->cp0_epc)) { 1185 unsigned short mmop[2] = { 0 }; 1186 1187 if (unlikely(get_user(mmop[0], epc) < 0)) 1188 status = SIGSEGV; 1189 if (unlikely(get_user(mmop[1], epc) < 0)) 1190 status = SIGSEGV; 1191 opcode = (mmop[0] << 16) | mmop[1]; 1192 1193 if (status < 0) 1194 status = simulate_rdhwr_mm(regs, opcode); 1195 } else { 1196 if (unlikely(get_user(opcode, epc) < 0)) 1197 status = SIGSEGV; 1198 1199 if (!cpu_has_llsc && status < 0) 1200 status = simulate_llsc(regs, opcode); 1201 1202 if (status < 0) 1203 status = simulate_rdhwr_normal(regs, opcode); 1204 } 1205 1206 if (status < 0) 1207 status = SIGILL; 1208 1209 if (unlikely(status > 0)) { 1210 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1211 regs->regs[31] = old31; 1212 force_sig(status, current); 1213 } 1214 1215 goto out; 1216 1217 case 3: 1218 /* 1219 * Old (MIPS I and MIPS II) processors will set this code 1220 * for COP1X opcode instructions that replaced the original 1221 * COP3 space. We don't limit COP1 space instructions in 1222 * the emulator according to the CPU ISA, so we want to 1223 * treat COP1X instructions consistently regardless of which 1224 * code the CPU chose. Therefore we redirect this trap to 1225 * the FP emulator too. 1226 * 1227 * Then some newer FPU-less processors use this code 1228 * erroneously too, so they are covered by this choice 1229 * as well. 1230 */ 1231 if (raw_cpu_has_fpu) 1232 break; 1233 /* Fall through. */ 1234 1235 case 1: 1236 err = enable_restore_fp_context(0); 1237 1238 if (!raw_cpu_has_fpu || err) { 1239 int sig; 1240 void __user *fault_addr = NULL; 1241 sig = fpu_emulator_cop1Handler(regs, 1242 ¤t->thread.fpu, 1243 0, &fault_addr); 1244 if (!process_fpemu_return(sig, fault_addr) && !err) 1245 mt_ase_fp_affinity(); 1246 } 1247 1248 goto out; 1249 1250 case 2: 1251 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1252 goto out; 1253 } 1254 1255 force_sig(SIGILL, current); 1256 1257 out: 1258 exception_exit(prev_state); 1259 } 1260 1261 asmlinkage void do_msa_fpe(struct pt_regs *regs) 1262 { 1263 enum ctx_state prev_state; 1264 1265 prev_state = exception_enter(); 1266 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1267 force_sig(SIGFPE, current); 1268 exception_exit(prev_state); 1269 } 1270 1271 asmlinkage void do_msa(struct pt_regs *regs) 1272 { 1273 enum ctx_state prev_state; 1274 int err; 1275 1276 prev_state = exception_enter(); 1277 1278 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1279 force_sig(SIGILL, current); 1280 goto out; 1281 } 1282 1283 die_if_kernel("do_msa invoked from kernel context!", regs); 1284 1285 err = enable_restore_fp_context(1); 1286 if (err) 1287 force_sig(SIGILL, current); 1288 out: 1289 exception_exit(prev_state); 1290 } 1291 1292 asmlinkage void do_mdmx(struct pt_regs *regs) 1293 { 1294 enum ctx_state prev_state; 1295 1296 prev_state = exception_enter(); 1297 force_sig(SIGILL, current); 1298 exception_exit(prev_state); 1299 } 1300 1301 /* 1302 * Called with interrupts disabled. 1303 */ 1304 asmlinkage void do_watch(struct pt_regs *regs) 1305 { 1306 enum ctx_state prev_state; 1307 u32 cause; 1308 1309 prev_state = exception_enter(); 1310 /* 1311 * Clear WP (bit 22) bit of cause register so we don't loop 1312 * forever. 1313 */ 1314 cause = read_c0_cause(); 1315 cause &= ~(1 << 22); 1316 write_c0_cause(cause); 1317 1318 /* 1319 * If the current thread has the watch registers loaded, save 1320 * their values and send SIGTRAP. Otherwise another thread 1321 * left the registers set, clear them and continue. 1322 */ 1323 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1324 mips_read_watch_registers(); 1325 local_irq_enable(); 1326 force_sig(SIGTRAP, current); 1327 } else { 1328 mips_clear_watch_registers(); 1329 local_irq_enable(); 1330 } 1331 exception_exit(prev_state); 1332 } 1333 1334 asmlinkage void do_mcheck(struct pt_regs *regs) 1335 { 1336 const int field = 2 * sizeof(unsigned long); 1337 int multi_match = regs->cp0_status & ST0_TS; 1338 enum ctx_state prev_state; 1339 1340 prev_state = exception_enter(); 1341 show_regs(regs); 1342 1343 if (multi_match) { 1344 printk("Index : %0x\n", read_c0_index()); 1345 printk("Pagemask: %0x\n", read_c0_pagemask()); 1346 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1347 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1348 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1349 printk("\n"); 1350 dump_tlb_all(); 1351 } 1352 1353 show_code((unsigned int __user *) regs->cp0_epc); 1354 1355 /* 1356 * Some chips may have other causes of machine check (e.g. SB1 1357 * graduation timer) 1358 */ 1359 panic("Caught Machine Check exception - %scaused by multiple " 1360 "matching entries in the TLB.", 1361 (multi_match) ? "" : "not "); 1362 } 1363 1364 asmlinkage void do_mt(struct pt_regs *regs) 1365 { 1366 int subcode; 1367 1368 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1369 >> VPECONTROL_EXCPT_SHIFT; 1370 switch (subcode) { 1371 case 0: 1372 printk(KERN_DEBUG "Thread Underflow\n"); 1373 break; 1374 case 1: 1375 printk(KERN_DEBUG "Thread Overflow\n"); 1376 break; 1377 case 2: 1378 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1379 break; 1380 case 3: 1381 printk(KERN_DEBUG "Gating Storage Exception\n"); 1382 break; 1383 case 4: 1384 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1385 break; 1386 case 5: 1387 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1388 break; 1389 default: 1390 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1391 subcode); 1392 break; 1393 } 1394 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1395 1396 force_sig(SIGILL, current); 1397 } 1398 1399 1400 asmlinkage void do_dsp(struct pt_regs *regs) 1401 { 1402 if (cpu_has_dsp) 1403 panic("Unexpected DSP exception"); 1404 1405 force_sig(SIGILL, current); 1406 } 1407 1408 asmlinkage void do_reserved(struct pt_regs *regs) 1409 { 1410 /* 1411 * Game over - no way to handle this if it ever occurs. Most probably 1412 * caused by a new unknown cpu type or after another deadly 1413 * hard/software error. 1414 */ 1415 show_regs(regs); 1416 panic("Caught reserved exception %ld - should not happen.", 1417 (regs->cp0_cause & 0x7f) >> 2); 1418 } 1419 1420 static int __initdata l1parity = 1; 1421 static int __init nol1parity(char *s) 1422 { 1423 l1parity = 0; 1424 return 1; 1425 } 1426 __setup("nol1par", nol1parity); 1427 static int __initdata l2parity = 1; 1428 static int __init nol2parity(char *s) 1429 { 1430 l2parity = 0; 1431 return 1; 1432 } 1433 __setup("nol2par", nol2parity); 1434 1435 /* 1436 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1437 * it different ways. 1438 */ 1439 static inline void parity_protection_init(void) 1440 { 1441 switch (current_cpu_type()) { 1442 case CPU_24K: 1443 case CPU_34K: 1444 case CPU_74K: 1445 case CPU_1004K: 1446 case CPU_1074K: 1447 case CPU_INTERAPTIV: 1448 case CPU_PROAPTIV: 1449 case CPU_P5600: 1450 { 1451 #define ERRCTL_PE 0x80000000 1452 #define ERRCTL_L2P 0x00800000 1453 unsigned long errctl; 1454 unsigned int l1parity_present, l2parity_present; 1455 1456 errctl = read_c0_ecc(); 1457 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1458 1459 /* probe L1 parity support */ 1460 write_c0_ecc(errctl | ERRCTL_PE); 1461 back_to_back_c0_hazard(); 1462 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1463 1464 /* probe L2 parity support */ 1465 write_c0_ecc(errctl|ERRCTL_L2P); 1466 back_to_back_c0_hazard(); 1467 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1468 1469 if (l1parity_present && l2parity_present) { 1470 if (l1parity) 1471 errctl |= ERRCTL_PE; 1472 if (l1parity ^ l2parity) 1473 errctl |= ERRCTL_L2P; 1474 } else if (l1parity_present) { 1475 if (l1parity) 1476 errctl |= ERRCTL_PE; 1477 } else if (l2parity_present) { 1478 if (l2parity) 1479 errctl |= ERRCTL_L2P; 1480 } else { 1481 /* No parity available */ 1482 } 1483 1484 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1485 1486 write_c0_ecc(errctl); 1487 back_to_back_c0_hazard(); 1488 errctl = read_c0_ecc(); 1489 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1490 1491 if (l1parity_present) 1492 printk(KERN_INFO "Cache parity protection %sabled\n", 1493 (errctl & ERRCTL_PE) ? "en" : "dis"); 1494 1495 if (l2parity_present) { 1496 if (l1parity_present && l1parity) 1497 errctl ^= ERRCTL_L2P; 1498 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1499 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1500 } 1501 } 1502 break; 1503 1504 case CPU_5KC: 1505 case CPU_5KE: 1506 case CPU_LOONGSON1: 1507 write_c0_ecc(0x80000000); 1508 back_to_back_c0_hazard(); 1509 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1510 printk(KERN_INFO "Cache parity protection %sabled\n", 1511 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1512 break; 1513 case CPU_20KC: 1514 case CPU_25KF: 1515 /* Clear the DE bit (bit 16) in the c0_status register. */ 1516 printk(KERN_INFO "Enable cache parity protection for " 1517 "MIPS 20KC/25KF CPUs.\n"); 1518 clear_c0_status(ST0_DE); 1519 break; 1520 default: 1521 break; 1522 } 1523 } 1524 1525 asmlinkage void cache_parity_error(void) 1526 { 1527 const int field = 2 * sizeof(unsigned long); 1528 unsigned int reg_val; 1529 1530 /* For the moment, report the problem and hang. */ 1531 printk("Cache error exception:\n"); 1532 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1533 reg_val = read_c0_cacheerr(); 1534 printk("c0_cacheerr == %08x\n", reg_val); 1535 1536 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1537 reg_val & (1<<30) ? "secondary" : "primary", 1538 reg_val & (1<<31) ? "data" : "insn"); 1539 if (cpu_has_mips_r2 && 1540 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1541 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1542 reg_val & (1<<29) ? "ED " : "", 1543 reg_val & (1<<28) ? "ET " : "", 1544 reg_val & (1<<27) ? "ES " : "", 1545 reg_val & (1<<26) ? "EE " : "", 1546 reg_val & (1<<25) ? "EB " : "", 1547 reg_val & (1<<24) ? "EI " : "", 1548 reg_val & (1<<23) ? "E1 " : "", 1549 reg_val & (1<<22) ? "E0 " : ""); 1550 } else { 1551 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1552 reg_val & (1<<29) ? "ED " : "", 1553 reg_val & (1<<28) ? "ET " : "", 1554 reg_val & (1<<26) ? "EE " : "", 1555 reg_val & (1<<25) ? "EB " : "", 1556 reg_val & (1<<24) ? "EI " : "", 1557 reg_val & (1<<23) ? "E1 " : "", 1558 reg_val & (1<<22) ? "E0 " : ""); 1559 } 1560 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1561 1562 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1563 if (reg_val & (1<<22)) 1564 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1565 1566 if (reg_val & (1<<23)) 1567 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1568 #endif 1569 1570 panic("Can't handle the cache error!"); 1571 } 1572 1573 asmlinkage void do_ftlb(void) 1574 { 1575 const int field = 2 * sizeof(unsigned long); 1576 unsigned int reg_val; 1577 1578 /* For the moment, report the problem and hang. */ 1579 if (cpu_has_mips_r2 && 1580 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1581 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1582 read_c0_ecc()); 1583 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1584 reg_val = read_c0_cacheerr(); 1585 pr_err("c0_cacheerr == %08x\n", reg_val); 1586 1587 if ((reg_val & 0xc0000000) == 0xc0000000) { 1588 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1589 } else { 1590 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1591 reg_val & (1<<30) ? "secondary" : "primary", 1592 reg_val & (1<<31) ? "data" : "insn"); 1593 } 1594 } else { 1595 pr_err("FTLB error exception\n"); 1596 } 1597 /* Just print the cacheerr bits for now */ 1598 cache_parity_error(); 1599 } 1600 1601 /* 1602 * SDBBP EJTAG debug exception handler. 1603 * We skip the instruction and return to the next instruction. 1604 */ 1605 void ejtag_exception_handler(struct pt_regs *regs) 1606 { 1607 const int field = 2 * sizeof(unsigned long); 1608 unsigned long depc, old_epc, old_ra; 1609 unsigned int debug; 1610 1611 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1612 depc = read_c0_depc(); 1613 debug = read_c0_debug(); 1614 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1615 if (debug & 0x80000000) { 1616 /* 1617 * In branch delay slot. 1618 * We cheat a little bit here and use EPC to calculate the 1619 * debug return address (DEPC). EPC is restored after the 1620 * calculation. 1621 */ 1622 old_epc = regs->cp0_epc; 1623 old_ra = regs->regs[31]; 1624 regs->cp0_epc = depc; 1625 compute_return_epc(regs); 1626 depc = regs->cp0_epc; 1627 regs->cp0_epc = old_epc; 1628 regs->regs[31] = old_ra; 1629 } else 1630 depc += 4; 1631 write_c0_depc(depc); 1632 1633 #if 0 1634 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1635 write_c0_debug(debug | 0x100); 1636 #endif 1637 } 1638 1639 /* 1640 * NMI exception handler. 1641 * No lock; only written during early bootup by CPU 0. 1642 */ 1643 static RAW_NOTIFIER_HEAD(nmi_chain); 1644 1645 int register_nmi_notifier(struct notifier_block *nb) 1646 { 1647 return raw_notifier_chain_register(&nmi_chain, nb); 1648 } 1649 1650 void __noreturn nmi_exception_handler(struct pt_regs *regs) 1651 { 1652 char str[100]; 1653 1654 raw_notifier_call_chain(&nmi_chain, 0, regs); 1655 bust_spinlocks(1); 1656 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1657 smp_processor_id(), regs->cp0_epc); 1658 regs->cp0_epc = read_c0_errorepc(); 1659 die(str, regs); 1660 } 1661 1662 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1663 1664 unsigned long ebase; 1665 unsigned long exception_handlers[32]; 1666 unsigned long vi_handlers[64]; 1667 1668 void __init *set_except_vector(int n, void *addr) 1669 { 1670 unsigned long handler = (unsigned long) addr; 1671 unsigned long old_handler; 1672 1673 #ifdef CONFIG_CPU_MICROMIPS 1674 /* 1675 * Only the TLB handlers are cache aligned with an even 1676 * address. All other handlers are on an odd address and 1677 * require no modification. Otherwise, MIPS32 mode will 1678 * be entered when handling any TLB exceptions. That 1679 * would be bad...since we must stay in microMIPS mode. 1680 */ 1681 if (!(handler & 0x1)) 1682 handler |= 1; 1683 #endif 1684 old_handler = xchg(&exception_handlers[n], handler); 1685 1686 if (n == 0 && cpu_has_divec) { 1687 #ifdef CONFIG_CPU_MICROMIPS 1688 unsigned long jump_mask = ~((1 << 27) - 1); 1689 #else 1690 unsigned long jump_mask = ~((1 << 28) - 1); 1691 #endif 1692 u32 *buf = (u32 *)(ebase + 0x200); 1693 unsigned int k0 = 26; 1694 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1695 uasm_i_j(&buf, handler & ~jump_mask); 1696 uasm_i_nop(&buf); 1697 } else { 1698 UASM_i_LA(&buf, k0, handler); 1699 uasm_i_jr(&buf, k0); 1700 uasm_i_nop(&buf); 1701 } 1702 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1703 } 1704 return (void *)old_handler; 1705 } 1706 1707 static void do_default_vi(void) 1708 { 1709 show_regs(get_irq_regs()); 1710 panic("Caught unexpected vectored interrupt."); 1711 } 1712 1713 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1714 { 1715 unsigned long handler; 1716 unsigned long old_handler = vi_handlers[n]; 1717 int srssets = current_cpu_data.srsets; 1718 u16 *h; 1719 unsigned char *b; 1720 1721 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1722 1723 if (addr == NULL) { 1724 handler = (unsigned long) do_default_vi; 1725 srs = 0; 1726 } else 1727 handler = (unsigned long) addr; 1728 vi_handlers[n] = handler; 1729 1730 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1731 1732 if (srs >= srssets) 1733 panic("Shadow register set %d not supported", srs); 1734 1735 if (cpu_has_veic) { 1736 if (board_bind_eic_interrupt) 1737 board_bind_eic_interrupt(n, srs); 1738 } else if (cpu_has_vint) { 1739 /* SRSMap is only defined if shadow sets are implemented */ 1740 if (srssets > 1) 1741 change_c0_srsmap(0xf << n*4, srs << n*4); 1742 } 1743 1744 if (srs == 0) { 1745 /* 1746 * If no shadow set is selected then use the default handler 1747 * that does normal register saving and standard interrupt exit 1748 */ 1749 extern char except_vec_vi, except_vec_vi_lui; 1750 extern char except_vec_vi_ori, except_vec_vi_end; 1751 extern char rollback_except_vec_vi; 1752 char *vec_start = using_rollback_handler() ? 1753 &rollback_except_vec_vi : &except_vec_vi; 1754 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1755 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1756 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1757 #else 1758 const int lui_offset = &except_vec_vi_lui - vec_start; 1759 const int ori_offset = &except_vec_vi_ori - vec_start; 1760 #endif 1761 const int handler_len = &except_vec_vi_end - vec_start; 1762 1763 if (handler_len > VECTORSPACING) { 1764 /* 1765 * Sigh... panicing won't help as the console 1766 * is probably not configured :( 1767 */ 1768 panic("VECTORSPACING too small"); 1769 } 1770 1771 set_handler(((unsigned long)b - ebase), vec_start, 1772 #ifdef CONFIG_CPU_MICROMIPS 1773 (handler_len - 1)); 1774 #else 1775 handler_len); 1776 #endif 1777 h = (u16 *)(b + lui_offset); 1778 *h = (handler >> 16) & 0xffff; 1779 h = (u16 *)(b + ori_offset); 1780 *h = (handler & 0xffff); 1781 local_flush_icache_range((unsigned long)b, 1782 (unsigned long)(b+handler_len)); 1783 } 1784 else { 1785 /* 1786 * In other cases jump directly to the interrupt handler. It 1787 * is the handler's responsibility to save registers if required 1788 * (eg hi/lo) and return from the exception using "eret". 1789 */ 1790 u32 insn; 1791 1792 h = (u16 *)b; 1793 /* j handler */ 1794 #ifdef CONFIG_CPU_MICROMIPS 1795 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 1796 #else 1797 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 1798 #endif 1799 h[0] = (insn >> 16) & 0xffff; 1800 h[1] = insn & 0xffff; 1801 h[2] = 0; 1802 h[3] = 0; 1803 local_flush_icache_range((unsigned long)b, 1804 (unsigned long)(b+8)); 1805 } 1806 1807 return (void *)old_handler; 1808 } 1809 1810 void *set_vi_handler(int n, vi_handler_t addr) 1811 { 1812 return set_vi_srs_handler(n, addr, 0); 1813 } 1814 1815 extern void tlb_init(void); 1816 1817 /* 1818 * Timer interrupt 1819 */ 1820 int cp0_compare_irq; 1821 EXPORT_SYMBOL_GPL(cp0_compare_irq); 1822 int cp0_compare_irq_shift; 1823 1824 /* 1825 * Performance counter IRQ or -1 if shared with timer 1826 */ 1827 int cp0_perfcount_irq; 1828 EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 1829 1830 static int noulri; 1831 1832 static int __init ulri_disable(char *s) 1833 { 1834 pr_info("Disabling ulri\n"); 1835 noulri = 1; 1836 1837 return 1; 1838 } 1839 __setup("noulri", ulri_disable); 1840 1841 /* configure STATUS register */ 1842 static void configure_status(void) 1843 { 1844 /* 1845 * Disable coprocessors and select 32-bit or 64-bit addressing 1846 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1847 * flag that some firmware may have left set and the TS bit (for 1848 * IP27). Set XX for ISA IV code to work. 1849 */ 1850 unsigned int status_set = ST0_CU0; 1851 #ifdef CONFIG_64BIT 1852 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1853 #endif 1854 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 1855 status_set |= ST0_XX; 1856 if (cpu_has_dsp) 1857 status_set |= ST0_MX; 1858 1859 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1860 status_set); 1861 } 1862 1863 /* configure HWRENA register */ 1864 static void configure_hwrena(void) 1865 { 1866 unsigned int hwrena = cpu_hwrena_impl_bits; 1867 1868 if (cpu_has_mips_r2) 1869 hwrena |= 0x0000000f; 1870 1871 if (!noulri && cpu_has_userlocal) 1872 hwrena |= (1 << 29); 1873 1874 if (hwrena) 1875 write_c0_hwrena(hwrena); 1876 } 1877 1878 static void configure_exception_vector(void) 1879 { 1880 if (cpu_has_veic || cpu_has_vint) { 1881 unsigned long sr = set_c0_status(ST0_BEV); 1882 write_c0_ebase(ebase); 1883 write_c0_status(sr); 1884 /* Setting vector spacing enables EI/VI mode */ 1885 change_c0_intctl(0x3e0, VECTORSPACING); 1886 } 1887 if (cpu_has_divec) { 1888 if (cpu_has_mipsmt) { 1889 unsigned int vpflags = dvpe(); 1890 set_c0_cause(CAUSEF_IV); 1891 evpe(vpflags); 1892 } else 1893 set_c0_cause(CAUSEF_IV); 1894 } 1895 } 1896 1897 void per_cpu_trap_init(bool is_boot_cpu) 1898 { 1899 unsigned int cpu = smp_processor_id(); 1900 1901 configure_status(); 1902 configure_hwrena(); 1903 1904 configure_exception_vector(); 1905 1906 /* 1907 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1908 * 1909 * o read IntCtl.IPTI to determine the timer interrupt 1910 * o read IntCtl.IPPCI to determine the performance counter interrupt 1911 */ 1912 if (cpu_has_mips_r2) { 1913 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 1914 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 1915 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 1916 if (cp0_perfcount_irq == cp0_compare_irq) 1917 cp0_perfcount_irq = -1; 1918 } else { 1919 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1920 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 1921 cp0_perfcount_irq = -1; 1922 } 1923 1924 if (!cpu_data[cpu].asid_cache) 1925 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1926 1927 atomic_inc(&init_mm.mm_count); 1928 current->active_mm = &init_mm; 1929 BUG_ON(current->mm); 1930 enter_lazy_tlb(&init_mm, current); 1931 1932 /* Boot CPU's cache setup in setup_arch(). */ 1933 if (!is_boot_cpu) 1934 cpu_cache_init(); 1935 tlb_init(); 1936 TLBMISS_HANDLER_SETUP(); 1937 } 1938 1939 /* Install CPU exception handler */ 1940 void set_handler(unsigned long offset, void *addr, unsigned long size) 1941 { 1942 #ifdef CONFIG_CPU_MICROMIPS 1943 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 1944 #else 1945 memcpy((void *)(ebase + offset), addr, size); 1946 #endif 1947 local_flush_icache_range(ebase + offset, ebase + offset + size); 1948 } 1949 1950 static char panic_null_cerr[] = 1951 "Trying to set NULL cache error exception handler"; 1952 1953 /* 1954 * Install uncached CPU exception handler. 1955 * This is suitable only for the cache error exception which is the only 1956 * exception handler that is being run uncached. 1957 */ 1958 void set_uncached_handler(unsigned long offset, void *addr, 1959 unsigned long size) 1960 { 1961 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 1962 1963 if (!addr) 1964 panic(panic_null_cerr); 1965 1966 memcpy((void *)(uncached_ebase + offset), addr, size); 1967 } 1968 1969 static int __initdata rdhwr_noopt; 1970 static int __init set_rdhwr_noopt(char *str) 1971 { 1972 rdhwr_noopt = 1; 1973 return 1; 1974 } 1975 1976 __setup("rdhwr_noopt", set_rdhwr_noopt); 1977 1978 void __init trap_init(void) 1979 { 1980 extern char except_vec3_generic; 1981 extern char except_vec4; 1982 extern char except_vec3_r4000; 1983 unsigned long i; 1984 1985 check_wait(); 1986 1987 #if defined(CONFIG_KGDB) 1988 if (kgdb_early_setup) 1989 return; /* Already done */ 1990 #endif 1991 1992 if (cpu_has_veic || cpu_has_vint) { 1993 unsigned long size = 0x200 + VECTORSPACING*64; 1994 ebase = (unsigned long) 1995 __alloc_bootmem(size, 1 << fls(size), 0); 1996 } else { 1997 #ifdef CONFIG_KVM_GUEST 1998 #define KVM_GUEST_KSEG0 0x40000000 1999 ebase = KVM_GUEST_KSEG0; 2000 #else 2001 ebase = CKSEG0; 2002 #endif 2003 if (cpu_has_mips_r2) 2004 ebase += (read_c0_ebase() & 0x3ffff000); 2005 } 2006 2007 if (cpu_has_mmips) { 2008 unsigned int config3 = read_c0_config3(); 2009 2010 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2011 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2012 else 2013 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2014 } 2015 2016 if (board_ebase_setup) 2017 board_ebase_setup(); 2018 per_cpu_trap_init(true); 2019 2020 /* 2021 * Copy the generic exception handlers to their final destination. 2022 * This will be overriden later as suitable for a particular 2023 * configuration. 2024 */ 2025 set_handler(0x180, &except_vec3_generic, 0x80); 2026 2027 /* 2028 * Setup default vectors 2029 */ 2030 for (i = 0; i <= 31; i++) 2031 set_except_vector(i, handle_reserved); 2032 2033 /* 2034 * Copy the EJTAG debug exception vector handler code to it's final 2035 * destination. 2036 */ 2037 if (cpu_has_ejtag && board_ejtag_handler_setup) 2038 board_ejtag_handler_setup(); 2039 2040 /* 2041 * Only some CPUs have the watch exceptions. 2042 */ 2043 if (cpu_has_watch) 2044 set_except_vector(23, handle_watch); 2045 2046 /* 2047 * Initialise interrupt handlers 2048 */ 2049 if (cpu_has_veic || cpu_has_vint) { 2050 int nvec = cpu_has_veic ? 64 : 8; 2051 for (i = 0; i < nvec; i++) 2052 set_vi_handler(i, NULL); 2053 } 2054 else if (cpu_has_divec) 2055 set_handler(0x200, &except_vec4, 0x8); 2056 2057 /* 2058 * Some CPUs can enable/disable for cache parity detection, but does 2059 * it different ways. 2060 */ 2061 parity_protection_init(); 2062 2063 /* 2064 * The Data Bus Errors / Instruction Bus Errors are signaled 2065 * by external hardware. Therefore these two exceptions 2066 * may have board specific handlers. 2067 */ 2068 if (board_be_init) 2069 board_be_init(); 2070 2071 set_except_vector(0, using_rollback_handler() ? rollback_handle_int 2072 : handle_int); 2073 set_except_vector(1, handle_tlbm); 2074 set_except_vector(2, handle_tlbl); 2075 set_except_vector(3, handle_tlbs); 2076 2077 set_except_vector(4, handle_adel); 2078 set_except_vector(5, handle_ades); 2079 2080 set_except_vector(6, handle_ibe); 2081 set_except_vector(7, handle_dbe); 2082 2083 set_except_vector(8, handle_sys); 2084 set_except_vector(9, handle_bp); 2085 set_except_vector(10, rdhwr_noopt ? handle_ri : 2086 (cpu_has_vtag_icache ? 2087 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 2088 set_except_vector(11, handle_cpu); 2089 set_except_vector(12, handle_ov); 2090 set_except_vector(13, handle_tr); 2091 set_except_vector(14, handle_msa_fpe); 2092 2093 if (current_cpu_type() == CPU_R6000 || 2094 current_cpu_type() == CPU_R6000A) { 2095 /* 2096 * The R6000 is the only R-series CPU that features a machine 2097 * check exception (similar to the R4000 cache error) and 2098 * unaligned ldc1/sdc1 exception. The handlers have not been 2099 * written yet. Well, anyway there is no R6000 machine on the 2100 * current list of targets for Linux/MIPS. 2101 * (Duh, crap, there is someone with a triple R6k machine) 2102 */ 2103 //set_except_vector(14, handle_mc); 2104 //set_except_vector(15, handle_ndc); 2105 } 2106 2107 2108 if (board_nmi_handler_setup) 2109 board_nmi_handler_setup(); 2110 2111 if (cpu_has_fpu && !cpu_has_nofpuex) 2112 set_except_vector(15, handle_fpe); 2113 2114 set_except_vector(16, handle_ftlb); 2115 set_except_vector(21, handle_msa); 2116 set_except_vector(22, handle_mdmx); 2117 2118 if (cpu_has_mcheck) 2119 set_except_vector(24, handle_mcheck); 2120 2121 if (cpu_has_mipsmt) 2122 set_except_vector(25, handle_mt); 2123 2124 set_except_vector(26, handle_dsp); 2125 2126 if (board_cache_error_setup) 2127 board_cache_error_setup(); 2128 2129 if (cpu_has_vce) 2130 /* Special exception: R4[04]00 uses also the divec space. */ 2131 set_handler(0x180, &except_vec3_r4000, 0x100); 2132 else if (cpu_has_4kex) 2133 set_handler(0x180, &except_vec3_generic, 0x80); 2134 else 2135 set_handler(0x080, &except_vec3_generic, 0x80); 2136 2137 local_flush_icache_range(ebase, ebase + 0x400); 2138 2139 sort_extable(__start___dbe_table, __stop___dbe_table); 2140 2141 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2142 } 2143 2144 static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2145 void *v) 2146 { 2147 switch (cmd) { 2148 case CPU_PM_ENTER_FAILED: 2149 case CPU_PM_EXIT: 2150 configure_status(); 2151 configure_hwrena(); 2152 configure_exception_vector(); 2153 2154 /* Restore register with CPU number for TLB handlers */ 2155 TLBMISS_HANDLER_RESTORE(); 2156 2157 break; 2158 } 2159 2160 return NOTIFY_OK; 2161 } 2162 2163 static struct notifier_block trap_pm_notifier_block = { 2164 .notifier_call = trap_pm_notifier, 2165 }; 2166 2167 static int __init trap_pm_init(void) 2168 { 2169 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2170 } 2171 arch_initcall(trap_pm_init); 2172