1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2000, 01 MIPS Technologies, Inc. 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki 13 */ 14 #include <linux/bug.h> 15 #include <linux/init.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/sched.h> 19 #include <linux/smp.h> 20 #include <linux/spinlock.h> 21 #include <linux/kallsyms.h> 22 #include <linux/bootmem.h> 23 #include <linux/interrupt.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/branch.h> 27 #include <asm/break.h> 28 #include <asm/cpu.h> 29 #include <asm/dsp.h> 30 #include <asm/fpu.h> 31 #include <asm/mipsregs.h> 32 #include <asm/mipsmtregs.h> 33 #include <asm/module.h> 34 #include <asm/pgtable.h> 35 #include <asm/ptrace.h> 36 #include <asm/sections.h> 37 #include <asm/system.h> 38 #include <asm/tlbdebug.h> 39 #include <asm/traps.h> 40 #include <asm/uaccess.h> 41 #include <asm/mmu_context.h> 42 #include <asm/types.h> 43 #include <asm/stacktrace.h> 44 45 extern asmlinkage void handle_int(void); 46 extern asmlinkage void handle_tlbm(void); 47 extern asmlinkage void handle_tlbl(void); 48 extern asmlinkage void handle_tlbs(void); 49 extern asmlinkage void handle_adel(void); 50 extern asmlinkage void handle_ades(void); 51 extern asmlinkage void handle_ibe(void); 52 extern asmlinkage void handle_dbe(void); 53 extern asmlinkage void handle_sys(void); 54 extern asmlinkage void handle_bp(void); 55 extern asmlinkage void handle_ri(void); 56 extern asmlinkage void handle_ri_rdhwr_vivt(void); 57 extern asmlinkage void handle_ri_rdhwr(void); 58 extern asmlinkage void handle_cpu(void); 59 extern asmlinkage void handle_ov(void); 60 extern asmlinkage void handle_tr(void); 61 extern asmlinkage void handle_fpe(void); 62 extern asmlinkage void handle_mdmx(void); 63 extern asmlinkage void handle_watch(void); 64 extern asmlinkage void handle_mt(void); 65 extern asmlinkage void handle_dsp(void); 66 extern asmlinkage void handle_mcheck(void); 67 extern asmlinkage void handle_reserved(void); 68 69 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 70 struct mips_fpu_struct *ctx, int has_fpu); 71 72 void (*board_watchpoint_handler)(struct pt_regs *regs); 73 void (*board_be_init)(void); 74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 75 void (*board_nmi_handler_setup)(void); 76 void (*board_ejtag_handler_setup)(void); 77 void (*board_bind_eic_interrupt)(int irq, int regset); 78 79 80 static void show_raw_backtrace(unsigned long reg29) 81 { 82 unsigned long *sp = (unsigned long *)reg29; 83 unsigned long addr; 84 85 printk("Call Trace:"); 86 #ifdef CONFIG_KALLSYMS 87 printk("\n"); 88 #endif 89 while (!kstack_end(sp)) { 90 addr = *sp++; 91 if (__kernel_text_address(addr)) 92 print_ip_sym(addr); 93 } 94 printk("\n"); 95 } 96 97 #ifdef CONFIG_KALLSYMS 98 int raw_show_trace; 99 static int __init set_raw_show_trace(char *str) 100 { 101 raw_show_trace = 1; 102 return 1; 103 } 104 __setup("raw_show_trace", set_raw_show_trace); 105 #endif 106 107 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 108 { 109 unsigned long sp = regs->regs[29]; 110 unsigned long ra = regs->regs[31]; 111 unsigned long pc = regs->cp0_epc; 112 113 if (raw_show_trace || !__kernel_text_address(pc)) { 114 show_raw_backtrace(sp); 115 return; 116 } 117 printk("Call Trace:\n"); 118 do { 119 print_ip_sym(pc); 120 pc = unwind_stack(task, &sp, pc, &ra); 121 } while (pc); 122 printk("\n"); 123 } 124 125 /* 126 * This routine abuses get_user()/put_user() to reference pointers 127 * with at least a bit of error checking ... 128 */ 129 static void show_stacktrace(struct task_struct *task, 130 const struct pt_regs *regs) 131 { 132 const int field = 2 * sizeof(unsigned long); 133 long stackdata; 134 int i; 135 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 136 137 printk("Stack :"); 138 i = 0; 139 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 140 if (i && ((i % (64 / field)) == 0)) 141 printk("\n "); 142 if (i > 39) { 143 printk(" ..."); 144 break; 145 } 146 147 if (__get_user(stackdata, sp++)) { 148 printk(" (Bad stack address)"); 149 break; 150 } 151 152 printk(" %0*lx", field, stackdata); 153 i++; 154 } 155 printk("\n"); 156 show_backtrace(task, regs); 157 } 158 159 void show_stack(struct task_struct *task, unsigned long *sp) 160 { 161 struct pt_regs regs; 162 if (sp) { 163 regs.regs[29] = (unsigned long)sp; 164 regs.regs[31] = 0; 165 regs.cp0_epc = 0; 166 } else { 167 if (task && task != current) { 168 regs.regs[29] = task->thread.reg29; 169 regs.regs[31] = 0; 170 regs.cp0_epc = task->thread.reg31; 171 } else { 172 prepare_frametrace(®s); 173 } 174 } 175 show_stacktrace(task, ®s); 176 } 177 178 /* 179 * The architecture-independent dump_stack generator 180 */ 181 void dump_stack(void) 182 { 183 struct pt_regs regs; 184 185 prepare_frametrace(®s); 186 show_backtrace(current, ®s); 187 } 188 189 EXPORT_SYMBOL(dump_stack); 190 191 static void show_code(unsigned int __user *pc) 192 { 193 long i; 194 195 printk("\nCode:"); 196 197 for(i = -3 ; i < 6 ; i++) { 198 unsigned int insn; 199 if (__get_user(insn, pc + i)) { 200 printk(" (Bad address in epc)\n"); 201 break; 202 } 203 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); 204 } 205 } 206 207 static void __show_regs(const struct pt_regs *regs) 208 { 209 const int field = 2 * sizeof(unsigned long); 210 unsigned int cause = regs->cp0_cause; 211 int i; 212 213 printk("Cpu %d\n", smp_processor_id()); 214 215 /* 216 * Saved main processor registers 217 */ 218 for (i = 0; i < 32; ) { 219 if ((i % 4) == 0) 220 printk("$%2d :", i); 221 if (i == 0) 222 printk(" %0*lx", field, 0UL); 223 else if (i == 26 || i == 27) 224 printk(" %*s", field, ""); 225 else 226 printk(" %0*lx", field, regs->regs[i]); 227 228 i++; 229 if ((i % 4) == 0) 230 printk("\n"); 231 } 232 233 #ifdef CONFIG_CPU_HAS_SMARTMIPS 234 printk("Acx : %0*lx\n", field, regs->acx); 235 #endif 236 printk("Hi : %0*lx\n", field, regs->hi); 237 printk("Lo : %0*lx\n", field, regs->lo); 238 239 /* 240 * Saved cp0 registers 241 */ 242 printk("epc : %0*lx ", field, regs->cp0_epc); 243 print_symbol("%s ", regs->cp0_epc); 244 printk(" %s\n", print_tainted()); 245 printk("ra : %0*lx ", field, regs->regs[31]); 246 print_symbol("%s\n", regs->regs[31]); 247 248 printk("Status: %08x ", (uint32_t) regs->cp0_status); 249 250 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 251 if (regs->cp0_status & ST0_KUO) 252 printk("KUo "); 253 if (regs->cp0_status & ST0_IEO) 254 printk("IEo "); 255 if (regs->cp0_status & ST0_KUP) 256 printk("KUp "); 257 if (regs->cp0_status & ST0_IEP) 258 printk("IEp "); 259 if (regs->cp0_status & ST0_KUC) 260 printk("KUc "); 261 if (regs->cp0_status & ST0_IEC) 262 printk("IEc "); 263 } else { 264 if (regs->cp0_status & ST0_KX) 265 printk("KX "); 266 if (regs->cp0_status & ST0_SX) 267 printk("SX "); 268 if (regs->cp0_status & ST0_UX) 269 printk("UX "); 270 switch (regs->cp0_status & ST0_KSU) { 271 case KSU_USER: 272 printk("USER "); 273 break; 274 case KSU_SUPERVISOR: 275 printk("SUPERVISOR "); 276 break; 277 case KSU_KERNEL: 278 printk("KERNEL "); 279 break; 280 default: 281 printk("BAD_MODE "); 282 break; 283 } 284 if (regs->cp0_status & ST0_ERL) 285 printk("ERL "); 286 if (regs->cp0_status & ST0_EXL) 287 printk("EXL "); 288 if (regs->cp0_status & ST0_IE) 289 printk("IE "); 290 } 291 printk("\n"); 292 293 printk("Cause : %08x\n", cause); 294 295 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 296 if (1 <= cause && cause <= 5) 297 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 298 299 printk("PrId : %08x (%s)\n", read_c0_prid(), 300 cpu_name_string()); 301 } 302 303 /* 304 * FIXME: really the generic show_regs should take a const pointer argument. 305 */ 306 void show_regs(struct pt_regs *regs) 307 { 308 __show_regs((struct pt_regs *)regs); 309 } 310 311 void show_registers(const struct pt_regs *regs) 312 { 313 __show_regs(regs); 314 print_modules(); 315 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 316 current->comm, current->pid, current_thread_info(), current); 317 show_stacktrace(current, regs); 318 show_code((unsigned int __user *) regs->cp0_epc); 319 printk("\n"); 320 } 321 322 static DEFINE_SPINLOCK(die_lock); 323 324 void __noreturn die(const char * str, const struct pt_regs * regs) 325 { 326 static int die_counter; 327 #ifdef CONFIG_MIPS_MT_SMTC 328 unsigned long dvpret = dvpe(); 329 #endif /* CONFIG_MIPS_MT_SMTC */ 330 331 console_verbose(); 332 spin_lock_irq(&die_lock); 333 bust_spinlocks(1); 334 #ifdef CONFIG_MIPS_MT_SMTC 335 mips_mt_regdump(dvpret); 336 #endif /* CONFIG_MIPS_MT_SMTC */ 337 printk("%s[#%d]:\n", str, ++die_counter); 338 show_registers(regs); 339 add_taint(TAINT_DIE); 340 spin_unlock_irq(&die_lock); 341 342 if (in_interrupt()) 343 panic("Fatal exception in interrupt"); 344 345 if (panic_on_oops) { 346 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); 347 ssleep(5); 348 panic("Fatal exception"); 349 } 350 351 do_exit(SIGSEGV); 352 } 353 354 extern const struct exception_table_entry __start___dbe_table[]; 355 extern const struct exception_table_entry __stop___dbe_table[]; 356 357 __asm__( 358 " .section __dbe_table, \"a\"\n" 359 " .previous \n"); 360 361 /* Given an address, look for it in the exception tables. */ 362 static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 363 { 364 const struct exception_table_entry *e; 365 366 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 367 if (!e) 368 e = search_module_dbetables(addr); 369 return e; 370 } 371 372 asmlinkage void do_be(struct pt_regs *regs) 373 { 374 const int field = 2 * sizeof(unsigned long); 375 const struct exception_table_entry *fixup = NULL; 376 int data = regs->cp0_cause & 4; 377 int action = MIPS_BE_FATAL; 378 379 /* XXX For now. Fixme, this searches the wrong table ... */ 380 if (data && !user_mode(regs)) 381 fixup = search_dbe_tables(exception_epc(regs)); 382 383 if (fixup) 384 action = MIPS_BE_FIXUP; 385 386 if (board_be_handler) 387 action = board_be_handler(regs, fixup != NULL); 388 389 switch (action) { 390 case MIPS_BE_DISCARD: 391 return; 392 case MIPS_BE_FIXUP: 393 if (fixup) { 394 regs->cp0_epc = fixup->nextinsn; 395 return; 396 } 397 break; 398 default: 399 break; 400 } 401 402 /* 403 * Assume it would be too dangerous to continue ... 404 */ 405 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 406 data ? "Data" : "Instruction", 407 field, regs->cp0_epc, field, regs->regs[31]); 408 die_if_kernel("Oops", regs); 409 force_sig(SIGBUS, current); 410 } 411 412 /* 413 * ll/sc emulation 414 */ 415 416 #define OPCODE 0xfc000000 417 #define BASE 0x03e00000 418 #define RT 0x001f0000 419 #define OFFSET 0x0000ffff 420 #define LL 0xc0000000 421 #define SC 0xe0000000 422 #define SPEC3 0x7c000000 423 #define RD 0x0000f800 424 #define FUNC 0x0000003f 425 #define RDHWR 0x0000003b 426 427 /* 428 * The ll_bit is cleared by r*_switch.S 429 */ 430 431 unsigned long ll_bit; 432 433 static struct task_struct *ll_task = NULL; 434 435 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) 436 { 437 unsigned long value, __user *vaddr; 438 long offset; 439 int signal = 0; 440 441 /* 442 * analyse the ll instruction that just caused a ri exception 443 * and put the referenced address to addr. 444 */ 445 446 /* sign extend offset */ 447 offset = opcode & OFFSET; 448 offset <<= 16; 449 offset >>= 16; 450 451 vaddr = (unsigned long __user *) 452 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 453 454 if ((unsigned long)vaddr & 3) { 455 signal = SIGBUS; 456 goto sig; 457 } 458 if (get_user(value, vaddr)) { 459 signal = SIGSEGV; 460 goto sig; 461 } 462 463 preempt_disable(); 464 465 if (ll_task == NULL || ll_task == current) { 466 ll_bit = 1; 467 } else { 468 ll_bit = 0; 469 } 470 ll_task = current; 471 472 preempt_enable(); 473 474 compute_return_epc(regs); 475 476 regs->regs[(opcode & RT) >> 16] = value; 477 478 return; 479 480 sig: 481 force_sig(signal, current); 482 } 483 484 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) 485 { 486 unsigned long __user *vaddr; 487 unsigned long reg; 488 long offset; 489 int signal = 0; 490 491 /* 492 * analyse the sc instruction that just caused a ri exception 493 * and put the referenced address to addr. 494 */ 495 496 /* sign extend offset */ 497 offset = opcode & OFFSET; 498 offset <<= 16; 499 offset >>= 16; 500 501 vaddr = (unsigned long __user *) 502 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 503 reg = (opcode & RT) >> 16; 504 505 if ((unsigned long)vaddr & 3) { 506 signal = SIGBUS; 507 goto sig; 508 } 509 510 preempt_disable(); 511 512 if (ll_bit == 0 || ll_task != current) { 513 compute_return_epc(regs); 514 regs->regs[reg] = 0; 515 preempt_enable(); 516 return; 517 } 518 519 preempt_enable(); 520 521 if (put_user(regs->regs[reg], vaddr)) { 522 signal = SIGSEGV; 523 goto sig; 524 } 525 526 compute_return_epc(regs); 527 regs->regs[reg] = 1; 528 529 return; 530 531 sig: 532 force_sig(signal, current); 533 } 534 535 /* 536 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 537 * opcodes are supposed to result in coprocessor unusable exceptions if 538 * executed on ll/sc-less processors. That's the theory. In practice a 539 * few processors such as NEC's VR4100 throw reserved instruction exceptions 540 * instead, so we're doing the emulation thing in both exception handlers. 541 */ 542 static inline int simulate_llsc(struct pt_regs *regs) 543 { 544 unsigned int opcode; 545 546 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 547 goto out_sigsegv; 548 549 if ((opcode & OPCODE) == LL) { 550 simulate_ll(regs, opcode); 551 return 0; 552 } 553 if ((opcode & OPCODE) == SC) { 554 simulate_sc(regs, opcode); 555 return 0; 556 } 557 558 return -EFAULT; /* Strange things going on ... */ 559 560 out_sigsegv: 561 force_sig(SIGSEGV, current); 562 return -EFAULT; 563 } 564 565 /* 566 * Simulate trapping 'rdhwr' instructions to provide user accessible 567 * registers not implemented in hardware. The only current use of this 568 * is the thread area pointer. 569 */ 570 static inline int simulate_rdhwr(struct pt_regs *regs) 571 { 572 struct thread_info *ti = task_thread_info(current); 573 unsigned int opcode; 574 575 if (get_user(opcode, (unsigned int __user *) exception_epc(regs))) 576 goto out_sigsegv; 577 578 if (unlikely(compute_return_epc(regs))) 579 return -EFAULT; 580 581 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 582 int rd = (opcode & RD) >> 11; 583 int rt = (opcode & RT) >> 16; 584 switch (rd) { 585 case 29: 586 regs->regs[rt] = ti->tp_value; 587 return 0; 588 default: 589 return -EFAULT; 590 } 591 } 592 593 /* Not ours. */ 594 return -EFAULT; 595 596 out_sigsegv: 597 force_sig(SIGSEGV, current); 598 return -EFAULT; 599 } 600 601 asmlinkage void do_ov(struct pt_regs *regs) 602 { 603 siginfo_t info; 604 605 die_if_kernel("Integer overflow", regs); 606 607 info.si_code = FPE_INTOVF; 608 info.si_signo = SIGFPE; 609 info.si_errno = 0; 610 info.si_addr = (void __user *) regs->cp0_epc; 611 force_sig_info(SIGFPE, &info, current); 612 } 613 614 /* 615 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 616 */ 617 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 618 { 619 siginfo_t info; 620 621 die_if_kernel("FP exception in kernel code", regs); 622 623 if (fcr31 & FPU_CSR_UNI_X) { 624 int sig; 625 626 /* 627 * Unimplemented operation exception. If we've got the full 628 * software emulator on-board, let's use it... 629 * 630 * Force FPU to dump state into task/thread context. We're 631 * moving a lot of data here for what is probably a single 632 * instruction, but the alternative is to pre-decode the FP 633 * register operands before invoking the emulator, which seems 634 * a bit extreme for what should be an infrequent event. 635 */ 636 /* Ensure 'resume' not overwrite saved fp context again. */ 637 lose_fpu(1); 638 639 /* Run the emulator */ 640 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); 641 642 /* 643 * We can't allow the emulated instruction to leave any of 644 * the cause bit set in $fcr31. 645 */ 646 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 647 648 /* Restore the hardware register state */ 649 own_fpu(1); /* Using the FPU again. */ 650 651 /* If something went wrong, signal */ 652 if (sig) 653 force_sig(sig, current); 654 655 return; 656 } else if (fcr31 & FPU_CSR_INV_X) 657 info.si_code = FPE_FLTINV; 658 else if (fcr31 & FPU_CSR_DIV_X) 659 info.si_code = FPE_FLTDIV; 660 else if (fcr31 & FPU_CSR_OVF_X) 661 info.si_code = FPE_FLTOVF; 662 else if (fcr31 & FPU_CSR_UDF_X) 663 info.si_code = FPE_FLTUND; 664 else if (fcr31 & FPU_CSR_INE_X) 665 info.si_code = FPE_FLTRES; 666 else 667 info.si_code = __SI_FAULT; 668 info.si_signo = SIGFPE; 669 info.si_errno = 0; 670 info.si_addr = (void __user *) regs->cp0_epc; 671 force_sig_info(SIGFPE, &info, current); 672 } 673 674 asmlinkage void do_bp(struct pt_regs *regs) 675 { 676 unsigned int opcode, bcode; 677 siginfo_t info; 678 679 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 680 goto out_sigsegv; 681 682 /* 683 * There is the ancient bug in the MIPS assemblers that the break 684 * code starts left to bit 16 instead to bit 6 in the opcode. 685 * Gas is bug-compatible, but not always, grrr... 686 * We handle both cases with a simple heuristics. --macro 687 */ 688 bcode = ((opcode >> 6) & ((1 << 20) - 1)); 689 if (bcode < (1 << 10)) 690 bcode <<= 10; 691 692 /* 693 * (A short test says that IRIX 5.3 sends SIGTRAP for all break 694 * insns, even for break codes that indicate arithmetic failures. 695 * Weird ...) 696 * But should we continue the brokenness??? --macro 697 */ 698 switch (bcode) { 699 case BRK_OVERFLOW << 10: 700 case BRK_DIVZERO << 10: 701 die_if_kernel("Break instruction in kernel code", regs); 702 if (bcode == (BRK_DIVZERO << 10)) 703 info.si_code = FPE_INTDIV; 704 else 705 info.si_code = FPE_INTOVF; 706 info.si_signo = SIGFPE; 707 info.si_errno = 0; 708 info.si_addr = (void __user *) regs->cp0_epc; 709 force_sig_info(SIGFPE, &info, current); 710 break; 711 case BRK_BUG: 712 die("Kernel bug detected", regs); 713 break; 714 default: 715 die_if_kernel("Break instruction in kernel code", regs); 716 force_sig(SIGTRAP, current); 717 } 718 return; 719 720 out_sigsegv: 721 force_sig(SIGSEGV, current); 722 } 723 724 asmlinkage void do_tr(struct pt_regs *regs) 725 { 726 unsigned int opcode, tcode = 0; 727 siginfo_t info; 728 729 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) 730 goto out_sigsegv; 731 732 /* Immediate versions don't provide a code. */ 733 if (!(opcode & OPCODE)) 734 tcode = ((opcode >> 6) & ((1 << 10) - 1)); 735 736 /* 737 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap 738 * insns, even for trap codes that indicate arithmetic failures. 739 * Weird ...) 740 * But should we continue the brokenness??? --macro 741 */ 742 switch (tcode) { 743 case BRK_OVERFLOW: 744 case BRK_DIVZERO: 745 die_if_kernel("Trap instruction in kernel code", regs); 746 if (tcode == BRK_DIVZERO) 747 info.si_code = FPE_INTDIV; 748 else 749 info.si_code = FPE_INTOVF; 750 info.si_signo = SIGFPE; 751 info.si_errno = 0; 752 info.si_addr = (void __user *) regs->cp0_epc; 753 force_sig_info(SIGFPE, &info, current); 754 break; 755 case BRK_BUG: 756 die("Kernel bug detected", regs); 757 break; 758 default: 759 die_if_kernel("Trap instruction in kernel code", regs); 760 force_sig(SIGTRAP, current); 761 } 762 return; 763 764 out_sigsegv: 765 force_sig(SIGSEGV, current); 766 } 767 768 asmlinkage void do_ri(struct pt_regs *regs) 769 { 770 die_if_kernel("Reserved instruction in kernel code", regs); 771 772 if (!cpu_has_llsc) 773 if (!simulate_llsc(regs)) 774 return; 775 776 if (!simulate_rdhwr(regs)) 777 return; 778 779 force_sig(SIGILL, current); 780 } 781 782 /* 783 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 784 * emulated more than some threshold number of instructions, force migration to 785 * a "CPU" that has FP support. 786 */ 787 static void mt_ase_fp_affinity(void) 788 { 789 #ifdef CONFIG_MIPS_MT_FPAFF 790 if (mt_fpemul_threshold > 0 && 791 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 792 /* 793 * If there's no FPU present, or if the application has already 794 * restricted the allowed set to exclude any CPUs with FPUs, 795 * we'll skip the procedure. 796 */ 797 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { 798 cpumask_t tmask; 799 800 cpus_and(tmask, current->thread.user_cpus_allowed, 801 mt_fpu_cpumask); 802 set_cpus_allowed(current, tmask); 803 set_thread_flag(TIF_FPUBOUND); 804 } 805 } 806 #endif /* CONFIG_MIPS_MT_FPAFF */ 807 } 808 809 asmlinkage void do_cpu(struct pt_regs *regs) 810 { 811 unsigned int cpid; 812 813 die_if_kernel("do_cpu invoked from kernel context!", regs); 814 815 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 816 817 switch (cpid) { 818 case 0: 819 if (!cpu_has_llsc) 820 if (!simulate_llsc(regs)) 821 return; 822 823 if (!simulate_rdhwr(regs)) 824 return; 825 826 break; 827 828 case 1: 829 if (used_math()) /* Using the FPU again. */ 830 own_fpu(1); 831 else { /* First time FPU user. */ 832 init_fpu(); 833 set_used_math(); 834 } 835 836 if (!raw_cpu_has_fpu) { 837 int sig; 838 sig = fpu_emulator_cop1Handler(regs, 839 ¤t->thread.fpu, 0); 840 if (sig) 841 force_sig(sig, current); 842 else 843 mt_ase_fp_affinity(); 844 } 845 846 return; 847 848 case 2: 849 case 3: 850 break; 851 } 852 853 force_sig(SIGILL, current); 854 } 855 856 asmlinkage void do_mdmx(struct pt_regs *regs) 857 { 858 force_sig(SIGILL, current); 859 } 860 861 asmlinkage void do_watch(struct pt_regs *regs) 862 { 863 if (board_watchpoint_handler) { 864 (*board_watchpoint_handler)(regs); 865 return; 866 } 867 868 /* 869 * We use the watch exception where available to detect stack 870 * overflows. 871 */ 872 dump_tlb_all(); 873 show_regs(regs); 874 panic("Caught WATCH exception - probably caused by stack overflow."); 875 } 876 877 asmlinkage void do_mcheck(struct pt_regs *regs) 878 { 879 const int field = 2 * sizeof(unsigned long); 880 int multi_match = regs->cp0_status & ST0_TS; 881 882 show_regs(regs); 883 884 if (multi_match) { 885 printk("Index : %0x\n", read_c0_index()); 886 printk("Pagemask: %0x\n", read_c0_pagemask()); 887 printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); 888 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 889 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 890 printk("\n"); 891 dump_tlb_all(); 892 } 893 894 show_code((unsigned int __user *) regs->cp0_epc); 895 896 /* 897 * Some chips may have other causes of machine check (e.g. SB1 898 * graduation timer) 899 */ 900 panic("Caught Machine Check exception - %scaused by multiple " 901 "matching entries in the TLB.", 902 (multi_match) ? "" : "not "); 903 } 904 905 asmlinkage void do_mt(struct pt_regs *regs) 906 { 907 int subcode; 908 909 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 910 >> VPECONTROL_EXCPT_SHIFT; 911 switch (subcode) { 912 case 0: 913 printk(KERN_DEBUG "Thread Underflow\n"); 914 break; 915 case 1: 916 printk(KERN_DEBUG "Thread Overflow\n"); 917 break; 918 case 2: 919 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 920 break; 921 case 3: 922 printk(KERN_DEBUG "Gating Storage Exception\n"); 923 break; 924 case 4: 925 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 926 break; 927 case 5: 928 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); 929 break; 930 default: 931 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 932 subcode); 933 break; 934 } 935 die_if_kernel("MIPS MT Thread exception in kernel", regs); 936 937 force_sig(SIGILL, current); 938 } 939 940 941 asmlinkage void do_dsp(struct pt_regs *regs) 942 { 943 if (cpu_has_dsp) 944 panic("Unexpected DSP exception\n"); 945 946 force_sig(SIGILL, current); 947 } 948 949 asmlinkage void do_reserved(struct pt_regs *regs) 950 { 951 /* 952 * Game over - no way to handle this if it ever occurs. Most probably 953 * caused by a new unknown cpu type or after another deadly 954 * hard/software error. 955 */ 956 show_regs(regs); 957 panic("Caught reserved exception %ld - should not happen.", 958 (regs->cp0_cause & 0x7f) >> 2); 959 } 960 961 /* 962 * Some MIPS CPUs can enable/disable for cache parity detection, but do 963 * it different ways. 964 */ 965 static inline void parity_protection_init(void) 966 { 967 switch (current_cpu_type()) { 968 case CPU_24K: 969 case CPU_34K: 970 case CPU_5KC: 971 write_c0_ecc(0x80000000); 972 back_to_back_c0_hazard(); 973 /* Set the PE bit (bit 31) in the c0_errctl register. */ 974 printk(KERN_INFO "Cache parity protection %sabled\n", 975 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 976 break; 977 case CPU_20KC: 978 case CPU_25KF: 979 /* Clear the DE bit (bit 16) in the c0_status register. */ 980 printk(KERN_INFO "Enable cache parity protection for " 981 "MIPS 20KC/25KF CPUs.\n"); 982 clear_c0_status(ST0_DE); 983 break; 984 default: 985 break; 986 } 987 } 988 989 asmlinkage void cache_parity_error(void) 990 { 991 const int field = 2 * sizeof(unsigned long); 992 unsigned int reg_val; 993 994 /* For the moment, report the problem and hang. */ 995 printk("Cache error exception:\n"); 996 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 997 reg_val = read_c0_cacheerr(); 998 printk("c0_cacheerr == %08x\n", reg_val); 999 1000 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1001 reg_val & (1<<30) ? "secondary" : "primary", 1002 reg_val & (1<<31) ? "data" : "insn"); 1003 printk("Error bits: %s%s%s%s%s%s%s\n", 1004 reg_val & (1<<29) ? "ED " : "", 1005 reg_val & (1<<28) ? "ET " : "", 1006 reg_val & (1<<26) ? "EE " : "", 1007 reg_val & (1<<25) ? "EB " : "", 1008 reg_val & (1<<24) ? "EI " : "", 1009 reg_val & (1<<23) ? "E1 " : "", 1010 reg_val & (1<<22) ? "E0 " : ""); 1011 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1012 1013 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1014 if (reg_val & (1<<22)) 1015 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1016 1017 if (reg_val & (1<<23)) 1018 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1019 #endif 1020 1021 panic("Can't handle the cache error!"); 1022 } 1023 1024 /* 1025 * SDBBP EJTAG debug exception handler. 1026 * We skip the instruction and return to the next instruction. 1027 */ 1028 void ejtag_exception_handler(struct pt_regs *regs) 1029 { 1030 const int field = 2 * sizeof(unsigned long); 1031 unsigned long depc, old_epc; 1032 unsigned int debug; 1033 1034 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1035 depc = read_c0_depc(); 1036 debug = read_c0_debug(); 1037 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1038 if (debug & 0x80000000) { 1039 /* 1040 * In branch delay slot. 1041 * We cheat a little bit here and use EPC to calculate the 1042 * debug return address (DEPC). EPC is restored after the 1043 * calculation. 1044 */ 1045 old_epc = regs->cp0_epc; 1046 regs->cp0_epc = depc; 1047 __compute_return_epc(regs); 1048 depc = regs->cp0_epc; 1049 regs->cp0_epc = old_epc; 1050 } else 1051 depc += 4; 1052 write_c0_depc(depc); 1053 1054 #if 0 1055 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1056 write_c0_debug(debug | 0x100); 1057 #endif 1058 } 1059 1060 /* 1061 * NMI exception handler. 1062 */ 1063 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1064 { 1065 bust_spinlocks(1); 1066 printk("NMI taken!!!!\n"); 1067 die("NMI", regs); 1068 } 1069 1070 #define VECTORSPACING 0x100 /* for EI/VI mode */ 1071 1072 unsigned long ebase; 1073 unsigned long exception_handlers[32]; 1074 unsigned long vi_handlers[64]; 1075 1076 /* 1077 * As a side effect of the way this is implemented we're limited 1078 * to interrupt handlers in the address range from 1079 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... 1080 */ 1081 void *set_except_vector(int n, void *addr) 1082 { 1083 unsigned long handler = (unsigned long) addr; 1084 unsigned long old_handler = exception_handlers[n]; 1085 1086 exception_handlers[n] = handler; 1087 if (n == 0 && cpu_has_divec) { 1088 *(u32 *)(ebase + 0x200) = 0x08000000 | 1089 (0x03ffffff & (handler >> 2)); 1090 flush_icache_range(ebase + 0x200, ebase + 0x204); 1091 } 1092 return (void *)old_handler; 1093 } 1094 1095 #ifdef CONFIG_CPU_MIPSR2_SRS 1096 /* 1097 * MIPSR2 shadow register set allocation 1098 * FIXME: SMP... 1099 */ 1100 1101 static struct shadow_registers { 1102 /* 1103 * Number of shadow register sets supported 1104 */ 1105 unsigned long sr_supported; 1106 /* 1107 * Bitmap of allocated shadow registers 1108 */ 1109 unsigned long sr_allocated; 1110 } shadow_registers; 1111 1112 static void mips_srs_init(void) 1113 { 1114 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1115 printk(KERN_INFO "%ld MIPSR2 register sets available\n", 1116 shadow_registers.sr_supported); 1117 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1118 } 1119 1120 int mips_srs_max(void) 1121 { 1122 return shadow_registers.sr_supported; 1123 } 1124 1125 int mips_srs_alloc(void) 1126 { 1127 struct shadow_registers *sr = &shadow_registers; 1128 int set; 1129 1130 again: 1131 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); 1132 if (set >= sr->sr_supported) 1133 return -1; 1134 1135 if (test_and_set_bit(set, &sr->sr_allocated)) 1136 goto again; 1137 1138 return set; 1139 } 1140 1141 void mips_srs_free(int set) 1142 { 1143 struct shadow_registers *sr = &shadow_registers; 1144 1145 clear_bit(set, &sr->sr_allocated); 1146 } 1147 1148 static asmlinkage void do_default_vi(void) 1149 { 1150 show_regs(get_irq_regs()); 1151 panic("Caught unexpected vectored interrupt."); 1152 } 1153 1154 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1155 { 1156 unsigned long handler; 1157 unsigned long old_handler = vi_handlers[n]; 1158 u32 *w; 1159 unsigned char *b; 1160 1161 if (!cpu_has_veic && !cpu_has_vint) 1162 BUG(); 1163 1164 if (addr == NULL) { 1165 handler = (unsigned long) do_default_vi; 1166 srs = 0; 1167 } else 1168 handler = (unsigned long) addr; 1169 vi_handlers[n] = (unsigned long) addr; 1170 1171 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1172 1173 if (srs >= mips_srs_max()) 1174 panic("Shadow register set %d not supported", srs); 1175 1176 if (cpu_has_veic) { 1177 if (board_bind_eic_interrupt) 1178 board_bind_eic_interrupt(n, srs); 1179 } else if (cpu_has_vint) { 1180 /* SRSMap is only defined if shadow sets are implemented */ 1181 if (mips_srs_max() > 1) 1182 change_c0_srsmap(0xf << n*4, srs << n*4); 1183 } 1184 1185 if (srs == 0) { 1186 /* 1187 * If no shadow set is selected then use the default handler 1188 * that does normal register saving and a standard interrupt exit 1189 */ 1190 1191 extern char except_vec_vi, except_vec_vi_lui; 1192 extern char except_vec_vi_ori, except_vec_vi_end; 1193 #ifdef CONFIG_MIPS_MT_SMTC 1194 /* 1195 * We need to provide the SMTC vectored interrupt handler 1196 * not only with the address of the handler, but with the 1197 * Status.IM bit to be masked before going there. 1198 */ 1199 extern char except_vec_vi_mori; 1200 const int mori_offset = &except_vec_vi_mori - &except_vec_vi; 1201 #endif /* CONFIG_MIPS_MT_SMTC */ 1202 const int handler_len = &except_vec_vi_end - &except_vec_vi; 1203 const int lui_offset = &except_vec_vi_lui - &except_vec_vi; 1204 const int ori_offset = &except_vec_vi_ori - &except_vec_vi; 1205 1206 if (handler_len > VECTORSPACING) { 1207 /* 1208 * Sigh... panicing won't help as the console 1209 * is probably not configured :( 1210 */ 1211 panic("VECTORSPACING too small"); 1212 } 1213 1214 memcpy(b, &except_vec_vi, handler_len); 1215 #ifdef CONFIG_MIPS_MT_SMTC 1216 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1217 1218 w = (u32 *)(b + mori_offset); 1219 *w = (*w & 0xffff0000) | (0x100 << n); 1220 #endif /* CONFIG_MIPS_MT_SMTC */ 1221 w = (u32 *)(b + lui_offset); 1222 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); 1223 w = (u32 *)(b + ori_offset); 1224 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); 1225 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); 1226 } 1227 else { 1228 /* 1229 * In other cases jump directly to the interrupt handler 1230 * 1231 * It is the handlers responsibility to save registers if required 1232 * (eg hi/lo) and return from the exception using "eret" 1233 */ 1234 w = (u32 *)b; 1235 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ 1236 *w = 0; 1237 flush_icache_range((unsigned long)b, (unsigned long)(b+8)); 1238 } 1239 1240 return (void *)old_handler; 1241 } 1242 1243 void *set_vi_handler(int n, vi_handler_t addr) 1244 { 1245 return set_vi_srs_handler(n, addr, 0); 1246 } 1247 1248 #else 1249 1250 static inline void mips_srs_init(void) 1251 { 1252 } 1253 1254 #endif /* CONFIG_CPU_MIPSR2_SRS */ 1255 1256 /* 1257 * This is used by native signal handling 1258 */ 1259 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); 1260 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); 1261 1262 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); 1263 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); 1264 1265 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); 1266 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); 1267 1268 #ifdef CONFIG_SMP 1269 static int smp_save_fp_context(struct sigcontext __user *sc) 1270 { 1271 return raw_cpu_has_fpu 1272 ? _save_fp_context(sc) 1273 : fpu_emulator_save_context(sc); 1274 } 1275 1276 static int smp_restore_fp_context(struct sigcontext __user *sc) 1277 { 1278 return raw_cpu_has_fpu 1279 ? _restore_fp_context(sc) 1280 : fpu_emulator_restore_context(sc); 1281 } 1282 #endif 1283 1284 static inline void signal_init(void) 1285 { 1286 #ifdef CONFIG_SMP 1287 /* For now just do the cpu_has_fpu check when the functions are invoked */ 1288 save_fp_context = smp_save_fp_context; 1289 restore_fp_context = smp_restore_fp_context; 1290 #else 1291 if (cpu_has_fpu) { 1292 save_fp_context = _save_fp_context; 1293 restore_fp_context = _restore_fp_context; 1294 } else { 1295 save_fp_context = fpu_emulator_save_context; 1296 restore_fp_context = fpu_emulator_restore_context; 1297 } 1298 #endif 1299 } 1300 1301 #ifdef CONFIG_MIPS32_COMPAT 1302 1303 /* 1304 * This is used by 32-bit signal stuff on the 64-bit kernel 1305 */ 1306 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); 1307 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); 1308 1309 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); 1310 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); 1311 1312 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); 1313 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); 1314 1315 static inline void signal32_init(void) 1316 { 1317 if (cpu_has_fpu) { 1318 save_fp_context32 = _save_fp_context32; 1319 restore_fp_context32 = _restore_fp_context32; 1320 } else { 1321 save_fp_context32 = fpu_emulator_save_context32; 1322 restore_fp_context32 = fpu_emulator_restore_context32; 1323 } 1324 } 1325 #endif 1326 1327 extern void cpu_cache_init(void); 1328 extern void tlb_init(void); 1329 extern void flush_tlb_handlers(void); 1330 1331 void __init per_cpu_trap_init(void) 1332 { 1333 unsigned int cpu = smp_processor_id(); 1334 unsigned int status_set = ST0_CU0; 1335 #ifdef CONFIG_MIPS_MT_SMTC 1336 int secondaryTC = 0; 1337 int bootTC = (cpu == 0); 1338 1339 /* 1340 * Only do per_cpu_trap_init() for first TC of Each VPE. 1341 * Note that this hack assumes that the SMTC init code 1342 * assigns TCs consecutively and in ascending order. 1343 */ 1344 1345 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 1346 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) 1347 secondaryTC = 1; 1348 #endif /* CONFIG_MIPS_MT_SMTC */ 1349 1350 /* 1351 * Disable coprocessors and select 32-bit or 64-bit addressing 1352 * and the 16/32 or 32/32 FPR register model. Reset the BEV 1353 * flag that some firmware may have left set and the TS bit (for 1354 * IP27). Set XX for ISA IV code to work. 1355 */ 1356 #ifdef CONFIG_64BIT 1357 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1358 #endif 1359 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1360 status_set |= ST0_XX; 1361 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1362 status_set); 1363 1364 if (cpu_has_dsp) 1365 set_c0_status(ST0_MX); 1366 1367 #ifdef CONFIG_CPU_MIPSR2 1368 if (cpu_has_mips_r2) { 1369 unsigned int enable = 0x0000000f; 1370 1371 if (cpu_has_userlocal) 1372 enable |= (1 << 29); 1373 1374 write_c0_hwrena(enable); 1375 } 1376 #endif 1377 1378 #ifdef CONFIG_MIPS_MT_SMTC 1379 if (!secondaryTC) { 1380 #endif /* CONFIG_MIPS_MT_SMTC */ 1381 1382 if (cpu_has_veic || cpu_has_vint) { 1383 write_c0_ebase(ebase); 1384 /* Setting vector spacing enables EI/VI mode */ 1385 change_c0_intctl(0x3e0, VECTORSPACING); 1386 } 1387 if (cpu_has_divec) { 1388 if (cpu_has_mipsmt) { 1389 unsigned int vpflags = dvpe(); 1390 set_c0_cause(CAUSEF_IV); 1391 evpe(vpflags); 1392 } else 1393 set_c0_cause(CAUSEF_IV); 1394 } 1395 1396 /* 1397 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 1398 * 1399 * o read IntCtl.IPTI to determine the timer interrupt 1400 * o read IntCtl.IPPCI to determine the performance counter interrupt 1401 */ 1402 if (cpu_has_mips_r2) { 1403 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1404 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1405 if (cp0_perfcount_irq == cp0_compare_irq) 1406 cp0_perfcount_irq = -1; 1407 } else { 1408 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1409 cp0_perfcount_irq = -1; 1410 } 1411 1412 #ifdef CONFIG_MIPS_MT_SMTC 1413 } 1414 #endif /* CONFIG_MIPS_MT_SMTC */ 1415 1416 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1417 TLBMISS_HANDLER_SETUP(); 1418 1419 atomic_inc(&init_mm.mm_count); 1420 current->active_mm = &init_mm; 1421 BUG_ON(current->mm); 1422 enter_lazy_tlb(&init_mm, current); 1423 1424 #ifdef CONFIG_MIPS_MT_SMTC 1425 if (bootTC) { 1426 #endif /* CONFIG_MIPS_MT_SMTC */ 1427 cpu_cache_init(); 1428 tlb_init(); 1429 #ifdef CONFIG_MIPS_MT_SMTC 1430 } else if (!secondaryTC) { 1431 /* 1432 * First TC in non-boot VPE must do subset of tlb_init() 1433 * for MMU countrol registers. 1434 */ 1435 write_c0_pagemask(PM_DEFAULT_MASK); 1436 write_c0_wired(0); 1437 } 1438 #endif /* CONFIG_MIPS_MT_SMTC */ 1439 } 1440 1441 /* Install CPU exception handler */ 1442 void __init set_handler(unsigned long offset, void *addr, unsigned long size) 1443 { 1444 memcpy((void *)(ebase + offset), addr, size); 1445 flush_icache_range(ebase + offset, ebase + offset + size); 1446 } 1447 1448 static char panic_null_cerr[] __initdata = 1449 "Trying to set NULL cache error exception handler"; 1450 1451 /* Install uncached CPU exception handler */ 1452 void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size) 1453 { 1454 #ifdef CONFIG_32BIT 1455 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1456 #endif 1457 #ifdef CONFIG_64BIT 1458 unsigned long uncached_ebase = TO_UNCAC(ebase); 1459 #endif 1460 1461 if (!addr) 1462 panic(panic_null_cerr); 1463 1464 memcpy((void *)(uncached_ebase + offset), addr, size); 1465 } 1466 1467 static int __initdata rdhwr_noopt; 1468 static int __init set_rdhwr_noopt(char *str) 1469 { 1470 rdhwr_noopt = 1; 1471 return 1; 1472 } 1473 1474 __setup("rdhwr_noopt", set_rdhwr_noopt); 1475 1476 void __init trap_init(void) 1477 { 1478 extern char except_vec3_generic, except_vec3_r4000; 1479 extern char except_vec4; 1480 unsigned long i; 1481 1482 if (cpu_has_veic || cpu_has_vint) 1483 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1484 else 1485 ebase = CAC_BASE; 1486 1487 mips_srs_init(); 1488 1489 per_cpu_trap_init(); 1490 1491 /* 1492 * Copy the generic exception handlers to their final destination. 1493 * This will be overriden later as suitable for a particular 1494 * configuration. 1495 */ 1496 set_handler(0x180, &except_vec3_generic, 0x80); 1497 1498 /* 1499 * Setup default vectors 1500 */ 1501 for (i = 0; i <= 31; i++) 1502 set_except_vector(i, handle_reserved); 1503 1504 /* 1505 * Copy the EJTAG debug exception vector handler code to it's final 1506 * destination. 1507 */ 1508 if (cpu_has_ejtag && board_ejtag_handler_setup) 1509 board_ejtag_handler_setup(); 1510 1511 /* 1512 * Only some CPUs have the watch exceptions. 1513 */ 1514 if (cpu_has_watch) 1515 set_except_vector(23, handle_watch); 1516 1517 /* 1518 * Initialise interrupt handlers 1519 */ 1520 if (cpu_has_veic || cpu_has_vint) { 1521 int nvec = cpu_has_veic ? 64 : 8; 1522 for (i = 0; i < nvec; i++) 1523 set_vi_handler(i, NULL); 1524 } 1525 else if (cpu_has_divec) 1526 set_handler(0x200, &except_vec4, 0x8); 1527 1528 /* 1529 * Some CPUs can enable/disable for cache parity detection, but does 1530 * it different ways. 1531 */ 1532 parity_protection_init(); 1533 1534 /* 1535 * The Data Bus Errors / Instruction Bus Errors are signaled 1536 * by external hardware. Therefore these two exceptions 1537 * may have board specific handlers. 1538 */ 1539 if (board_be_init) 1540 board_be_init(); 1541 1542 set_except_vector(0, handle_int); 1543 set_except_vector(1, handle_tlbm); 1544 set_except_vector(2, handle_tlbl); 1545 set_except_vector(3, handle_tlbs); 1546 1547 set_except_vector(4, handle_adel); 1548 set_except_vector(5, handle_ades); 1549 1550 set_except_vector(6, handle_ibe); 1551 set_except_vector(7, handle_dbe); 1552 1553 set_except_vector(8, handle_sys); 1554 set_except_vector(9, handle_bp); 1555 set_except_vector(10, rdhwr_noopt ? handle_ri : 1556 (cpu_has_vtag_icache ? 1557 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 1558 set_except_vector(11, handle_cpu); 1559 set_except_vector(12, handle_ov); 1560 set_except_vector(13, handle_tr); 1561 1562 if (current_cpu_type() == CPU_R6000 || 1563 current_cpu_type() == CPU_R6000A) { 1564 /* 1565 * The R6000 is the only R-series CPU that features a machine 1566 * check exception (similar to the R4000 cache error) and 1567 * unaligned ldc1/sdc1 exception. The handlers have not been 1568 * written yet. Well, anyway there is no R6000 machine on the 1569 * current list of targets for Linux/MIPS. 1570 * (Duh, crap, there is someone with a triple R6k machine) 1571 */ 1572 //set_except_vector(14, handle_mc); 1573 //set_except_vector(15, handle_ndc); 1574 } 1575 1576 1577 if (board_nmi_handler_setup) 1578 board_nmi_handler_setup(); 1579 1580 if (cpu_has_fpu && !cpu_has_nofpuex) 1581 set_except_vector(15, handle_fpe); 1582 1583 set_except_vector(22, handle_mdmx); 1584 1585 if (cpu_has_mcheck) 1586 set_except_vector(24, handle_mcheck); 1587 1588 if (cpu_has_mipsmt) 1589 set_except_vector(25, handle_mt); 1590 1591 set_except_vector(26, handle_dsp); 1592 1593 if (cpu_has_vce) 1594 /* Special exception: R4[04]00 uses also the divec space. */ 1595 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1596 else if (cpu_has_4kex) 1597 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1598 else 1599 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1600 1601 signal_init(); 1602 #ifdef CONFIG_MIPS32_COMPAT 1603 signal32_init(); 1604 #endif 1605 1606 flush_icache_range(ebase, ebase + 0x400); 1607 flush_tlb_handlers(); 1608 } 1609