1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * the definition file of cs5536 Virtual Support Module(VSM). 4 * pci configuration space can be accessed through the VSM, so 5 * there is no need of the MSR read/write now, except the spec. 6 * MSR registers which are not implemented yet. 7 * 8 * Copyright (C) 2007 Lemote Inc. 9 * Author : jlliu, liujl@lemote.com 10 */ 11 12 #ifndef _CS5536_PCI_H 13 #define _CS5536_PCI_H 14 15 #include <linux/types.h> 16 #include <linux/pci_regs.h> 17 18 extern void cs5536_pci_conf_write4(int function, int reg, u32 value); 19 extern u32 cs5536_pci_conf_read4(int function, int reg); 20 21 #define CS5536_ACC_INTR 9 22 #define CS5536_IDE_INTR 14 23 #define CS5536_USB_INTR 11 24 #define CS5536_MFGPT_INTR 5 25 #define CS5536_UART1_INTR 4 26 #define CS5536_UART2_INTR 3 27 28 /************** PCI BUS DEVICE FUNCTION ***************/ 29 30 /* 31 * PCI bus device function 32 */ 33 #define PCI_BUS_CS5536 0 34 #define PCI_IDSEL_CS5536 14 35 36 /********** STANDARD PCI-2.2 EXPANSION ****************/ 37 38 /* 39 * PCI configuration space 40 * we have to virtualize the PCI configure space head, so we should 41 * define the necessary IDs and some others. 42 */ 43 44 /* CONFIG of PCI VENDOR ID*/ 45 #define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ 46 (((mod_dev_id) << 16) | (sys_vendor_id)) 47 48 /* VENDOR ID */ 49 #define CS5536_VENDOR_ID 0x1022 50 51 /* DEVICE ID */ 52 #define CS5536_ISA_DEVICE_ID 0x2090 53 #define CS5536_IDE_DEVICE_ID 0x209a 54 #define CS5536_ACC_DEVICE_ID 0x2093 55 #define CS5536_OHCI_DEVICE_ID 0x2094 56 #define CS5536_EHCI_DEVICE_ID 0x2095 57 58 /* CLASS CODE : CLASS SUB-CLASS INTERFACE */ 59 #define CS5536_ISA_CLASS_CODE 0x060100 60 #define CS5536_IDE_CLASS_CODE 0x010180 61 #define CS5536_ACC_CLASS_CODE 0x040100 62 #define CS5536_OHCI_CLASS_CODE 0x0C0310 63 #define CS5536_EHCI_CLASS_CODE 0x0C0320 64 65 /* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ 66 67 #define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ 68 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ 69 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); 70 71 #define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ 72 #define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ 73 #define PCI_NORMAL_HEADER_TYPE 0x00 74 #define PCI_NORMAL_LATENCY_TIMER 0x00 75 #define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ 76 77 /* BAR */ 78 #define PCI_BAR0_REG 0x10 79 #define PCI_BAR1_REG 0x14 80 #define PCI_BAR2_REG 0x18 81 #define PCI_BAR3_REG 0x1c 82 #define PCI_BAR4_REG 0x20 83 #define PCI_BAR5_REG 0x24 84 #define PCI_BAR_RANGE_MASK 0xFFFFFFFF 85 86 /* CARDBUS CIS POINTER */ 87 #define PCI_CARDBUS_CIS_POINTER 0x00000000 88 89 /* SUBSYSTEM VENDOR ID */ 90 #define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID 91 92 /* SUBSYSTEM ID */ 93 #define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID 94 #define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID 95 #define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID 96 #define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID 97 #define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID 98 99 /* EXPANSION ROM BAR */ 100 #define PCI_EXPANSION_ROM_BAR 0x00000000 101 102 /* CAPABILITIES POINTER */ 103 #define PCI_CAPLIST_POINTER 0x00000000 104 #define PCI_CAPLIST_USB_POINTER 0x40 105 /* INTERRUPT */ 106 107 #define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ 108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ 109 ((pin) << 8) | (mod_intr)) 110 111 #define PCI_MAX_LATENCY 0x40 112 #define PCI_MIN_GRANT 0x00 113 #define PCI_DEFAULT_PIN 0x01 114 115 /*********** EXPANSION PCI REG ************************/ 116 117 /* 118 * ISA EXPANSION 119 */ 120 #define PCI_UART1_INT_REG 0x50 121 #define PCI_UART2_INT_REG 0x54 122 #define PCI_ISA_FIXUP_REG 0x58 123 124 /* 125 * IDE EXPANSION 126 */ 127 #define PCI_IDE_CFG_REG 0x40 128 #define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF 129 #define PCI_IDE_DTC_REG 0x48 130 #define PCI_IDE_CAST_REG 0x4C 131 #define PCI_IDE_ETC_REG 0x50 132 #define PCI_IDE_PM_REG 0x54 133 #define PCI_IDE_INT_REG 0x60 134 135 /* 136 * ACC EXPANSION 137 */ 138 #define PCI_ACC_INT_REG 0x50 139 140 /* 141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI 142 */ 143 #define PCI_OHCI_PM_REG 0x40 144 #define PCI_OHCI_INT_REG 0x50 145 146 /* 147 * EHCI EXPANSION 148 */ 149 #define PCI_EHCI_LEGSMIEN_REG 0x50 150 #define PCI_EHCI_LEGSMISTS_REG 0x54 151 #define PCI_EHCI_FLADJ_REG 0x60 152 153 #endif /* _CS5536_PCI_H_ */ 154