123a271ecSDavid Daneyif CPU_CAVIUM_OCTEON 25b3b1688SDavid Daney 3c9941158SDavid Daneyconfig CAVIUM_CN63XXP1 4c9941158SDavid Daney bool "Enable CN63XXP1 errata worarounds" 5c9941158SDavid Daney default "n" 6c9941158SDavid Daney help 7c9941158SDavid Daney The CN63XXP1 chip requires build time workarounds to 8c9941158SDavid Daney function reliably, select this option to enable them. These 9c9941158SDavid Daney workarounds will cause a slight decrease in performance on 10c9941158SDavid Daney non-CN63XXP1 hardware, so it is recommended to select "n" 11c9941158SDavid Daney unless it is known the workarounds are needed. 12c9941158SDavid Daney 13*9ddebc46SDavid Daneyendif # CPU_CAVIUM_OCTEON 14*9ddebc46SDavid Daney 15*9ddebc46SDavid Daneyif CAVIUM_OCTEON_SOC 16*9ddebc46SDavid Daney 175b3b1688SDavid Daneyconfig CAVIUM_OCTEON_2ND_KERNEL 185b3b1688SDavid Daney bool "Build the kernel to be used as a 2nd kernel on the same chip" 195b3b1688SDavid Daney default "n" 205b3b1688SDavid Daney help 215b3b1688SDavid Daney This option configures this kernel to be linked at a different 225b3b1688SDavid Daney address and use the 2nd uart for output. This allows a kernel built 235b3b1688SDavid Daney with this option to be run at the same time as one built without this 245b3b1688SDavid Daney option. 255b3b1688SDavid Daney 265b3b1688SDavid Daneyconfig CAVIUM_OCTEON_HW_FIX_UNALIGNED 275b3b1688SDavid Daney bool "Enable hardware fixups of unaligned loads and stores" 285b3b1688SDavid Daney default "y" 295b3b1688SDavid Daney help 305b3b1688SDavid Daney Configure the Octeon hardware to automatically fix unaligned loads 315b3b1688SDavid Daney and stores. Normally unaligned accesses are fixed using a kernel 325b3b1688SDavid Daney exception handler. This option enables the hardware automatic fixups, 335b3b1688SDavid Daney which requires only an extra 3 cycles. Disable this option if you 345b3b1688SDavid Daney are running code that relies on address exceptions on unaligned 355b3b1688SDavid Daney accesses. 365b3b1688SDavid Daney 375b3b1688SDavid Daneyconfig CAVIUM_OCTEON_CVMSEG_SIZE 385b3b1688SDavid Daney int "Number of L1 cache lines reserved for CVMSEG memory" 395b3b1688SDavid Daney range 0 54 405b3b1688SDavid Daney default 1 415b3b1688SDavid Daney help 425b3b1688SDavid Daney CVMSEG LM is a segment that accesses portions of the dcache as a 435b3b1688SDavid Daney local memory; the larger CVMSEG is, the smaller the cache is. 445b3b1688SDavid Daney This selects the size of CVMSEG LM, which is in cache blocks. The 455b3b1688SDavid Daney legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 465b3b1688SDavid Daney between zero and 6192 bytes). 475b3b1688SDavid Daney 485b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2 495b3b1688SDavid Daney bool "Lock often used kernel code in the L2" 505b3b1688SDavid Daney default "y" 515b3b1688SDavid Daney help 525b3b1688SDavid Daney Enable locking parts of the kernel into the L2 cache. 535b3b1688SDavid Daney 545b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_TLB 555b3b1688SDavid Daney bool "Lock the TLB handler in L2" 565b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 575b3b1688SDavid Daney default "y" 585b3b1688SDavid Daney help 595b3b1688SDavid Daney Lock the low level TLB fast path into L2. 605b3b1688SDavid Daney 615b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 625b3b1688SDavid Daney bool "Lock the exception handler in L2" 635b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 645b3b1688SDavid Daney default "y" 655b3b1688SDavid Daney help 665b3b1688SDavid Daney Lock the low level exception handler into L2. 675b3b1688SDavid Daney 685b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 695b3b1688SDavid Daney bool "Lock the interrupt handler in L2" 705b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 715b3b1688SDavid Daney default "y" 725b3b1688SDavid Daney help 735b3b1688SDavid Daney Lock the low level interrupt handler into L2. 745b3b1688SDavid Daney 755b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 765b3b1688SDavid Daney bool "Lock the 2nd level interrupt handler in L2" 775b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 785b3b1688SDavid Daney default "y" 795b3b1688SDavid Daney help 805b3b1688SDavid Daney Lock the 2nd level interrupt handler in L2. 815b3b1688SDavid Daney 825b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 835b3b1688SDavid Daney bool "Lock memcpy() in L2" 845b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 855b3b1688SDavid Daney default "y" 865b3b1688SDavid Daney help 875b3b1688SDavid Daney Lock the kernel's implementation of memcpy() into L2. 885b3b1688SDavid Daney 89b93b2abcSDavid Daneyconfig IOMMU_HELPER 90b93b2abcSDavid Daney bool 91b93b2abcSDavid Daney 92b93b2abcSDavid Daneyconfig NEED_SG_DMA_LENGTH 93b93b2abcSDavid Daney bool 94b93b2abcSDavid Daney 95b93b2abcSDavid Daneyconfig SWIOTLB 96b93b2abcSDavid Daney def_bool y 97b93b2abcSDavid Daney select IOMMU_HELPER 98b93b2abcSDavid Daney select NEED_SG_DMA_LENGTH 9923a271ecSDavid Daney 10023a271ecSDavid Daney 1010e49caf6SVenkat Subbiahconfig OCTEON_ILM 1020e49caf6SVenkat Subbiah tristate "Module to measure interrupt latency using Octeon CIU Timer" 1030e49caf6SVenkat Subbiah help 1040e49caf6SVenkat Subbiah This driver is a module to measure interrupt latency using the 1050e49caf6SVenkat Subbiah the CIU Timers on Octeon. 1060e49caf6SVenkat Subbiah 1070e49caf6SVenkat Subbiah To compile this driver as a module, choose M here. The module 1080e49caf6SVenkat Subbiah will be called octeon-ilm 1090e49caf6SVenkat Subbiah 110*9ddebc46SDavid Daneyendif # CAVIUM_OCTEON_SOC 111