1# SPDX-License-Identifier: GPL-2.0 2if CPU_CAVIUM_OCTEON 3 4config CAVIUM_CN63XXP1 5 bool "Enable CN63XXP1 errata workarounds" 6 default "n" 7 help 8 The CN63XXP1 chip requires build time workarounds to 9 function reliably, select this option to enable them. These 10 workarounds will cause a slight decrease in performance on 11 non-CN63XXP1 hardware, so it is recommended to select "n" 12 unless it is known the workarounds are needed. 13 14config CAVIUM_OCTEON_CVMSEG_SIZE 15 int "Number of L1 cache lines reserved for CVMSEG memory" 16 range 0 54 17 default 0 if !CAVIUM_OCTEON_SOC 18 default 1 if CAVIUM_OCTEON_SOC 19 help 20 CVMSEG LM is a segment that accesses portions of the dcache as a 21 local memory; the larger CVMSEG is, the smaller the cache is. 22 This selects the size of CVMSEG LM, which is in cache blocks. The 23 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 24 between zero and 6192 bytes). 25 26config CRYPTO_SHA256_OCTEON 27 tristate 28 default CRYPTO_LIB_SHA256 29 select CRYPTO_ARCH_HAVE_LIB_SHA256 30 select CRYPTO_LIB_SHA256_GENERIC 31 32endif # CPU_CAVIUM_OCTEON 33 34if CAVIUM_OCTEON_SOC 35 36config CAVIUM_OCTEON_LOCK_L2 37 bool "Lock often used kernel code in the L2" 38 default "y" 39 help 40 Enable locking parts of the kernel into the L2 cache. 41 42config CAVIUM_OCTEON_LOCK_L2_TLB 43 bool "Lock the TLB handler in L2" 44 depends on CAVIUM_OCTEON_LOCK_L2 45 default "y" 46 help 47 Lock the low level TLB fast path into L2. 48 49config CAVIUM_OCTEON_LOCK_L2_EXCEPTION 50 bool "Lock the exception handler in L2" 51 depends on CAVIUM_OCTEON_LOCK_L2 52 default "y" 53 help 54 Lock the low level exception handler into L2. 55 56config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 57 bool "Lock the interrupt handler in L2" 58 depends on CAVIUM_OCTEON_LOCK_L2 59 default "y" 60 help 61 Lock the low level interrupt handler into L2. 62 63config CAVIUM_OCTEON_LOCK_L2_INTERRUPT 64 bool "Lock the 2nd level interrupt handler in L2" 65 depends on CAVIUM_OCTEON_LOCK_L2 66 default "y" 67 help 68 Lock the 2nd level interrupt handler in L2. 69 70config CAVIUM_OCTEON_LOCK_L2_MEMCPY 71 bool "Lock memcpy() in L2" 72 depends on CAVIUM_OCTEON_LOCK_L2 73 default "y" 74 help 75 Lock the kernel's implementation of memcpy() into L2. 76 77config CAVIUM_RESERVE32 78 int "Memory to reserve for user processes shared region (MB)" 79 range 0 1536 80 default "0" 81 help 82 Reserve a shared memory region for user processes to use for hardware 83 memory buffers. This is required for 32bit applications to be able to 84 send and receive packets directly. Applications access this memory by 85 memory mapping /dev/mem for the addresses in /proc/octeon_info. For 86 optimal performance with HugeTLBs, keep this size an even number of 87 megabytes. 88 89config OCTEON_ILM 90 tristate "Module to measure interrupt latency using Octeon CIU Timer" 91 help 92 This driver is a module to measure interrupt latency using the 93 the CIU Timers on Octeon. 94 95 To compile this driver as a module, choose M here. The module 96 will be called octeon-ilm 97 98endif # CAVIUM_OCTEON_SOC 99