123a271ecSDavid Daneyif CPU_CAVIUM_OCTEON 25b3b1688SDavid Daney 3c9941158SDavid Daneyconfig CAVIUM_CN63XXP1 4c9941158SDavid Daney bool "Enable CN63XXP1 errata worarounds" 5c9941158SDavid Daney default "n" 6c9941158SDavid Daney help 7c9941158SDavid Daney The CN63XXP1 chip requires build time workarounds to 8c9941158SDavid Daney function reliably, select this option to enable them. These 9c9941158SDavid Daney workarounds will cause a slight decrease in performance on 10c9941158SDavid Daney non-CN63XXP1 hardware, so it is recommended to select "n" 11c9941158SDavid Daney unless it is known the workarounds are needed. 12c9941158SDavid Daney 13*8a837cdbSDavid Daneyconfig CAVIUM_OCTEON_CVMSEG_SIZE 14*8a837cdbSDavid Daney int "Number of L1 cache lines reserved for CVMSEG memory" 15*8a837cdbSDavid Daney range 0 54 16*8a837cdbSDavid Daney default 1 17*8a837cdbSDavid Daney help 18*8a837cdbSDavid Daney CVMSEG LM is a segment that accesses portions of the dcache as a 19*8a837cdbSDavid Daney local memory; the larger CVMSEG is, the smaller the cache is. 20*8a837cdbSDavid Daney This selects the size of CVMSEG LM, which is in cache blocks. The 21*8a837cdbSDavid Daney legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 22*8a837cdbSDavid Daney between zero and 6192 bytes). 23*8a837cdbSDavid Daney 249ddebc46SDavid Daneyendif # CPU_CAVIUM_OCTEON 259ddebc46SDavid Daney 269ddebc46SDavid Daneyif CAVIUM_OCTEON_SOC 279ddebc46SDavid Daney 285b3b1688SDavid Daneyconfig CAVIUM_OCTEON_2ND_KERNEL 295b3b1688SDavid Daney bool "Build the kernel to be used as a 2nd kernel on the same chip" 305b3b1688SDavid Daney default "n" 315b3b1688SDavid Daney help 325b3b1688SDavid Daney This option configures this kernel to be linked at a different 335b3b1688SDavid Daney address and use the 2nd uart for output. This allows a kernel built 345b3b1688SDavid Daney with this option to be run at the same time as one built without this 355b3b1688SDavid Daney option. 365b3b1688SDavid Daney 375b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2 385b3b1688SDavid Daney bool "Lock often used kernel code in the L2" 395b3b1688SDavid Daney default "y" 405b3b1688SDavid Daney help 415b3b1688SDavid Daney Enable locking parts of the kernel into the L2 cache. 425b3b1688SDavid Daney 435b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_TLB 445b3b1688SDavid Daney bool "Lock the TLB handler in L2" 455b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 465b3b1688SDavid Daney default "y" 475b3b1688SDavid Daney help 485b3b1688SDavid Daney Lock the low level TLB fast path into L2. 495b3b1688SDavid Daney 505b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 515b3b1688SDavid Daney bool "Lock the exception handler in L2" 525b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 535b3b1688SDavid Daney default "y" 545b3b1688SDavid Daney help 555b3b1688SDavid Daney Lock the low level exception handler into L2. 565b3b1688SDavid Daney 575b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 585b3b1688SDavid Daney bool "Lock the interrupt handler in L2" 595b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 605b3b1688SDavid Daney default "y" 615b3b1688SDavid Daney help 625b3b1688SDavid Daney Lock the low level interrupt handler into L2. 635b3b1688SDavid Daney 645b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 655b3b1688SDavid Daney bool "Lock the 2nd level interrupt handler in L2" 665b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 675b3b1688SDavid Daney default "y" 685b3b1688SDavid Daney help 695b3b1688SDavid Daney Lock the 2nd level interrupt handler in L2. 705b3b1688SDavid Daney 715b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 725b3b1688SDavid Daney bool "Lock memcpy() in L2" 735b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 745b3b1688SDavid Daney default "y" 755b3b1688SDavid Daney help 765b3b1688SDavid Daney Lock the kernel's implementation of memcpy() into L2. 775b3b1688SDavid Daney 78b93b2abcSDavid Daneyconfig IOMMU_HELPER 79b93b2abcSDavid Daney bool 80b93b2abcSDavid Daney 81b93b2abcSDavid Daneyconfig NEED_SG_DMA_LENGTH 82b93b2abcSDavid Daney bool 83b93b2abcSDavid Daney 84b93b2abcSDavid Daneyconfig SWIOTLB 85b93b2abcSDavid Daney def_bool y 86b93b2abcSDavid Daney select IOMMU_HELPER 87b93b2abcSDavid Daney select NEED_SG_DMA_LENGTH 8823a271ecSDavid Daney 890e49caf6SVenkat Subbiahconfig OCTEON_ILM 900e49caf6SVenkat Subbiah tristate "Module to measure interrupt latency using Octeon CIU Timer" 910e49caf6SVenkat Subbiah help 920e49caf6SVenkat Subbiah This driver is a module to measure interrupt latency using the 930e49caf6SVenkat Subbiah the CIU Timers on Octeon. 940e49caf6SVenkat Subbiah 950e49caf6SVenkat Subbiah To compile this driver as a module, choose M here. The module 960e49caf6SVenkat Subbiah will be called octeon-ilm 970e49caf6SVenkat Subbiah 989ddebc46SDavid Daneyendif # CAVIUM_OCTEON_SOC 99