1*23a271ecSDavid Daneyif CPU_CAVIUM_OCTEON 25b3b1688SDavid Daney 3c9941158SDavid Daneyconfig CAVIUM_CN63XXP1 4c9941158SDavid Daney bool "Enable CN63XXP1 errata worarounds" 5c9941158SDavid Daney default "n" 6c9941158SDavid Daney help 7c9941158SDavid Daney The CN63XXP1 chip requires build time workarounds to 8c9941158SDavid Daney function reliably, select this option to enable them. These 9c9941158SDavid Daney workarounds will cause a slight decrease in performance on 10c9941158SDavid Daney non-CN63XXP1 hardware, so it is recommended to select "n" 11c9941158SDavid Daney unless it is known the workarounds are needed. 12c9941158SDavid Daney 135b3b1688SDavid Daneyconfig CAVIUM_OCTEON_2ND_KERNEL 145b3b1688SDavid Daney bool "Build the kernel to be used as a 2nd kernel on the same chip" 155b3b1688SDavid Daney default "n" 165b3b1688SDavid Daney help 175b3b1688SDavid Daney This option configures this kernel to be linked at a different 185b3b1688SDavid Daney address and use the 2nd uart for output. This allows a kernel built 195b3b1688SDavid Daney with this option to be run at the same time as one built without this 205b3b1688SDavid Daney option. 215b3b1688SDavid Daney 225b3b1688SDavid Daneyconfig CAVIUM_OCTEON_HW_FIX_UNALIGNED 235b3b1688SDavid Daney bool "Enable hardware fixups of unaligned loads and stores" 245b3b1688SDavid Daney default "y" 255b3b1688SDavid Daney help 265b3b1688SDavid Daney Configure the Octeon hardware to automatically fix unaligned loads 275b3b1688SDavid Daney and stores. Normally unaligned accesses are fixed using a kernel 285b3b1688SDavid Daney exception handler. This option enables the hardware automatic fixups, 295b3b1688SDavid Daney which requires only an extra 3 cycles. Disable this option if you 305b3b1688SDavid Daney are running code that relies on address exceptions on unaligned 315b3b1688SDavid Daney accesses. 325b3b1688SDavid Daney 335b3b1688SDavid Daneyconfig CAVIUM_OCTEON_CVMSEG_SIZE 345b3b1688SDavid Daney int "Number of L1 cache lines reserved for CVMSEG memory" 355b3b1688SDavid Daney range 0 54 365b3b1688SDavid Daney default 1 375b3b1688SDavid Daney help 385b3b1688SDavid Daney CVMSEG LM is a segment that accesses portions of the dcache as a 395b3b1688SDavid Daney local memory; the larger CVMSEG is, the smaller the cache is. 405b3b1688SDavid Daney This selects the size of CVMSEG LM, which is in cache blocks. The 415b3b1688SDavid Daney legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 425b3b1688SDavid Daney between zero and 6192 bytes). 435b3b1688SDavid Daney 445b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2 455b3b1688SDavid Daney bool "Lock often used kernel code in the L2" 465b3b1688SDavid Daney default "y" 475b3b1688SDavid Daney help 485b3b1688SDavid Daney Enable locking parts of the kernel into the L2 cache. 495b3b1688SDavid Daney 505b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_TLB 515b3b1688SDavid Daney bool "Lock the TLB handler in L2" 525b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 535b3b1688SDavid Daney default "y" 545b3b1688SDavid Daney help 555b3b1688SDavid Daney Lock the low level TLB fast path into L2. 565b3b1688SDavid Daney 575b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 585b3b1688SDavid Daney bool "Lock the exception handler in L2" 595b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 605b3b1688SDavid Daney default "y" 615b3b1688SDavid Daney help 625b3b1688SDavid Daney Lock the low level exception handler into L2. 635b3b1688SDavid Daney 645b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 655b3b1688SDavid Daney bool "Lock the interrupt handler in L2" 665b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 675b3b1688SDavid Daney default "y" 685b3b1688SDavid Daney help 695b3b1688SDavid Daney Lock the low level interrupt handler into L2. 705b3b1688SDavid Daney 715b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 725b3b1688SDavid Daney bool "Lock the 2nd level interrupt handler in L2" 735b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 745b3b1688SDavid Daney default "y" 755b3b1688SDavid Daney help 765b3b1688SDavid Daney Lock the 2nd level interrupt handler in L2. 775b3b1688SDavid Daney 785b3b1688SDavid Daneyconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 795b3b1688SDavid Daney bool "Lock memcpy() in L2" 805b3b1688SDavid Daney depends on CAVIUM_OCTEON_LOCK_L2 815b3b1688SDavid Daney default "y" 825b3b1688SDavid Daney help 835b3b1688SDavid Daney Lock the kernel's implementation of memcpy() into L2. 845b3b1688SDavid Daney 855b3b1688SDavid Daneyconfig ARCH_SPARSEMEM_ENABLE 865b3b1688SDavid Daney def_bool y 875b3b1688SDavid Daney select SPARSEMEM_STATIC 881ec0e739SAndreas Bießmann 891ec0e739SAndreas Bießmannconfig CAVIUM_OCTEON_HELPER 901ec0e739SAndreas Bießmann def_bool y 911ec0e739SAndreas Bießmann depends on OCTEON_ETHERNET || PCI 92b93b2abcSDavid Daney 93b93b2abcSDavid Daneyconfig IOMMU_HELPER 94b93b2abcSDavid Daney bool 95b93b2abcSDavid Daney 96b93b2abcSDavid Daneyconfig NEED_SG_DMA_LENGTH 97b93b2abcSDavid Daney bool 98b93b2abcSDavid Daney 99b93b2abcSDavid Daneyconfig SWIOTLB 100b93b2abcSDavid Daney def_bool y 101b93b2abcSDavid Daney select IOMMU_HELPER 102b93b2abcSDavid Daney select NEED_SG_DMA_LENGTH 103*23a271ecSDavid Daney 104*23a271ecSDavid Daney 105*23a271ecSDavid Daneyendif # CPU_CAVIUM_OCTEON 106