1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2017 Microsemi Corporation */ 3 4/dts-v1/; 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/phy/phy-ocelot-serdes.h> 8#include "ocelot.dtsi" 9 10/ { 11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot"; 12 13 chosen { 14 stdout-path = "serial0:115200n8"; 15 }; 16 17 memory@0 { 18 device_type = "memory"; 19 reg = <0x0 0x0e000000>; 20 }; 21}; 22 23&gpio { 24 phy_int_pins: phy_int_pins { 25 pins = "GPIO_4"; 26 function = "gpio"; 27 }; 28}; 29 30&mdio0 { 31 status = "okay"; 32}; 33 34&mdio1 { 35 status = "okay"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&miim1>, <&phy_int_pins>; 38 39 phy7: ethernet-phy@0 { 40 reg = <0>; 41 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 42 interrupt-parent = <&gpio>; 43 }; 44 phy6: ethernet-phy@1 { 45 reg = <1>; 46 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 47 interrupt-parent = <&gpio>; 48 }; 49 phy5: ethernet-phy@2 { 50 reg = <2>; 51 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 52 interrupt-parent = <&gpio>; 53 }; 54 phy4: ethernet-phy@3 { 55 reg = <3>; 56 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-parent = <&gpio>; 58 }; 59}; 60 61&port0 { 62 phy-handle = <&phy0>; 63}; 64 65&port1 { 66 phy-handle = <&phy1>; 67}; 68 69&port2 { 70 phy-handle = <&phy2>; 71}; 72 73&port3 { 74 phy-handle = <&phy3>; 75}; 76 77&port4 { 78 phy-handle = <&phy7>; 79 phy-mode = "sgmii"; 80 phys = <&serdes 4 SERDES1G(2)>; 81}; 82 83&port5 { 84 phy-handle = <&phy4>; 85 phy-mode = "sgmii"; 86 phys = <&serdes 5 SERDES1G(5)>; 87}; 88 89&port6 { 90 phy-handle = <&phy6>; 91 phy-mode = "sgmii"; 92 phys = <&serdes 6 SERDES1G(3)>; 93}; 94 95&port9 { 96 phy-handle = <&phy5>; 97 phy-mode = "sgmii"; 98 phys = <&serdes 9 SERDES1G(4)>; 99}; 100 101&uart0 { 102 status = "okay"; 103}; 104 105&uart2 { 106 status = "okay"; 107}; 108