xref: /linux/arch/mips/boot/dts/mscc/ocelot_pcb120.dts (revision 4f2c0a4acffbec01079c28f839422e64ddeff004) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/dts-v1/;
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/phy/phy-ocelot-serdes.h>
9#include "ocelot.dtsi"
10
11/ {
12	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
13
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	memory@0 {
19		device_type = "memory";
20		reg = <0x0 0x0e000000>;
21	};
22};
23
24&gpio {
25	phy_int_pins: phy-int-pins {
26		pins = "GPIO_4";
27		function = "gpio";
28	};
29
30	phy_load_save_pins: phy-load-save-pins {
31		pins = "GPIO_10";
32		function = "ptp2";
33	};
34};
35
36&mdio0 {
37	status = "okay";
38};
39
40&mdio1 {
41	status = "okay";
42	pinctrl-names = "default";
43	pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
44
45	phy7: ethernet-phy@0 {
46		reg = <0>;
47		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
48		interrupt-parent = <&gpio>;
49		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
50	};
51	phy6: ethernet-phy@1 {
52		reg = <1>;
53		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
54		interrupt-parent = <&gpio>;
55		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
56	};
57	phy5: ethernet-phy@2 {
58		reg = <2>;
59		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
60		interrupt-parent = <&gpio>;
61		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
62	};
63	phy4: ethernet-phy@3 {
64		reg = <3>;
65		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
66		interrupt-parent = <&gpio>;
67		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
68	};
69};
70
71&port0 {
72	status = "okay";
73	phy-handle = <&phy0>;
74	phy-mode = "internal";
75};
76
77&port1 {
78	status = "okay";
79	phy-handle = <&phy1>;
80	phy-mode = "internal";
81};
82
83&port2 {
84	status = "okay";
85	phy-handle = <&phy2>;
86	phy-mode = "internal";
87};
88
89&port3 {
90	status = "okay";
91	phy-handle = <&phy3>;
92	phy-mode = "internal";
93};
94
95&port4 {
96	status = "okay";
97	phy-handle = <&phy7>;
98	phy-mode = "sgmii";
99	phys = <&serdes 4 SERDES1G(2)>;
100};
101
102&port5 {
103	status = "okay";
104	phy-handle = <&phy4>;
105	phy-mode = "sgmii";
106	phys = <&serdes 5 SERDES1G(5)>;
107};
108
109&port6 {
110	status = "okay";
111	phy-handle = <&phy6>;
112	phy-mode = "sgmii";
113	phys = <&serdes 6 SERDES1G(3)>;
114};
115
116&port9 {
117	status = "okay";
118	phy-handle = <&phy5>;
119	phy-mode = "sgmii";
120	phys = <&serdes 9 SERDES1G(4)>;
121};
122
123&uart0 {
124	status = "okay";
125};
126
127&uart2 {
128	status = "okay";
129};
130