xref: /linux/arch/loongarch/kernel/smp.c (revision 9ad28ba1c6f054ef801bcd63c5b73792b4b1d9a4)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4  *
5  * Derived from MIPS:
6  * Copyright (C) 2000, 2001 Kanoj Sarcar
7  * Copyright (C) 2000, 2001 Ralf Baechle
8  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
9  * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
10  */
11 #include <linux/cpu.h>
12 #include <linux/cpumask.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/seq_file.h>
16 #include <linux/smp.h>
17 #include <linux/threads.h>
18 #include <linux/export.h>
19 #include <linux/time.h>
20 #include <linux/tracepoint.h>
21 #include <linux/sched/hotplug.h>
22 #include <linux/sched/task_stack.h>
23 
24 #include <asm/cpu.h>
25 #include <asm/idle.h>
26 #include <asm/loongson.h>
27 #include <asm/mmu_context.h>
28 #include <asm/numa.h>
29 #include <asm/processor.h>
30 #include <asm/setup.h>
31 #include <asm/time.h>
32 
33 int __cpu_number_map[NR_CPUS];   /* Map physical to logical */
34 EXPORT_SYMBOL(__cpu_number_map);
35 
36 int __cpu_logical_map[NR_CPUS];		/* Map logical to physical */
37 EXPORT_SYMBOL(__cpu_logical_map);
38 
39 /* Number of threads (siblings) per CPU core */
40 int smp_num_siblings = 1;
41 EXPORT_SYMBOL(smp_num_siblings);
42 
43 /* Representing the threads (siblings) of each logical CPU */
44 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
45 EXPORT_SYMBOL(cpu_sibling_map);
46 
47 /* Representing the core map of multi-core chips of each logical CPU */
48 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
49 EXPORT_SYMBOL(cpu_core_map);
50 
51 static DECLARE_COMPLETION(cpu_starting);
52 static DECLARE_COMPLETION(cpu_running);
53 
54 /*
55  * A logcal cpu mask containing only one VPE per core to
56  * reduce the number of IPIs on large MT systems.
57  */
58 cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
59 EXPORT_SYMBOL(cpu_foreign_map);
60 
61 /* representing cpus for which sibling maps can be computed */
62 static cpumask_t cpu_sibling_setup_map;
63 
64 /* representing cpus for which core maps can be computed */
65 static cpumask_t cpu_core_setup_map;
66 
67 struct secondary_data cpuboot_data;
68 static DEFINE_PER_CPU(int, cpu_state);
69 
70 enum ipi_msg_type {
71 	IPI_RESCHEDULE,
72 	IPI_CALL_FUNCTION,
73 };
74 
75 static const char *ipi_types[NR_IPI] __tracepoint_string = {
76 	[IPI_RESCHEDULE] = "Rescheduling interrupts",
77 	[IPI_CALL_FUNCTION] = "Function call interrupts",
78 };
79 
80 void show_ipi_list(struct seq_file *p, int prec)
81 {
82 	unsigned int cpu, i;
83 
84 	for (i = 0; i < NR_IPI; i++) {
85 		seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >= 4 ? " " : "");
86 		for_each_online_cpu(cpu)
87 			seq_printf(p, "%10u ", per_cpu(irq_stat, cpu).ipi_irqs[i]);
88 		seq_printf(p, " LoongArch  %d  %s\n", i + 1, ipi_types[i]);
89 	}
90 }
91 
92 /* Send mailbox buffer via Mail_Send */
93 static void csr_mail_send(uint64_t data, int cpu, int mailbox)
94 {
95 	uint64_t val;
96 
97 	/* Send high 32 bits */
98 	val = IOCSR_MBUF_SEND_BLOCKING;
99 	val |= (IOCSR_MBUF_SEND_BOX_HI(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
100 	val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
101 	val |= (data & IOCSR_MBUF_SEND_H32_MASK);
102 	iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
103 
104 	/* Send low 32 bits */
105 	val = IOCSR_MBUF_SEND_BLOCKING;
106 	val |= (IOCSR_MBUF_SEND_BOX_LO(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
107 	val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
108 	val |= (data << IOCSR_MBUF_SEND_BUF_SHIFT);
109 	iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
110 };
111 
112 static u32 ipi_read_clear(int cpu)
113 {
114 	u32 action;
115 
116 	/* Load the ipi register to figure out what we're supposed to do */
117 	action = iocsr_read32(LOONGARCH_IOCSR_IPI_STATUS);
118 	/* Clear the ipi register to clear the interrupt */
119 	iocsr_write32(action, LOONGARCH_IOCSR_IPI_CLEAR);
120 	smp_mb();
121 
122 	return action;
123 }
124 
125 static void ipi_write_action(int cpu, u32 action)
126 {
127 	unsigned int irq = 0;
128 
129 	while ((irq = ffs(action))) {
130 		uint32_t val = IOCSR_IPI_SEND_BLOCKING;
131 
132 		val |= (irq - 1);
133 		val |= (cpu << IOCSR_IPI_SEND_CPU_SHIFT);
134 		iocsr_write32(val, LOONGARCH_IOCSR_IPI_SEND);
135 		action &= ~BIT(irq - 1);
136 	}
137 }
138 
139 void loongson_send_ipi_single(int cpu, unsigned int action)
140 {
141 	ipi_write_action(cpu_logical_map(cpu), (u32)action);
142 }
143 
144 void loongson_send_ipi_mask(const struct cpumask *mask, unsigned int action)
145 {
146 	unsigned int i;
147 
148 	for_each_cpu(i, mask)
149 		ipi_write_action(cpu_logical_map(i), (u32)action);
150 }
151 
152 irqreturn_t loongson_ipi_interrupt(int irq, void *dev)
153 {
154 	unsigned int action;
155 	unsigned int cpu = smp_processor_id();
156 
157 	action = ipi_read_clear(cpu_logical_map(cpu));
158 
159 	if (action & SMP_RESCHEDULE) {
160 		scheduler_ipi();
161 		per_cpu(irq_stat, cpu).ipi_irqs[IPI_RESCHEDULE]++;
162 	}
163 
164 	if (action & SMP_CALL_FUNCTION) {
165 		generic_smp_call_function_interrupt();
166 		per_cpu(irq_stat, cpu).ipi_irqs[IPI_CALL_FUNCTION]++;
167 	}
168 
169 	return IRQ_HANDLED;
170 }
171 
172 void __init loongson_smp_setup(void)
173 {
174 	cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
175 	cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
176 
177 	iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
178 	pr_info("Detected %i available CPU(s)\n", loongson_sysconf.nr_cpus);
179 }
180 
181 void __init loongson_prepare_cpus(unsigned int max_cpus)
182 {
183 	int i = 0;
184 
185 	for (i = 0; i < loongson_sysconf.nr_cpus; i++) {
186 		set_cpu_present(i, true);
187 		csr_mail_send(0, __cpu_logical_map[i], 0);
188 	}
189 
190 	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
191 }
192 
193 /*
194  * Setup the PC, SP, and TP of a secondary processor and start it running!
195  */
196 void loongson_boot_secondary(int cpu, struct task_struct *idle)
197 {
198 	unsigned long entry;
199 
200 	pr_info("Booting CPU#%d...\n", cpu);
201 
202 	entry = __pa_symbol((unsigned long)&smpboot_entry);
203 	cpuboot_data.stack = (unsigned long)__KSTK_TOS(idle);
204 	cpuboot_data.thread_info = (unsigned long)task_thread_info(idle);
205 
206 	csr_mail_send(entry, cpu_logical_map(cpu), 0);
207 
208 	loongson_send_ipi_single(cpu, SMP_BOOT_CPU);
209 }
210 
211 /*
212  * SMP init and finish on secondary CPUs
213  */
214 void loongson_init_secondary(void)
215 {
216 	unsigned int cpu = smp_processor_id();
217 	unsigned int imask = ECFGF_IP0 | ECFGF_IP1 | ECFGF_IP2 |
218 			     ECFGF_IPI | ECFGF_PMC | ECFGF_TIMER;
219 
220 	change_csr_ecfg(ECFG0_IM, imask);
221 
222 	iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
223 
224 #ifdef CONFIG_NUMA
225 	numa_add_cpu(cpu);
226 #endif
227 	per_cpu(cpu_state, cpu) = CPU_ONLINE;
228 	cpu_data[cpu].core =
229 		     cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
230 	cpu_data[cpu].package =
231 		     cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
232 }
233 
234 void loongson_smp_finish(void)
235 {
236 	local_irq_enable();
237 	iocsr_write64(0, LOONGARCH_IOCSR_MBUF0);
238 	pr_info("CPU#%d finished\n", smp_processor_id());
239 }
240 
241 #ifdef CONFIG_HOTPLUG_CPU
242 
243 int loongson_cpu_disable(void)
244 {
245 	unsigned long flags;
246 	unsigned int cpu = smp_processor_id();
247 
248 	if (io_master(cpu))
249 		return -EBUSY;
250 
251 #ifdef CONFIG_NUMA
252 	numa_remove_cpu(cpu);
253 #endif
254 	set_cpu_online(cpu, false);
255 	calculate_cpu_foreign_map();
256 	local_irq_save(flags);
257 	irq_migrate_all_off_this_cpu();
258 	clear_csr_ecfg(ECFG0_IM);
259 	local_irq_restore(flags);
260 	local_flush_tlb_all();
261 
262 	return 0;
263 }
264 
265 void loongson_cpu_die(unsigned int cpu)
266 {
267 	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
268 		cpu_relax();
269 
270 	mb();
271 }
272 
273 void play_dead(void)
274 {
275 	register uint64_t addr;
276 	register void (*init_fn)(void);
277 
278 	idle_task_exit();
279 	local_irq_enable();
280 	set_csr_ecfg(ECFGF_IPI);
281 	__this_cpu_write(cpu_state, CPU_DEAD);
282 
283 	__smp_mb();
284 	do {
285 		__asm__ __volatile__("idle 0\n\t");
286 		addr = iocsr_read64(LOONGARCH_IOCSR_MBUF0);
287 	} while (addr == 0);
288 
289 	init_fn = (void *)TO_CACHE(addr);
290 	iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_CLEAR);
291 
292 	init_fn();
293 	unreachable();
294 }
295 
296 #endif
297 
298 /*
299  * Power management
300  */
301 #ifdef CONFIG_PM
302 
303 static int loongson_ipi_suspend(void)
304 {
305 	return 0;
306 }
307 
308 static void loongson_ipi_resume(void)
309 {
310 	iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
311 }
312 
313 static struct syscore_ops loongson_ipi_syscore_ops = {
314 	.resume         = loongson_ipi_resume,
315 	.suspend        = loongson_ipi_suspend,
316 };
317 
318 /*
319  * Enable boot cpu ipi before enabling nonboot cpus
320  * during syscore_resume.
321  */
322 static int __init ipi_pm_init(void)
323 {
324 	register_syscore_ops(&loongson_ipi_syscore_ops);
325 	return 0;
326 }
327 
328 core_initcall(ipi_pm_init);
329 #endif
330 
331 static inline void set_cpu_sibling_map(int cpu)
332 {
333 	int i;
334 
335 	cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
336 
337 	if (smp_num_siblings <= 1)
338 		cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
339 	else {
340 		for_each_cpu(i, &cpu_sibling_setup_map) {
341 			if (cpus_are_siblings(cpu, i)) {
342 				cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
343 				cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
344 			}
345 		}
346 	}
347 }
348 
349 static inline void set_cpu_core_map(int cpu)
350 {
351 	int i;
352 
353 	cpumask_set_cpu(cpu, &cpu_core_setup_map);
354 
355 	for_each_cpu(i, &cpu_core_setup_map) {
356 		if (cpu_data[cpu].package == cpu_data[i].package) {
357 			cpumask_set_cpu(i, &cpu_core_map[cpu]);
358 			cpumask_set_cpu(cpu, &cpu_core_map[i]);
359 		}
360 	}
361 }
362 
363 /*
364  * Calculate a new cpu_foreign_map mask whenever a
365  * new cpu appears or disappears.
366  */
367 void calculate_cpu_foreign_map(void)
368 {
369 	int i, k, core_present;
370 	cpumask_t temp_foreign_map;
371 
372 	/* Re-calculate the mask */
373 	cpumask_clear(&temp_foreign_map);
374 	for_each_online_cpu(i) {
375 		core_present = 0;
376 		for_each_cpu(k, &temp_foreign_map)
377 			if (cpus_are_siblings(i, k))
378 				core_present = 1;
379 		if (!core_present)
380 			cpumask_set_cpu(i, &temp_foreign_map);
381 	}
382 
383 	for_each_online_cpu(i)
384 		cpumask_andnot(&cpu_foreign_map[i],
385 			       &temp_foreign_map, &cpu_sibling_map[i]);
386 }
387 
388 /* Preload SMP state for boot cpu */
389 void smp_prepare_boot_cpu(void)
390 {
391 	unsigned int cpu, node, rr_node;
392 
393 	set_cpu_possible(0, true);
394 	set_cpu_online(0, true);
395 	set_my_cpu_offset(per_cpu_offset(0));
396 
397 	rr_node = first_node(node_online_map);
398 	for_each_possible_cpu(cpu) {
399 		node = early_cpu_to_node(cpu);
400 
401 		/*
402 		 * The mapping between present cpus and nodes has been
403 		 * built during MADT and SRAT parsing.
404 		 *
405 		 * If possible cpus = present cpus here, early_cpu_to_node
406 		 * will return valid node.
407 		 *
408 		 * If possible cpus > present cpus here (e.g. some possible
409 		 * cpus will be added by cpu-hotplug later), for possible but
410 		 * not present cpus, early_cpu_to_node will return NUMA_NO_NODE,
411 		 * and we just map them to online nodes in round-robin way.
412 		 * Once hotplugged, new correct mapping will be built for them.
413 		 */
414 		if (node != NUMA_NO_NODE)
415 			set_cpu_numa_node(cpu, node);
416 		else {
417 			set_cpu_numa_node(cpu, rr_node);
418 			rr_node = next_node_in(rr_node, node_online_map);
419 		}
420 	}
421 }
422 
423 /* called from main before smp_init() */
424 void __init smp_prepare_cpus(unsigned int max_cpus)
425 {
426 	init_new_context(current, &init_mm);
427 	current_thread_info()->cpu = 0;
428 	loongson_prepare_cpus(max_cpus);
429 	set_cpu_sibling_map(0);
430 	set_cpu_core_map(0);
431 	calculate_cpu_foreign_map();
432 #ifndef CONFIG_HOTPLUG_CPU
433 	init_cpu_present(cpu_possible_mask);
434 #endif
435 }
436 
437 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
438 {
439 	loongson_boot_secondary(cpu, tidle);
440 
441 	/* Wait for CPU to start and be ready to sync counters */
442 	if (!wait_for_completion_timeout(&cpu_starting,
443 					 msecs_to_jiffies(5000))) {
444 		pr_crit("CPU%u: failed to start\n", cpu);
445 		return -EIO;
446 	}
447 
448 	/* Wait for CPU to finish startup & mark itself online before return */
449 	wait_for_completion(&cpu_running);
450 
451 	return 0;
452 }
453 
454 /*
455  * First C code run on the secondary CPUs after being started up by
456  * the master.
457  */
458 asmlinkage void start_secondary(void)
459 {
460 	unsigned int cpu;
461 
462 	sync_counter();
463 	cpu = smp_processor_id();
464 	set_my_cpu_offset(per_cpu_offset(cpu));
465 
466 	cpu_probe();
467 	constant_clockevent_init();
468 	loongson_init_secondary();
469 
470 	set_cpu_sibling_map(cpu);
471 	set_cpu_core_map(cpu);
472 
473 	notify_cpu_starting(cpu);
474 
475 	/* Notify boot CPU that we're starting */
476 	complete(&cpu_starting);
477 
478 	/* The CPU is running, now mark it online */
479 	set_cpu_online(cpu, true);
480 
481 	calculate_cpu_foreign_map();
482 
483 	/*
484 	 * Notify boot CPU that we're up & online and it can safely return
485 	 * from __cpu_up()
486 	 */
487 	complete(&cpu_running);
488 
489 	/*
490 	 * irq will be enabled in loongson_smp_finish(), enabling it too
491 	 * early is dangerous.
492 	 */
493 	WARN_ON_ONCE(!irqs_disabled());
494 	loongson_smp_finish();
495 
496 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
497 }
498 
499 void __init smp_cpus_done(unsigned int max_cpus)
500 {
501 }
502 
503 static void stop_this_cpu(void *dummy)
504 {
505 	set_cpu_online(smp_processor_id(), false);
506 	calculate_cpu_foreign_map();
507 	local_irq_disable();
508 	while (true);
509 }
510 
511 void smp_send_stop(void)
512 {
513 	smp_call_function(stop_this_cpu, NULL, 0);
514 }
515 
516 int setup_profiling_timer(unsigned int multiplier)
517 {
518 	return 0;
519 }
520 
521 static void flush_tlb_all_ipi(void *info)
522 {
523 	local_flush_tlb_all();
524 }
525 
526 void flush_tlb_all(void)
527 {
528 	on_each_cpu(flush_tlb_all_ipi, NULL, 1);
529 }
530 
531 static void flush_tlb_mm_ipi(void *mm)
532 {
533 	local_flush_tlb_mm((struct mm_struct *)mm);
534 }
535 
536 void flush_tlb_mm(struct mm_struct *mm)
537 {
538 	if (atomic_read(&mm->mm_users) == 0)
539 		return;		/* happens as a result of exit_mmap() */
540 
541 	preempt_disable();
542 
543 	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
544 		on_each_cpu_mask(mm_cpumask(mm), flush_tlb_mm_ipi, mm, 1);
545 	} else {
546 		unsigned int cpu;
547 
548 		for_each_online_cpu(cpu) {
549 			if (cpu != smp_processor_id() && cpu_context(cpu, mm))
550 				cpu_context(cpu, mm) = 0;
551 		}
552 		local_flush_tlb_mm(mm);
553 	}
554 
555 	preempt_enable();
556 }
557 
558 struct flush_tlb_data {
559 	struct vm_area_struct *vma;
560 	unsigned long addr1;
561 	unsigned long addr2;
562 };
563 
564 static void flush_tlb_range_ipi(void *info)
565 {
566 	struct flush_tlb_data *fd = info;
567 
568 	local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
569 }
570 
571 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
572 {
573 	struct mm_struct *mm = vma->vm_mm;
574 
575 	preempt_disable();
576 	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
577 		struct flush_tlb_data fd = {
578 			.vma = vma,
579 			.addr1 = start,
580 			.addr2 = end,
581 		};
582 
583 		on_each_cpu_mask(mm_cpumask(mm), flush_tlb_range_ipi, &fd, 1);
584 	} else {
585 		unsigned int cpu;
586 
587 		for_each_online_cpu(cpu) {
588 			if (cpu != smp_processor_id() && cpu_context(cpu, mm))
589 				cpu_context(cpu, mm) = 0;
590 		}
591 		local_flush_tlb_range(vma, start, end);
592 	}
593 	preempt_enable();
594 }
595 
596 static void flush_tlb_kernel_range_ipi(void *info)
597 {
598 	struct flush_tlb_data *fd = info;
599 
600 	local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
601 }
602 
603 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
604 {
605 	struct flush_tlb_data fd = {
606 		.addr1 = start,
607 		.addr2 = end,
608 	};
609 
610 	on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
611 }
612 
613 static void flush_tlb_page_ipi(void *info)
614 {
615 	struct flush_tlb_data *fd = info;
616 
617 	local_flush_tlb_page(fd->vma, fd->addr1);
618 }
619 
620 void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
621 {
622 	preempt_disable();
623 	if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
624 		struct flush_tlb_data fd = {
625 			.vma = vma,
626 			.addr1 = page,
627 		};
628 
629 		on_each_cpu_mask(mm_cpumask(vma->vm_mm), flush_tlb_page_ipi, &fd, 1);
630 	} else {
631 		unsigned int cpu;
632 
633 		for_each_online_cpu(cpu) {
634 			if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
635 				cpu_context(cpu, vma->vm_mm) = 0;
636 		}
637 		local_flush_tlb_page(vma, page);
638 	}
639 	preempt_enable();
640 }
641 EXPORT_SYMBOL(flush_tlb_page);
642 
643 static void flush_tlb_one_ipi(void *info)
644 {
645 	unsigned long vaddr = (unsigned long) info;
646 
647 	local_flush_tlb_one(vaddr);
648 }
649 
650 void flush_tlb_one(unsigned long vaddr)
651 {
652 	on_each_cpu(flush_tlb_one_ipi, (void *)vaddr, 1);
653 }
654 EXPORT_SYMBOL(flush_tlb_one);
655