1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Loongson Technology Corporation Limited 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@1 { 19 compatible = "loongson,la364"; 20 device_type = "cpu"; 21 reg = <0x0>; 22 clocks = <&cpu_clk>; 23 }; 24 25 cpu1: cpu@2 { 26 compatible = "loongson,la364"; 27 device_type = "cpu"; 28 reg = <0x1>; 29 clocks = <&cpu_clk>; 30 }; 31 }; 32 33 cpu_clk: cpu-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <1400000000>; 37 }; 38 39 cpuintc: interrupt-controller { 40 compatible = "loongson,cpu-interrupt-controller"; 41 #interrupt-cells = <1>; 42 interrupt-controller; 43 }; 44 45 bus@10000000 { 46 compatible = "simple-bus"; 47 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 48 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 49 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 50 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 54 isa@18400000 { 55 compatible = "isa"; 56 #size-cells = <1>; 57 #address-cells = <2>; 58 ranges = <1 0x0 0x0 0x18400000 0x4000>; 59 }; 60 61 pmc: power-management@100d0000 { 62 compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon"; 63 reg = <0x0 0x100d0000 0x0 0x58>; 64 interrupt-parent = <&eiointc>; 65 interrupts = <47>; 66 loongson,suspend-address = <0x0 0x1c000500>; 67 68 syscon-reboot { 69 compatible = "syscon-reboot"; 70 offset = <0x30>; 71 mask = <0x1>; 72 }; 73 74 syscon-poweroff { 75 compatible = "syscon-poweroff"; 76 regmap = <&pmc>; 77 offset = <0x14>; 78 mask = <0x3c00>; 79 value = <0x3c00>; 80 }; 81 }; 82 83 liointc: interrupt-controller@1fe01400 { 84 compatible = "loongson,liointc-1.0"; 85 reg = <0x0 0x1fe01400 0x0 0x64>; 86 87 interrupt-controller; 88 #interrupt-cells = <2>; 89 interrupt-parent = <&cpuintc>; 90 interrupts = <2>; 91 interrupt-names = "int0"; 92 loongson,parent_int_map = <0xffffffff>, /* int0 */ 93 <0x00000000>, /* int1 */ 94 <0x00000000>, /* int2 */ 95 <0x00000000>; /* int3 */ 96 }; 97 98 eiointc: interrupt-controller@1fe01600 { 99 compatible = "loongson,ls2k2000-eiointc"; 100 reg = <0x0 0x1fe01600 0x0 0xea00>; 101 interrupt-controller; 102 #interrupt-cells = <1>; 103 interrupt-parent = <&cpuintc>; 104 interrupts = <3>; 105 }; 106 107 pic: interrupt-controller@10000000 { 108 compatible = "loongson,pch-pic-1.0"; 109 reg = <0x0 0x10000000 0x0 0x400>; 110 interrupt-controller; 111 #interrupt-cells = <2>; 112 loongson,pic-base-vec = <0>; 113 interrupt-parent = <&eiointc>; 114 }; 115 116 msi: msi-controller@1fe01140 { 117 compatible = "loongson,pch-msi-1.0"; 118 reg = <0x0 0x1fe01140 0x0 0x8>; 119 interrupt-controller; 120 #interrupt-cells = <1>; 121 msi-controller; 122 loongson,msi-base-vec = <64>; 123 loongson,msi-num-vecs = <192>; 124 interrupt-parent = <&eiointc>; 125 }; 126 127 rtc0: rtc@100d0100 { 128 compatible = "loongson,ls2k2000-rtc", "loongson,ls7a-rtc"; 129 reg = <0x0 0x100d0100 0x0 0x100>; 130 interrupt-parent = <&pic>; 131 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; 132 status = "disabled"; 133 }; 134 135 uart0: serial@1fe001e0 { 136 compatible = "ns16550a"; 137 reg = <0x0 0x1fe001e0 0x0 0x10>; 138 clock-frequency = <100000000>; 139 interrupt-parent = <&liointc>; 140 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 141 no-loopback-test; 142 status = "disabled"; 143 }; 144 145 pcie@1a000000 { 146 compatible = "loongson,ls2k-pci"; 147 reg = <0x0 0x1a000000 0x0 0x02000000>, 148 <0xfe 0x0 0x0 0x20000000>; 149 #address-cells = <3>; 150 #size-cells = <2>; 151 device_type = "pci"; 152 msi-parent = <&msi>; 153 bus-range = <0x0 0xff>; 154 ranges = <0x01000000 0x0 0x00008000 0x0 0x18408000 0x0 0x00008000>, 155 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 156 157 gmac0: ethernet@3,0 { 158 reg = <0x1800 0x0 0x0 0x0 0x0>; 159 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-parent = <&pic>; 161 status = "disabled"; 162 }; 163 164 gmac1: ethernet@3,1 { 165 reg = <0x1900 0x0 0x0 0x0 0x0>; 166 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-parent = <&pic>; 168 status = "disabled"; 169 }; 170 171 gmac2: ethernet@3,2 { 172 reg = <0x1a00 0x0 0x0 0x0 0x0>; 173 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 174 interrupt-parent = <&pic>; 175 status = "disabled"; 176 }; 177 178 xhci0: usb@4,0 { 179 reg = <0x2000 0x0 0x0 0x0 0x0>; 180 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-parent = <&pic>; 182 status = "disabled"; 183 }; 184 185 xhci1: usb@19,0 { 186 reg = <0xc800 0x0 0x0 0x0 0x0>; 187 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-parent = <&pic>; 189 status = "disabled"; 190 }; 191 192 display@6,1 { 193 reg = <0x3100 0x0 0x0 0x0 0x0>; 194 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-parent = <&pic>; 196 status = "disabled"; 197 }; 198 199 hda@7,0 { 200 reg = <0x3800 0x0 0x0 0x0 0x0>; 201 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-parent = <&pic>; 203 status = "disabled"; 204 }; 205 206 sata: sata@8,0 { 207 reg = <0x4000 0x0 0x0 0x0 0x0>; 208 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-parent = <&pic>; 210 status = "disabled"; 211 }; 212 213 pcie@9,0 { 214 reg = <0x4800 0x0 0x0 0x0 0x0>; 215 #address-cells = <3>; 216 #size-cells = <2>; 217 device_type = "pci"; 218 interrupt-parent = <&pic>; 219 #interrupt-cells = <1>; 220 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 221 interrupt-map = <0x0 0x0 0x0 0x0 &pic 32 IRQ_TYPE_LEVEL_HIGH>; 222 ranges; 223 }; 224 225 pcie@a,0 { 226 reg = <0x5000 0x0 0x0 0x0 0x0>; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 device_type = "pci"; 230 interrupt-parent = <&pic>; 231 #interrupt-cells = <1>; 232 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 233 interrupt-map = <0x0 0x0 0x0 0x0 &pic 33 IRQ_TYPE_LEVEL_HIGH>; 234 ranges; 235 }; 236 237 pcie@b,0 { 238 reg = <0x5800 0x0 0x0 0x0 0x0>; 239 #address-cells = <3>; 240 #size-cells = <2>; 241 device_type = "pci"; 242 interrupt-parent = <&pic>; 243 #interrupt-cells = <1>; 244 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 245 interrupt-map = <0x0 0x0 0x0 0x0 &pic 34 IRQ_TYPE_LEVEL_HIGH>; 246 ranges; 247 }; 248 249 pcie@c,0 { 250 reg = <0x6000 0x0 0x0 0x0 0x0>; 251 #address-cells = <3>; 252 #size-cells = <2>; 253 device_type = "pci"; 254 interrupt-parent = <&pic>; 255 #interrupt-cells = <1>; 256 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 257 interrupt-map = <0x0 0x0 0x0 0x0 &pic 35 IRQ_TYPE_LEVEL_HIGH>; 258 ranges; 259 }; 260 261 pcie@d,0 { 262 reg = <0x6800 0x0 0x0 0x0 0x0>; 263 #address-cells = <3>; 264 #size-cells = <2>; 265 device_type = "pci"; 266 interrupt-parent = <&pic>; 267 #interrupt-cells = <1>; 268 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 269 interrupt-map = <0x0 0x0 0x0 0x0 &pic 36 IRQ_TYPE_LEVEL_HIGH>; 270 ranges; 271 }; 272 273 pcie@e,0 { 274 reg = <0x7000 0x0 0x0 0x0 0x0>; 275 #address-cells = <3>; 276 #size-cells = <2>; 277 device_type = "pci"; 278 interrupt-parent = <&pic>; 279 #interrupt-cells = <1>; 280 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 281 interrupt-map = <0x0 0x0 0x0 0x0 &pic 37 IRQ_TYPE_LEVEL_HIGH>; 282 ranges; 283 }; 284 285 pcie@f,0 { 286 reg = <0x7800 0x0 0x0 0x0 0x0>; 287 #address-cells = <3>; 288 #size-cells = <2>; 289 device_type = "pci"; 290 interrupt-parent = <&pic>; 291 #interrupt-cells = <1>; 292 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 293 interrupt-map = <0x0 0x0 0x0 0x0 &pic 40 IRQ_TYPE_LEVEL_HIGH>; 294 ranges; 295 }; 296 297 pcie@10,0 { 298 reg = <0x8000 0x0 0x0 0x0 0x0>; 299 #address-cells = <3>; 300 #size-cells = <2>; 301 device_type = "pci"; 302 interrupt-parent = <&pic>; 303 #interrupt-cells = <1>; 304 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 305 interrupt-map = <0x0 0x0 0x0 0x0 &pic 30 IRQ_TYPE_LEVEL_HIGH>; 306 ranges; 307 }; 308 }; 309 }; 310}; 311