1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Loongson Technology Corporation Limited 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/clock/loongson,ls2k-clk.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "loongson,la264"; 22 device_type = "cpu"; 23 reg= <0x0>; 24 clocks = <&clk LOONGSON2_NODE_CLK>; 25 }; 26 27 cpu1: cpu@1 { 28 compatible = "loongson,la264"; 29 device_type = "cpu"; 30 reg = <0x1>; 31 clocks = <&clk LOONGSON2_NODE_CLK>; 32 }; 33 }; 34 35 ref_100m: clock-ref-100m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <100000000>; 39 clock-output-names = "ref_100m"; 40 }; 41 42 cpuintc: interrupt-controller { 43 compatible = "loongson,cpu-interrupt-controller"; 44 #interrupt-cells = <1>; 45 interrupt-controller; 46 }; 47 48 /* i2c of the dvi eeprom edid */ 49 i2c-gpio-0 { 50 compatible = "i2c-gpio"; 51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 52 sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 53 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 54 #address-cells = <1>; 55 #size-cells = <0>; 56 status = "disabled"; 57 }; 58 59 /* i2c of the eeprom edid */ 60 i2c-gpio-1 { 61 compatible = "i2c-gpio"; 62 scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 63 sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 i2c-gpio,delay-us = <5>; /* ~100 kHz */ 65 #address-cells = <1>; 66 #size-cells = <0>; 67 status = "disabled"; 68 }; 69 70 thermal-zones { 71 cpu-thermal { 72 polling-delay-passive = <1000>; 73 polling-delay = <5000>; 74 thermal-sensors = <&tsensor 0>; 75 76 trips { 77 cpu_alert: cpu-alert { 78 temperature = <33000>; 79 hysteresis = <2000>; 80 type = "active"; 81 }; 82 83 cpu_crit: cpu-crit { 84 temperature = <85000>; 85 hysteresis = <5000>; 86 type = "critical"; 87 }; 88 }; 89 }; 90 }; 91 92 bus@10000000 { 93 compatible = "simple-bus"; 94 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>, 95 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>, 96 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>, 97 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>, 98 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>; 99 #address-cells = <2>; 100 #size-cells = <2>; 101 dma-coherent; 102 103 isa@18000000 { 104 compatible = "isa"; 105 #size-cells = <1>; 106 #address-cells = <2>; 107 ranges = <1 0x0 0x0 0x18000000 0x4000>; 108 }; 109 110 liointc0: interrupt-controller@1fe01400 { 111 compatible = "loongson,liointc-2.0"; 112 reg = <0x0 0x1fe01400 0x0 0x40>, 113 <0x0 0x1fe01040 0x0 0x8>, 114 <0x0 0x1fe01140 0x0 0x8>; 115 reg-names = "main", "isr0", "isr1"; 116 interrupt-controller; 117 #interrupt-cells = <2>; 118 interrupt-parent = <&cpuintc>; 119 interrupts = <2>; 120 interrupt-names = "int0"; 121 loongson,parent_int_map = <0xffffffff>, /* int0 */ 122 <0x00000000>, /* int1 */ 123 <0x00000000>, /* int2 */ 124 <0x00000000>; /* int3 */ 125 }; 126 127 liointc1: interrupt-controller@1fe01440 { 128 compatible = "loongson,liointc-2.0"; 129 reg = <0x0 0x1fe01440 0x0 0x40>, 130 <0x0 0x1fe01048 0x0 0x8>, 131 <0x0 0x1fe01148 0x0 0x8>; 132 reg-names = "main", "isr0", "isr1"; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 interrupt-parent = <&cpuintc>; 136 interrupts = <3>; 137 interrupt-names = "int1"; 138 loongson,parent_int_map = <0x00000000>, /* int0 */ 139 <0xffffffff>, /* int1 */ 140 <0x00000000>, /* int2 */ 141 <0x00000000>; /* int3 */ 142 }; 143 144 chipid@1fe00000 { 145 compatible = "loongson,ls2k-chipid"; 146 reg = <0x0 0x1fe00000 0x0 0x30>; 147 little-endian; 148 }; 149 150 pctrl: pinctrl@1fe00420 { 151 compatible = "loongson,ls2k-pinctrl"; 152 reg = <0x0 0x1fe00420 0x0 0x18>; 153 status = "disabled"; 154 }; 155 156 clk: clock-controller@1fe00480 { 157 compatible = "loongson,ls2k-clk"; 158 reg = <0x0 0x1fe00480 0x0 0x58>; 159 #clock-cells = <1>; 160 clocks = <&ref_100m>; 161 clock-names = "ref_100m"; 162 status = "disabled"; 163 }; 164 165 gpio0: gpio@1fe00500 { 166 compatible = "loongson,ls2k-gpio"; 167 reg = <0x0 0x1fe00500 0x0 0x38>; 168 ngpios = <64>; 169 #gpio-cells = <2>; 170 gpio-controller; 171 gpio-ranges = <&pctrl 0x0 0x0 15>, 172 <&pctrl 16 16 15>, 173 <&pctrl 32 32 10>, 174 <&pctrl 44 44 20>; 175 interrupt-parent = <&liointc1>; 176 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>, 177 <29 IRQ_TYPE_LEVEL_HIGH>, 178 <30 IRQ_TYPE_LEVEL_HIGH>, 179 <30 IRQ_TYPE_LEVEL_HIGH>, 180 <26 IRQ_TYPE_LEVEL_HIGH>, 181 <26 IRQ_TYPE_LEVEL_HIGH>, 182 <26 IRQ_TYPE_LEVEL_HIGH>, 183 <26 IRQ_TYPE_LEVEL_HIGH>, 184 <26 IRQ_TYPE_LEVEL_HIGH>, 185 <26 IRQ_TYPE_LEVEL_HIGH>, 186 <26 IRQ_TYPE_LEVEL_HIGH>, 187 <26 IRQ_TYPE_LEVEL_HIGH>, 188 <26 IRQ_TYPE_LEVEL_HIGH>, 189 <26 IRQ_TYPE_LEVEL_HIGH>, 190 <26 IRQ_TYPE_LEVEL_HIGH>, 191 <>, 192 <26 IRQ_TYPE_LEVEL_HIGH>, 193 <26 IRQ_TYPE_LEVEL_HIGH>, 194 <26 IRQ_TYPE_LEVEL_HIGH>, 195 <26 IRQ_TYPE_LEVEL_HIGH>, 196 <26 IRQ_TYPE_LEVEL_HIGH>, 197 <26 IRQ_TYPE_LEVEL_HIGH>, 198 <26 IRQ_TYPE_LEVEL_HIGH>, 199 <26 IRQ_TYPE_LEVEL_HIGH>, 200 <26 IRQ_TYPE_LEVEL_HIGH>, 201 <26 IRQ_TYPE_LEVEL_HIGH>, 202 <26 IRQ_TYPE_LEVEL_HIGH>, 203 <26 IRQ_TYPE_LEVEL_HIGH>, 204 <26 IRQ_TYPE_LEVEL_HIGH>, 205 <26 IRQ_TYPE_LEVEL_HIGH>, 206 <26 IRQ_TYPE_LEVEL_HIGH>, 207 <26 IRQ_TYPE_LEVEL_HIGH>, 208 <27 IRQ_TYPE_LEVEL_HIGH>, 209 <27 IRQ_TYPE_LEVEL_HIGH>, 210 <27 IRQ_TYPE_LEVEL_HIGH>, 211 <27 IRQ_TYPE_LEVEL_HIGH>, 212 <27 IRQ_TYPE_LEVEL_HIGH>, 213 <>, 214 <27 IRQ_TYPE_LEVEL_HIGH>, 215 <27 IRQ_TYPE_LEVEL_HIGH>, 216 <27 IRQ_TYPE_LEVEL_HIGH>, 217 <27 IRQ_TYPE_LEVEL_HIGH>, 218 <>, 219 <>, 220 <27 IRQ_TYPE_LEVEL_HIGH>, 221 <27 IRQ_TYPE_LEVEL_HIGH>, 222 <27 IRQ_TYPE_LEVEL_HIGH>, 223 <27 IRQ_TYPE_LEVEL_HIGH>, 224 <27 IRQ_TYPE_LEVEL_HIGH>, 225 <27 IRQ_TYPE_LEVEL_HIGH>, 226 <27 IRQ_TYPE_LEVEL_HIGH>, 227 <27 IRQ_TYPE_LEVEL_HIGH>, 228 <27 IRQ_TYPE_LEVEL_HIGH>, 229 <27 IRQ_TYPE_LEVEL_HIGH>, 230 <27 IRQ_TYPE_LEVEL_HIGH>, 231 <27 IRQ_TYPE_LEVEL_HIGH>, 232 <27 IRQ_TYPE_LEVEL_HIGH>, 233 <27 IRQ_TYPE_LEVEL_HIGH>, 234 <27 IRQ_TYPE_LEVEL_HIGH>, 235 <27 IRQ_TYPE_LEVEL_HIGH>, 236 <27 IRQ_TYPE_LEVEL_HIGH>, 237 <27 IRQ_TYPE_LEVEL_HIGH>, 238 <27 IRQ_TYPE_LEVEL_HIGH>, 239 <27 IRQ_TYPE_LEVEL_HIGH>; 240 }; 241 242 tsensor: thermal-sensor@1fe01500 { 243 compatible = "loongson,ls2k1000-thermal"; 244 reg = <0x0 0x1fe01500 0x0 0x30>; 245 interrupt-parent = <&liointc0>; 246 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 247 #thermal-sensor-cells = <1>; 248 }; 249 250 dma-controller@1fe00c00 { 251 compatible = "loongson,ls2k1000-apbdma"; 252 reg = <0x0 0x1fe00c00 0x0 0x8>; 253 interrupt-parent = <&liointc1>; 254 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&clk LOONGSON2_APB_CLK>; 256 #dma-cells = <1>; 257 status = "disabled"; 258 }; 259 260 dma-controller@1fe00c10 { 261 compatible = "loongson,ls2k1000-apbdma"; 262 reg = <0x0 0x1fe00c10 0x0 0x8>; 263 interrupt-parent = <&liointc1>; 264 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&clk LOONGSON2_APB_CLK>; 266 #dma-cells = <1>; 267 status = "disabled"; 268 }; 269 270 dma-controller@1fe00c20 { 271 compatible = "loongson,ls2k1000-apbdma"; 272 reg = <0x0 0x1fe00c20 0x0 0x8>; 273 interrupt-parent = <&liointc1>; 274 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clk LOONGSON2_APB_CLK>; 276 #dma-cells = <1>; 277 status = "disabled"; 278 }; 279 280 dma-controller@1fe00c30 { 281 compatible = "loongson,ls2k1000-apbdma"; 282 reg = <0x0 0x1fe00c30 0x0 0x8>; 283 interrupt-parent = <&liointc1>; 284 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&clk LOONGSON2_APB_CLK>; 286 #dma-cells = <1>; 287 status = "disabled"; 288 }; 289 290 dma-controller@1fe00c40 { 291 compatible = "loongson,ls2k1000-apbdma"; 292 reg = <0x0 0x1fe00c40 0x0 0x8>; 293 interrupt-parent = <&liointc1>; 294 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk LOONGSON2_APB_CLK>; 296 #dma-cells = <1>; 297 status = "disabled"; 298 }; 299 300 uart0: serial@1fe20000 { 301 compatible = "ns16550a"; 302 reg = <0x0 0x1fe20000 0x0 0x10>; 303 clock-frequency = <125000000>; 304 interrupt-parent = <&liointc0>; 305 interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>; 306 no-loopback-test; 307 status = "disabled"; 308 }; 309 310 i2c2: i2c@1fe21000 { 311 compatible = "loongson,ls2k-i2c"; 312 reg = <0x0 0x1fe21000 0x0 0x8>; 313 interrupt-parent = <&liointc0>; 314 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 315 status = "disabled"; 316 }; 317 318 i2c3: i2c@1fe21800 { 319 compatible = "loongson,ls2k-i2c"; 320 reg = <0x0 0x1fe21800 0x0 0x8>; 321 interrupt-parent = <&liointc0>; 322 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 323 status = "disabled"; 324 }; 325 326 pmc: power-management@1fe27000 { 327 compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon"; 328 reg = <0x0 0x1fe27000 0x0 0x58>; 329 interrupt-parent = <&liointc1>; 330 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 331 loongson,suspend-address = <0x0 0x1c000500>; 332 333 syscon-reboot { 334 compatible = "syscon-reboot"; 335 offset = <0x30>; 336 mask = <0x1>; 337 }; 338 339 syscon-poweroff { 340 compatible = "syscon-poweroff"; 341 regmap = <&pmc>; 342 offset = <0x14>; 343 mask = <0x3c00>; 344 value = <0x3c00>; 345 }; 346 }; 347 348 rtc0: rtc@1fe27800 { 349 compatible = "loongson,ls2k1000-rtc"; 350 reg = <0x0 0x1fe27800 0x0 0x100>; 351 interrupt-parent = <&liointc1>; 352 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 353 status = "disabled"; 354 }; 355 356 spi0: spi@1fff0220 { 357 compatible = "loongson,ls2k1000-spi"; 358 reg = <0x0 0x1fff0220 0x0 0x10>; 359 clocks = <&clk LOONGSON2_BOOT_CLK>; 360 status = "disabled"; 361 }; 362 363 pcie@1a000000 { 364 compatible = "loongson,ls2k-pci"; 365 reg = <0x0 0x1a000000 0x0 0x02000000>, 366 <0xfe 0x0 0x0 0x20000000>; 367 #address-cells = <3>; 368 #size-cells = <2>; 369 device_type = "pci"; 370 bus-range = <0x0 0xff>; 371 ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>, 372 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; 373 374 gmac0: ethernet@3,0 { 375 reg = <0x1800 0x0 0x0 0x0 0x0>; 376 interrupt-parent = <&liointc0>; 377 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 378 <13 IRQ_TYPE_LEVEL_HIGH>; 379 interrupt-names = "macirq", "eth_lpi"; 380 status = "disabled"; 381 }; 382 383 gmac1: ethernet@3,1 { 384 reg = <0x1900 0x0 0x0 0x0 0x0>; 385 interrupt-parent = <&liointc0>; 386 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 387 <15 IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-names = "macirq", "eth_lpi"; 389 status = "disabled"; 390 }; 391 392 ehci0: usb@4,1 { 393 reg = <0x2100 0x0 0x0 0x0 0x0>; 394 interrupt-parent = <&liointc1>; 395 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 }; 398 399 ohci0: usb@4,2 { 400 reg = <0x2200 0x0 0x0 0x0 0x0>; 401 interrupt-parent = <&liointc1>; 402 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 403 status = "disabled"; 404 }; 405 406 display@6,0 { 407 reg = <0x3000 0x0 0x0 0x0 0x0>; 408 interrupt-parent = <&liointc0>; 409 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 410 status = "disabled"; 411 }; 412 413 hda@7,0 { 414 reg = <0x3800 0x0 0x0 0x0 0x0>; 415 interrupt-parent = <&liointc0>; 416 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 417 status = "disabled"; 418 }; 419 420 sata: sata@8,0 { 421 reg = <0x4000 0x0 0x0 0x0 0x0>; 422 interrupt-parent = <&liointc0>; 423 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 424 status = "disabled"; 425 }; 426 427 pcie@9,0 { 428 reg = <0x4800 0x0 0x0 0x0 0x0>; 429 #address-cells = <3>; 430 #size-cells = <2>; 431 device_type = "pci"; 432 #interrupt-cells = <1>; 433 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 434 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>; 435 ranges; 436 }; 437 438 pcie@a,0 { 439 reg = <0x5000 0x0 0x0 0x0 0x0>; 440 #address-cells = <3>; 441 #size-cells = <2>; 442 device_type = "pci"; 443 interrupt-parent = <&liointc1>; 444 #interrupt-cells = <1>; 445 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 446 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>; 447 ranges; 448 }; 449 450 pcie@b,0 { 451 reg = <0x5800 0x0 0x0 0x0 0x0>; 452 #address-cells = <3>; 453 #size-cells = <2>; 454 device_type = "pci"; 455 interrupt-parent = <&liointc1>; 456 #interrupt-cells = <1>; 457 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 458 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>; 459 ranges; 460 }; 461 462 pcie@c,0 { 463 reg = <0x6000 0x0 0x0 0x0 0x0>; 464 #address-cells = <3>; 465 #size-cells = <2>; 466 device_type = "pci"; 467 interrupt-parent = <&liointc1>; 468 #interrupt-cells = <1>; 469 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 470 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>; 471 ranges; 472 }; 473 474 pcie@d,0 { 475 reg = <0x6800 0x0 0x0 0x0 0x0>; 476 #address-cells = <3>; 477 #size-cells = <2>; 478 device_type = "pci"; 479 interrupt-parent = <&liointc1>; 480 #interrupt-cells = <1>; 481 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 482 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>; 483 ranges; 484 }; 485 486 pcie@e,0 { 487 reg = <0x7000 0x0 0x0 0x0 0x0>; 488 #address-cells = <3>; 489 #size-cells = <2>; 490 device_type = "pci"; 491 interrupt-parent = <&liointc1>; 492 #interrupt-cells = <1>; 493 interrupt-map-mask = <0x0 0x0 0x0 0x0>; 494 interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>; 495 ranges; 496 }; 497 }; 498 }; 499}; 500