1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_H 17 #define __ASM_PGTABLE_H 18 19 #include <asm/bug.h> 20 #include <asm/proc-fns.h> 21 22 #include <asm/memory.h> 23 #include <asm/pgtable-hwdef.h> 24 25 /* 26 * Software defined PTE bits definition. 27 */ 28 #define PTE_VALID (_AT(pteval_t, 1) << 0) 29 #define PTE_WRITE (PTE_DBM) /* same as DBM (51) */ 30 #define PTE_DIRTY (_AT(pteval_t, 1) << 55) 31 #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 32 #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ 33 34 /* 35 * VMALLOC and SPARSEMEM_VMEMMAP ranges. 36 * 37 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array 38 * (rounded up to PUD_SIZE). 39 * VMALLOC_START: beginning of the kernel VA space 40 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, 41 * fixed mappings and modules 42 */ 43 #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) 44 45 #ifndef CONFIG_KASAN 46 #define VMALLOC_START (VA_START) 47 #else 48 #include <asm/kasan.h> 49 #define VMALLOC_START (KASAN_SHADOW_END + SZ_64K) 50 #endif 51 52 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 53 54 #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) 55 56 #define FIRST_USER_ADDRESS 0UL 57 58 #ifndef __ASSEMBLY__ 59 60 #include <linux/mmdebug.h> 61 62 extern void __pte_error(const char *file, int line, unsigned long val); 63 extern void __pmd_error(const char *file, int line, unsigned long val); 64 extern void __pud_error(const char *file, int line, unsigned long val); 65 extern void __pgd_error(const char *file, int line, unsigned long val); 66 67 #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) 68 #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) 69 70 #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) 71 #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) 72 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) 73 #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT)) 74 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) 75 76 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) 77 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 78 #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) 79 80 #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) 81 82 #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) 83 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) 84 #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) 85 86 #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) 87 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) 88 89 #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) 90 #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) 91 92 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) 93 #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) 94 #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) 95 #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 96 #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 97 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) 98 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) 99 100 #define __P000 PAGE_NONE 101 #define __P001 PAGE_READONLY 102 #define __P010 PAGE_COPY 103 #define __P011 PAGE_COPY 104 #define __P100 PAGE_READONLY_EXEC 105 #define __P101 PAGE_READONLY_EXEC 106 #define __P110 PAGE_COPY_EXEC 107 #define __P111 PAGE_COPY_EXEC 108 109 #define __S000 PAGE_NONE 110 #define __S001 PAGE_READONLY 111 #define __S010 PAGE_SHARED 112 #define __S011 PAGE_SHARED 113 #define __S100 PAGE_READONLY_EXEC 114 #define __S101 PAGE_READONLY_EXEC 115 #define __S110 PAGE_SHARED_EXEC 116 #define __S111 PAGE_SHARED_EXEC 117 118 /* 119 * ZERO_PAGE is a global shared page that is always zero: used 120 * for zero-mapped memory areas etc.. 121 */ 122 extern struct page *empty_zero_page; 123 #define ZERO_PAGE(vaddr) (empty_zero_page) 124 125 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 126 127 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 128 129 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 130 131 #define pte_none(pte) (!pte_val(pte)) 132 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 133 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 134 135 /* Find an entry in the third-level page table. */ 136 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 137 138 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) 139 140 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 141 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 142 #define pte_unmap(pte) do { } while (0) 143 #define pte_unmap_nested(pte) do { } while (0) 144 145 /* 146 * The following only work if pte_present(). Undefined behaviour otherwise. 147 */ 148 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 149 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 150 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 151 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 152 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 153 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 154 155 #ifdef CONFIG_ARM64_HW_AFDBM 156 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 157 #else 158 #define pte_hw_dirty(pte) (0) 159 #endif 160 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 161 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 162 163 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 164 #define pte_valid_user(pte) \ 165 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 166 #define pte_valid_not_user(pte) \ 167 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 168 169 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 170 { 171 pte_val(pte) &= ~pgprot_val(prot); 172 return pte; 173 } 174 175 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 176 { 177 pte_val(pte) |= pgprot_val(prot); 178 return pte; 179 } 180 181 static inline pte_t pte_wrprotect(pte_t pte) 182 { 183 return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 184 } 185 186 static inline pte_t pte_mkwrite(pte_t pte) 187 { 188 return set_pte_bit(pte, __pgprot(PTE_WRITE)); 189 } 190 191 static inline pte_t pte_mkclean(pte_t pte) 192 { 193 return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 194 } 195 196 static inline pte_t pte_mkdirty(pte_t pte) 197 { 198 return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 199 } 200 201 static inline pte_t pte_mkold(pte_t pte) 202 { 203 return clear_pte_bit(pte, __pgprot(PTE_AF)); 204 } 205 206 static inline pte_t pte_mkyoung(pte_t pte) 207 { 208 return set_pte_bit(pte, __pgprot(PTE_AF)); 209 } 210 211 static inline pte_t pte_mkspecial(pte_t pte) 212 { 213 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 214 } 215 216 static inline pte_t pte_mkcont(pte_t pte) 217 { 218 return set_pte_bit(pte, __pgprot(PTE_CONT)); 219 } 220 221 static inline pte_t pte_mknoncont(pte_t pte) 222 { 223 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 224 } 225 226 static inline void set_pte(pte_t *ptep, pte_t pte) 227 { 228 *ptep = pte; 229 230 /* 231 * Only if the new pte is valid and kernel, otherwise TLB maintenance 232 * or update_mmu_cache() have the necessary barriers. 233 */ 234 if (pte_valid_not_user(pte)) { 235 dsb(ishst); 236 isb(); 237 } 238 } 239 240 struct mm_struct; 241 struct vm_area_struct; 242 243 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 244 245 /* 246 * PTE bits configuration in the presence of hardware Dirty Bit Management 247 * (PTE_WRITE == PTE_DBM): 248 * 249 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 250 * 0 0 | 1 0 0 251 * 0 1 | 1 1 0 252 * 1 0 | 1 0 1 253 * 1 1 | 0 1 x 254 * 255 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 256 * the page fault mechanism. Checking the dirty status of a pte becomes: 257 * 258 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 259 */ 260 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 261 pte_t *ptep, pte_t pte) 262 { 263 if (pte_valid_user(pte)) { 264 if (!pte_special(pte) && pte_exec(pte)) 265 __sync_icache_dcache(pte, addr); 266 if (pte_sw_dirty(pte) && pte_write(pte)) 267 pte_val(pte) &= ~PTE_RDONLY; 268 else 269 pte_val(pte) |= PTE_RDONLY; 270 } 271 272 /* 273 * If the existing pte is valid, check for potential race with 274 * hardware updates of the pte (ptep_set_access_flags safely changes 275 * valid ptes without going through an invalid entry). 276 */ 277 if (IS_ENABLED(CONFIG_DEBUG_VM) && IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 278 pte_valid(*ptep)) { 279 BUG_ON(!pte_young(pte)); 280 BUG_ON(pte_write(*ptep) && !pte_dirty(pte)); 281 } 282 283 set_pte(ptep, pte); 284 } 285 286 /* 287 * Huge pte definitions. 288 */ 289 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 290 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 291 292 /* 293 * Hugetlb definitions. 294 */ 295 #define HUGE_MAX_HSTATE 2 296 #define HPAGE_SHIFT PMD_SHIFT 297 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 298 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 299 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 300 301 #define __HAVE_ARCH_PTE_SPECIAL 302 303 static inline pte_t pud_pte(pud_t pud) 304 { 305 return __pte(pud_val(pud)); 306 } 307 308 static inline pmd_t pud_pmd(pud_t pud) 309 { 310 return __pmd(pud_val(pud)); 311 } 312 313 static inline pte_t pmd_pte(pmd_t pmd) 314 { 315 return __pte(pmd_val(pmd)); 316 } 317 318 static inline pmd_t pte_pmd(pte_t pte) 319 { 320 return __pmd(pte_val(pte)); 321 } 322 323 static inline pgprot_t mk_sect_prot(pgprot_t prot) 324 { 325 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 326 } 327 328 /* 329 * THP definitions. 330 */ 331 332 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 333 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 334 #define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd)) 335 #ifdef CONFIG_HAVE_RCU_TABLE_FREE 336 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 337 struct vm_area_struct; 338 void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address, 339 pmd_t *pmdp); 340 #endif /* CONFIG_HAVE_RCU_TABLE_FREE */ 341 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 342 343 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 344 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 345 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 346 #define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd))) 347 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 348 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 349 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 350 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 351 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) 352 353 #define __HAVE_ARCH_PMD_WRITE 354 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 355 356 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 357 358 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 359 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 360 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 361 362 #define pud_write(pud) pte_write(pud_pte(pud)) 363 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 364 365 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 366 367 static inline int has_transparent_hugepage(void) 368 { 369 return 1; 370 } 371 372 #define __pgprot_modify(prot,mask,bits) \ 373 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 374 375 /* 376 * Mark the prot value as uncacheable and unbufferable. 377 */ 378 #define pgprot_noncached(prot) \ 379 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 380 #define pgprot_writecombine(prot) \ 381 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 382 #define pgprot_device(prot) \ 383 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 384 #define __HAVE_PHYS_MEM_ACCESS_PROT 385 struct file; 386 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 387 unsigned long size, pgprot_t vma_prot); 388 389 #define pmd_none(pmd) (!pmd_val(pmd)) 390 #define pmd_present(pmd) (pmd_val(pmd)) 391 392 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 393 394 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 395 PMD_TYPE_TABLE) 396 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 397 PMD_TYPE_SECT) 398 399 #ifdef CONFIG_ARM64_64K_PAGES 400 #define pud_sect(pud) (0) 401 #define pud_table(pud) (1) 402 #else 403 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 404 PUD_TYPE_SECT) 405 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 406 PUD_TYPE_TABLE) 407 #endif 408 409 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 410 { 411 *pmdp = pmd; 412 dsb(ishst); 413 isb(); 414 } 415 416 static inline void pmd_clear(pmd_t *pmdp) 417 { 418 set_pmd(pmdp, __pmd(0)); 419 } 420 421 static inline pte_t *pmd_page_vaddr(pmd_t pmd) 422 { 423 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); 424 } 425 426 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 427 428 /* 429 * Conversion functions: convert a page and protection to a page entry, 430 * and a page entry and page directory to the page they refer to. 431 */ 432 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 433 434 #if CONFIG_PGTABLE_LEVELS > 2 435 436 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 437 438 #define pud_none(pud) (!pud_val(pud)) 439 #define pud_bad(pud) (!(pud_val(pud) & 2)) 440 #define pud_present(pud) (pud_val(pud)) 441 442 static inline void set_pud(pud_t *pudp, pud_t pud) 443 { 444 *pudp = pud; 445 dsb(ishst); 446 isb(); 447 } 448 449 static inline void pud_clear(pud_t *pudp) 450 { 451 set_pud(pudp, __pud(0)); 452 } 453 454 static inline pmd_t *pud_page_vaddr(pud_t pud) 455 { 456 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 457 } 458 459 /* Find an entry in the second-level page table. */ 460 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 461 462 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 463 { 464 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); 465 } 466 467 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 468 469 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 470 471 #if CONFIG_PGTABLE_LEVELS > 3 472 473 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 474 475 #define pgd_none(pgd) (!pgd_val(pgd)) 476 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 477 #define pgd_present(pgd) (pgd_val(pgd)) 478 479 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 480 { 481 *pgdp = pgd; 482 dsb(ishst); 483 } 484 485 static inline void pgd_clear(pgd_t *pgdp) 486 { 487 set_pgd(pgdp, __pgd(0)); 488 } 489 490 static inline pud_t *pgd_page_vaddr(pgd_t pgd) 491 { 492 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); 493 } 494 495 /* Find an entry in the frst-level page table. */ 496 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 497 498 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) 499 { 500 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); 501 } 502 503 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 504 505 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 506 507 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 508 509 /* to find an entry in a page-table-directory */ 510 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 511 512 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 513 514 /* to find an entry in a kernel page-table-directory */ 515 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 516 517 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 518 { 519 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 520 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 521 /* preserve the hardware dirty information */ 522 if (pte_hw_dirty(pte)) 523 pte = pte_mkdirty(pte); 524 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 525 return pte; 526 } 527 528 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 529 { 530 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 531 } 532 533 #ifdef CONFIG_ARM64_HW_AFDBM 534 /* 535 * Atomic pte/pmd modifications. 536 */ 537 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 538 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 539 unsigned long address, 540 pte_t *ptep) 541 { 542 pteval_t pteval; 543 unsigned int tmp, res; 544 545 asm volatile("// ptep_test_and_clear_young\n" 546 " prfm pstl1strm, %2\n" 547 "1: ldxr %0, %2\n" 548 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 549 " and %0, %0, %4 // clear PTE_AF\n" 550 " stxr %w1, %0, %2\n" 551 " cbnz %w1, 1b\n" 552 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 553 : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 554 555 return res; 556 } 557 558 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 559 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 560 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 561 unsigned long address, 562 pmd_t *pmdp) 563 { 564 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 565 } 566 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 567 568 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 569 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 570 unsigned long address, pte_t *ptep) 571 { 572 pteval_t old_pteval; 573 unsigned int tmp; 574 575 asm volatile("// ptep_get_and_clear\n" 576 " prfm pstl1strm, %2\n" 577 "1: ldxr %0, %2\n" 578 " stxr %w1, xzr, %2\n" 579 " cbnz %w1, 1b\n" 580 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 581 582 return __pte(old_pteval); 583 } 584 585 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 586 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR 587 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm, 588 unsigned long address, pmd_t *pmdp) 589 { 590 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 591 } 592 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 593 594 /* 595 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 596 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 597 */ 598 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 599 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 600 { 601 pteval_t pteval; 602 unsigned long tmp; 603 604 asm volatile("// ptep_set_wrprotect\n" 605 " prfm pstl1strm, %2\n" 606 "1: ldxr %0, %2\n" 607 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 608 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 609 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 610 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 611 " stxr %w1, %0, %2\n" 612 " cbnz %w1, 1b\n" 613 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 614 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 615 : "cc"); 616 } 617 618 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 619 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 620 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 621 unsigned long address, pmd_t *pmdp) 622 { 623 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 624 } 625 #endif 626 #endif /* CONFIG_ARM64_HW_AFDBM */ 627 628 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 629 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 630 631 /* 632 * Encode and decode a swap entry: 633 * bits 0-1: present (must be zero) 634 * bits 2-7: swap type 635 * bits 8-57: swap offset 636 */ 637 #define __SWP_TYPE_SHIFT 2 638 #define __SWP_TYPE_BITS 6 639 #define __SWP_OFFSET_BITS 50 640 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 641 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 642 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 643 644 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 645 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 646 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 647 648 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 649 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 650 651 /* 652 * Ensure that there are not more swap files than can be encoded in the kernel 653 * PTEs. 654 */ 655 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 656 657 extern int kern_addr_valid(unsigned long addr); 658 659 #include <asm-generic/pgtable.h> 660 661 #define pgtable_cache_init() do { } while (0) 662 663 /* 664 * On AArch64, the cache coherency is handled via the set_pte_at() function. 665 */ 666 static inline void update_mmu_cache(struct vm_area_struct *vma, 667 unsigned long addr, pte_t *ptep) 668 { 669 /* 670 * We don't do anything here, so there's a very small chance of 671 * us retaking a user fault which we just fixed up. The alternative 672 * is doing a dsb(ishst), but that penalises the fastpath. 673 */ 674 } 675 676 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 677 678 #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 679 #define kc_offset_to_vaddr(o) ((o) | VA_START) 680 681 #endif /* !__ASSEMBLY__ */ 682 683 #endif /* __ASM_PGTABLE_H */ 684