1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 /* 53 * Outside of a few very special situations (e.g. hibernation), we always 54 * use broadcast TLB invalidation instructions, therefore a spurious page 55 * fault on one CPU which has been handled concurrently by another CPU 56 * does not need to perform additional invalidation. 57 */ 58 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 59 60 /* 61 * ZERO_PAGE is a global shared page that is always zero: used 62 * for zero-mapped memory areas etc.. 63 */ 64 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 65 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 69 70 /* 71 * Macros to convert between a physical address and its placement in a 72 * page table entry, taking care of 52-bit addresses. 73 */ 74 #ifdef CONFIG_ARM64_PA_BITS_52 75 static inline phys_addr_t __pte_to_phys(pte_t pte) 76 { 77 pte_val(pte) &= ~PTE_MAYBE_SHARED; 78 return (pte_val(pte) & PTE_ADDR_LOW) | 79 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 80 } 81 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 82 { 83 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 84 } 85 #else 86 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 87 #define __phys_to_pte_val(phys) (phys) 88 #endif 89 90 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 91 #define pfn_pte(pfn,prot) \ 92 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 93 94 #define pte_none(pte) (!pte_val(pte)) 95 #define __pte_clear(mm, addr, ptep) \ 96 __set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 107 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 109 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 110 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 111 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 112 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 113 114 #define pte_cont_addr_end(addr, end) \ 115 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117 }) 118 119 #define pmd_cont_addr_end(addr, end) \ 120 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122 }) 123 124 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 125 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 126 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 127 128 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 129 #define pte_present_invalid(pte) \ 130 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 131 /* 132 * Execute-only user mappings do not have the PTE_USER bit set. All valid 133 * kernel mappings have the PTE_UXN bit set. 134 */ 135 #define pte_valid_not_user(pte) \ 136 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 137 /* 138 * Returns true if the pte is valid and has the contiguous bit set. 139 */ 140 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 141 /* 142 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 143 * so that we don't erroneously return false for pages that have been 144 * remapped as PROT_NONE but are yet to be flushed from the TLB. 145 * Note that we can't make any assumptions based on the state of the access 146 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 147 * TLB. 148 */ 149 #define pte_accessible(mm, pte) \ 150 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 151 152 /* 153 * p??_access_permitted() is true for valid user mappings (PTE_USER 154 * bit set, subject to the write permission check). For execute-only 155 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 156 * not set) must return false. PROT_NONE mappings do not have the 157 * PTE_VALID bit set. 158 */ 159 #define pte_access_permitted(pte, write) \ 160 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 161 #define pmd_access_permitted(pmd, write) \ 162 (pte_access_permitted(pmd_pte(pmd), (write))) 163 #define pud_access_permitted(pud, write) \ 164 (pte_access_permitted(pud_pte(pud), (write))) 165 166 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 167 { 168 pte_val(pte) &= ~pgprot_val(prot); 169 return pte; 170 } 171 172 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 173 { 174 pte_val(pte) |= pgprot_val(prot); 175 return pte; 176 } 177 178 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 179 { 180 pmd_val(pmd) &= ~pgprot_val(prot); 181 return pmd; 182 } 183 184 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 185 { 186 pmd_val(pmd) |= pgprot_val(prot); 187 return pmd; 188 } 189 190 static inline pte_t pte_mkwrite_novma(pte_t pte) 191 { 192 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 193 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 194 return pte; 195 } 196 197 static inline pte_t pte_mkclean(pte_t pte) 198 { 199 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 200 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 201 202 return pte; 203 } 204 205 static inline pte_t pte_mkdirty(pte_t pte) 206 { 207 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 208 209 if (pte_write(pte)) 210 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 211 212 return pte; 213 } 214 215 static inline pte_t pte_wrprotect(pte_t pte) 216 { 217 /* 218 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 219 * clear), set the PTE_DIRTY bit. 220 */ 221 if (pte_hw_dirty(pte)) 222 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 223 224 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 225 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 226 return pte; 227 } 228 229 static inline pte_t pte_mkold(pte_t pte) 230 { 231 return clear_pte_bit(pte, __pgprot(PTE_AF)); 232 } 233 234 static inline pte_t pte_mkyoung(pte_t pte) 235 { 236 return set_pte_bit(pte, __pgprot(PTE_AF)); 237 } 238 239 static inline pte_t pte_mkspecial(pte_t pte) 240 { 241 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 242 } 243 244 static inline pte_t pte_mkcont(pte_t pte) 245 { 246 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 247 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 248 } 249 250 static inline pte_t pte_mknoncont(pte_t pte) 251 { 252 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 253 } 254 255 static inline pte_t pte_mkpresent(pte_t pte) 256 { 257 return set_pte_bit(pte, __pgprot(PTE_VALID)); 258 } 259 260 static inline pte_t pte_mkinvalid(pte_t pte) 261 { 262 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 263 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 264 return pte; 265 } 266 267 static inline pmd_t pmd_mkcont(pmd_t pmd) 268 { 269 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 270 } 271 272 static inline pte_t pte_mkdevmap(pte_t pte) 273 { 274 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 275 } 276 277 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 278 static inline int pte_uffd_wp(pte_t pte) 279 { 280 return !!(pte_val(pte) & PTE_UFFD_WP); 281 } 282 283 static inline pte_t pte_mkuffd_wp(pte_t pte) 284 { 285 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 286 } 287 288 static inline pte_t pte_clear_uffd_wp(pte_t pte) 289 { 290 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 291 } 292 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 293 294 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 295 { 296 WRITE_ONCE(*ptep, pte); 297 } 298 299 static inline void __set_pte(pte_t *ptep, pte_t pte) 300 { 301 __set_pte_nosync(ptep, pte); 302 303 /* 304 * Only if the new pte is valid and kernel, otherwise TLB maintenance 305 * or update_mmu_cache() have the necessary barriers. 306 */ 307 if (pte_valid_not_user(pte)) { 308 dsb(ishst); 309 isb(); 310 } 311 } 312 313 static inline pte_t __ptep_get(pte_t *ptep) 314 { 315 return READ_ONCE(*ptep); 316 } 317 318 extern void __sync_icache_dcache(pte_t pteval); 319 bool pgattr_change_is_safe(u64 old, u64 new); 320 321 /* 322 * PTE bits configuration in the presence of hardware Dirty Bit Management 323 * (PTE_WRITE == PTE_DBM): 324 * 325 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 326 * 0 0 | 1 0 0 327 * 0 1 | 1 1 0 328 * 1 0 | 1 0 1 329 * 1 1 | 0 1 x 330 * 331 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 332 * the page fault mechanism. Checking the dirty status of a pte becomes: 333 * 334 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 335 */ 336 337 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 338 pte_t pte) 339 { 340 pte_t old_pte; 341 342 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 343 return; 344 345 old_pte = __ptep_get(ptep); 346 347 if (!pte_valid(old_pte) || !pte_valid(pte)) 348 return; 349 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 350 return; 351 352 /* 353 * Check for potential race with hardware updates of the pte 354 * (__ptep_set_access_flags safely changes valid ptes without going 355 * through an invalid entry). 356 */ 357 VM_WARN_ONCE(!pte_young(pte), 358 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 359 __func__, pte_val(old_pte), pte_val(pte)); 360 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 361 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 362 __func__, pte_val(old_pte), pte_val(pte)); 363 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 364 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 365 __func__, pte_val(old_pte), pte_val(pte)); 366 } 367 368 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 369 { 370 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 371 __sync_icache_dcache(pte); 372 373 /* 374 * If the PTE would provide user space access to the tags associated 375 * with it then ensure that the MTE tags are synchronised. Although 376 * pte_access_permitted() returns false for exec only mappings, they 377 * don't expose tags (instruction fetches don't check tags). 378 */ 379 if (system_supports_mte() && pte_access_permitted(pte, false) && 380 !pte_special(pte) && pte_tagged(pte)) 381 mte_sync_tags(pte, nr_pages); 382 } 383 384 /* 385 * Select all bits except the pfn 386 */ 387 static inline pgprot_t pte_pgprot(pte_t pte) 388 { 389 unsigned long pfn = pte_pfn(pte); 390 391 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 392 } 393 394 #define pte_advance_pfn pte_advance_pfn 395 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 396 { 397 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 398 } 399 400 static inline void __set_ptes(struct mm_struct *mm, 401 unsigned long __always_unused addr, 402 pte_t *ptep, pte_t pte, unsigned int nr) 403 { 404 page_table_check_ptes_set(mm, ptep, pte, nr); 405 __sync_cache_and_tags(pte, nr); 406 407 for (;;) { 408 __check_safe_pte_update(mm, ptep, pte); 409 __set_pte(ptep, pte); 410 if (--nr == 0) 411 break; 412 ptep++; 413 pte = pte_advance_pfn(pte, 1); 414 } 415 } 416 417 /* 418 * Huge pte definitions. 419 */ 420 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 421 422 /* 423 * Hugetlb definitions. 424 */ 425 #define HUGE_MAX_HSTATE 4 426 #define HPAGE_SHIFT PMD_SHIFT 427 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 428 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 429 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 430 431 static inline pte_t pgd_pte(pgd_t pgd) 432 { 433 return __pte(pgd_val(pgd)); 434 } 435 436 static inline pte_t p4d_pte(p4d_t p4d) 437 { 438 return __pte(p4d_val(p4d)); 439 } 440 441 static inline pte_t pud_pte(pud_t pud) 442 { 443 return __pte(pud_val(pud)); 444 } 445 446 static inline pud_t pte_pud(pte_t pte) 447 { 448 return __pud(pte_val(pte)); 449 } 450 451 static inline pmd_t pud_pmd(pud_t pud) 452 { 453 return __pmd(pud_val(pud)); 454 } 455 456 static inline pte_t pmd_pte(pmd_t pmd) 457 { 458 return __pte(pmd_val(pmd)); 459 } 460 461 static inline pmd_t pte_pmd(pte_t pte) 462 { 463 return __pmd(pte_val(pte)); 464 } 465 466 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 467 { 468 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 469 } 470 471 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 472 { 473 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 474 } 475 476 static inline pte_t pte_swp_mkexclusive(pte_t pte) 477 { 478 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 479 } 480 481 static inline int pte_swp_exclusive(pte_t pte) 482 { 483 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 484 } 485 486 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 487 { 488 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 489 } 490 491 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 492 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 493 { 494 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 495 } 496 497 static inline int pte_swp_uffd_wp(pte_t pte) 498 { 499 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 500 } 501 502 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 503 { 504 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 505 } 506 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 507 508 #ifdef CONFIG_NUMA_BALANCING 509 /* 510 * See the comment in include/linux/pgtable.h 511 */ 512 static inline int pte_protnone(pte_t pte) 513 { 514 /* 515 * pte_present_invalid() tells us that the pte is invalid from HW 516 * perspective but present from SW perspective, so the fields are to be 517 * interpretted as per the HW layout. The second 2 checks are the unique 518 * encoding that we use for PROT_NONE. It is insufficient to only use 519 * the first check because we share the same encoding scheme with pmds 520 * which support pmd_mkinvalid(), so can be present-invalid without 521 * being PROT_NONE. 522 */ 523 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 524 } 525 526 static inline int pmd_protnone(pmd_t pmd) 527 { 528 return pte_protnone(pmd_pte(pmd)); 529 } 530 #endif 531 532 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 533 534 /* 535 * THP definitions. 536 */ 537 538 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 539 static inline int pmd_trans_huge(pmd_t pmd) 540 { 541 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 542 } 543 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 544 545 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 546 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 547 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 548 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 549 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 550 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 551 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 552 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 553 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 554 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 555 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 556 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 557 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 558 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 559 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 560 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 561 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 562 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 563 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 564 #define pmd_swp_clear_uffd_wp(pmd) \ 565 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 566 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 567 568 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 569 570 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 571 572 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 573 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 574 #endif 575 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 576 { 577 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 578 } 579 580 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 581 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 582 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 583 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 584 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 585 586 #define pud_young(pud) pte_young(pud_pte(pud)) 587 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 588 #define pud_write(pud) pte_write(pud_pte(pud)) 589 590 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 591 592 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 593 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 594 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 595 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 596 597 static inline void __set_pte_at(struct mm_struct *mm, 598 unsigned long __always_unused addr, 599 pte_t *ptep, pte_t pte, unsigned int nr) 600 { 601 __sync_cache_and_tags(pte, nr); 602 __check_safe_pte_update(mm, ptep, pte); 603 __set_pte(ptep, pte); 604 } 605 606 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 607 pmd_t *pmdp, pmd_t pmd) 608 { 609 page_table_check_pmd_set(mm, pmdp, pmd); 610 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 611 PMD_SIZE >> PAGE_SHIFT); 612 } 613 614 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 615 pud_t *pudp, pud_t pud) 616 { 617 page_table_check_pud_set(mm, pudp, pud); 618 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 619 PUD_SIZE >> PAGE_SHIFT); 620 } 621 622 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 623 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 624 625 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 626 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 627 628 #define __pgprot_modify(prot,mask,bits) \ 629 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 630 631 #define pgprot_nx(prot) \ 632 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 633 634 /* 635 * Mark the prot value as uncacheable and unbufferable. 636 */ 637 #define pgprot_noncached(prot) \ 638 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 639 #define pgprot_writecombine(prot) \ 640 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 641 #define pgprot_device(prot) \ 642 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 643 #define pgprot_tagged(prot) \ 644 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 645 #define pgprot_mhp pgprot_tagged 646 /* 647 * DMA allocations for non-coherent devices use what the Arm architecture calls 648 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 649 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 650 * is intended for MMIO and thus forbids speculation, preserves access size, 651 * requires strict alignment and can also force write responses to come from the 652 * endpoint. 653 */ 654 #define pgprot_dmacoherent(prot) \ 655 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 656 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 657 658 #define __HAVE_PHYS_MEM_ACCESS_PROT 659 struct file; 660 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 661 unsigned long size, pgprot_t vma_prot); 662 663 #define pmd_none(pmd) (!pmd_val(pmd)) 664 665 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 666 PMD_TYPE_TABLE) 667 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 668 PMD_TYPE_SECT) 669 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 670 #define pmd_bad(pmd) (!pmd_table(pmd)) 671 672 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 673 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 674 675 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 676 static inline bool pud_sect(pud_t pud) { return false; } 677 static inline bool pud_table(pud_t pud) { return true; } 678 #else 679 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 680 PUD_TYPE_SECT) 681 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 682 PUD_TYPE_TABLE) 683 #endif 684 685 extern pgd_t init_pg_dir[]; 686 extern pgd_t init_pg_end[]; 687 extern pgd_t swapper_pg_dir[]; 688 extern pgd_t idmap_pg_dir[]; 689 extern pgd_t tramp_pg_dir[]; 690 extern pgd_t reserved_pg_dir[]; 691 692 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 693 694 static inline bool in_swapper_pgdir(void *addr) 695 { 696 return ((unsigned long)addr & PAGE_MASK) == 697 ((unsigned long)swapper_pg_dir & PAGE_MASK); 698 } 699 700 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 701 { 702 #ifdef __PAGETABLE_PMD_FOLDED 703 if (in_swapper_pgdir(pmdp)) { 704 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 705 return; 706 } 707 #endif /* __PAGETABLE_PMD_FOLDED */ 708 709 WRITE_ONCE(*pmdp, pmd); 710 711 if (pmd_valid(pmd)) { 712 dsb(ishst); 713 isb(); 714 } 715 } 716 717 static inline void pmd_clear(pmd_t *pmdp) 718 { 719 set_pmd(pmdp, __pmd(0)); 720 } 721 722 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 723 { 724 return __pmd_to_phys(pmd); 725 } 726 727 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 728 { 729 return (unsigned long)__va(pmd_page_paddr(pmd)); 730 } 731 732 /* Find an entry in the third-level page table. */ 733 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 734 735 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 736 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 737 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 738 739 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 740 741 /* use ONLY for statically allocated translation tables */ 742 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 743 744 /* 745 * Conversion functions: convert a page and protection to a page entry, 746 * and a page entry and page directory to the page they refer to. 747 */ 748 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 749 750 #if CONFIG_PGTABLE_LEVELS > 2 751 752 #define pmd_ERROR(e) \ 753 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 754 755 #define pud_none(pud) (!pud_val(pud)) 756 #define pud_bad(pud) (!pud_table(pud)) 757 #define pud_present(pud) pte_present(pud_pte(pud)) 758 #ifndef __PAGETABLE_PMD_FOLDED 759 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 760 #else 761 #define pud_leaf(pud) false 762 #endif 763 #define pud_valid(pud) pte_valid(pud_pte(pud)) 764 #define pud_user(pud) pte_user(pud_pte(pud)) 765 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 766 767 static inline bool pgtable_l4_enabled(void); 768 769 static inline void set_pud(pud_t *pudp, pud_t pud) 770 { 771 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 772 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 773 return; 774 } 775 776 WRITE_ONCE(*pudp, pud); 777 778 if (pud_valid(pud)) { 779 dsb(ishst); 780 isb(); 781 } 782 } 783 784 static inline void pud_clear(pud_t *pudp) 785 { 786 set_pud(pudp, __pud(0)); 787 } 788 789 static inline phys_addr_t pud_page_paddr(pud_t pud) 790 { 791 return __pud_to_phys(pud); 792 } 793 794 static inline pmd_t *pud_pgtable(pud_t pud) 795 { 796 return (pmd_t *)__va(pud_page_paddr(pud)); 797 } 798 799 /* Find an entry in the second-level page table. */ 800 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 801 802 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 803 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 804 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 805 806 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 807 808 /* use ONLY for statically allocated translation tables */ 809 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 810 811 #else 812 813 #define pud_valid(pud) false 814 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 815 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 816 817 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 818 #define pmd_set_fixmap(addr) NULL 819 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 820 #define pmd_clear_fixmap() 821 822 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 823 824 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 825 826 #if CONFIG_PGTABLE_LEVELS > 3 827 828 static __always_inline bool pgtable_l4_enabled(void) 829 { 830 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 831 return true; 832 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 833 return vabits_actual == VA_BITS; 834 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 835 } 836 837 static inline bool mm_pud_folded(const struct mm_struct *mm) 838 { 839 return !pgtable_l4_enabled(); 840 } 841 #define mm_pud_folded mm_pud_folded 842 843 #define pud_ERROR(e) \ 844 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 845 846 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 847 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 848 #define p4d_present(p4d) (!p4d_none(p4d)) 849 850 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 851 { 852 if (in_swapper_pgdir(p4dp)) { 853 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 854 return; 855 } 856 857 WRITE_ONCE(*p4dp, p4d); 858 dsb(ishst); 859 isb(); 860 } 861 862 static inline void p4d_clear(p4d_t *p4dp) 863 { 864 if (pgtable_l4_enabled()) 865 set_p4d(p4dp, __p4d(0)); 866 } 867 868 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 869 { 870 return __p4d_to_phys(p4d); 871 } 872 873 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 874 875 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 876 { 877 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 878 } 879 880 static inline pud_t *p4d_pgtable(p4d_t p4d) 881 { 882 return (pud_t *)__va(p4d_page_paddr(p4d)); 883 } 884 885 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 886 { 887 BUG_ON(!pgtable_l4_enabled()); 888 889 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 890 } 891 892 static inline 893 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 894 { 895 if (!pgtable_l4_enabled()) 896 return p4d_to_folded_pud(p4dp, addr); 897 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 898 } 899 #define pud_offset_lockless pud_offset_lockless 900 901 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 902 { 903 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 904 } 905 #define pud_offset pud_offset 906 907 static inline pud_t *pud_set_fixmap(unsigned long addr) 908 { 909 if (!pgtable_l4_enabled()) 910 return NULL; 911 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 912 } 913 914 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 915 { 916 if (!pgtable_l4_enabled()) 917 return p4d_to_folded_pud(p4dp, addr); 918 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 919 } 920 921 static inline void pud_clear_fixmap(void) 922 { 923 if (pgtable_l4_enabled()) 924 clear_fixmap(FIX_PUD); 925 } 926 927 /* use ONLY for statically allocated translation tables */ 928 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 929 { 930 if (!pgtable_l4_enabled()) 931 return p4d_to_folded_pud(p4dp, addr); 932 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 933 } 934 935 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 936 937 #else 938 939 static inline bool pgtable_l4_enabled(void) { return false; } 940 941 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 942 943 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 944 #define pud_set_fixmap(addr) NULL 945 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 946 #define pud_clear_fixmap() 947 948 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 949 950 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 951 952 #if CONFIG_PGTABLE_LEVELS > 4 953 954 static __always_inline bool pgtable_l5_enabled(void) 955 { 956 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 957 return vabits_actual == VA_BITS; 958 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 959 } 960 961 static inline bool mm_p4d_folded(const struct mm_struct *mm) 962 { 963 return !pgtable_l5_enabled(); 964 } 965 #define mm_p4d_folded mm_p4d_folded 966 967 #define p4d_ERROR(e) \ 968 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 969 970 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 971 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 972 #define pgd_present(pgd) (!pgd_none(pgd)) 973 974 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 975 { 976 if (in_swapper_pgdir(pgdp)) { 977 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 978 return; 979 } 980 981 WRITE_ONCE(*pgdp, pgd); 982 dsb(ishst); 983 isb(); 984 } 985 986 static inline void pgd_clear(pgd_t *pgdp) 987 { 988 if (pgtable_l5_enabled()) 989 set_pgd(pgdp, __pgd(0)); 990 } 991 992 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 993 { 994 return __pgd_to_phys(pgd); 995 } 996 997 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 998 999 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1000 { 1001 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1002 } 1003 1004 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1005 { 1006 BUG_ON(!pgtable_l5_enabled()); 1007 1008 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1009 } 1010 1011 static inline 1012 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1013 { 1014 if (!pgtable_l5_enabled()) 1015 return pgd_to_folded_p4d(pgdp, addr); 1016 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1017 } 1018 #define p4d_offset_lockless p4d_offset_lockless 1019 1020 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1021 { 1022 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1023 } 1024 1025 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1026 { 1027 if (!pgtable_l5_enabled()) 1028 return NULL; 1029 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1030 } 1031 1032 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1033 { 1034 if (!pgtable_l5_enabled()) 1035 return pgd_to_folded_p4d(pgdp, addr); 1036 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1037 } 1038 1039 static inline void p4d_clear_fixmap(void) 1040 { 1041 if (pgtable_l5_enabled()) 1042 clear_fixmap(FIX_P4D); 1043 } 1044 1045 /* use ONLY for statically allocated translation tables */ 1046 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1047 { 1048 if (!pgtable_l5_enabled()) 1049 return pgd_to_folded_p4d(pgdp, addr); 1050 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1051 } 1052 1053 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1054 1055 #else 1056 1057 static inline bool pgtable_l5_enabled(void) { return false; } 1058 1059 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1060 1061 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1062 #define p4d_set_fixmap(addr) NULL 1063 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1064 #define p4d_clear_fixmap() 1065 1066 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1067 1068 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1069 1070 #define pgd_ERROR(e) \ 1071 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1072 1073 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1074 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1075 1076 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1077 { 1078 /* 1079 * Normal and Normal-Tagged are two different memory types and indices 1080 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1081 */ 1082 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1083 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1084 PTE_GP | PTE_ATTRINDX_MASK; 1085 /* preserve the hardware dirty information */ 1086 if (pte_hw_dirty(pte)) 1087 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1088 1089 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1090 /* 1091 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1092 * dirtiness again. 1093 */ 1094 if (pte_sw_dirty(pte)) 1095 pte = pte_mkdirty(pte); 1096 return pte; 1097 } 1098 1099 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1100 { 1101 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1102 } 1103 1104 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1105 unsigned long address, pte_t *ptep, 1106 pte_t entry, int dirty); 1107 1108 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1109 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1110 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1111 unsigned long address, pmd_t *pmdp, 1112 pmd_t entry, int dirty) 1113 { 1114 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1115 pmd_pte(entry), dirty); 1116 } 1117 1118 static inline int pud_devmap(pud_t pud) 1119 { 1120 return 0; 1121 } 1122 1123 static inline int pgd_devmap(pgd_t pgd) 1124 { 1125 return 0; 1126 } 1127 #endif 1128 1129 #ifdef CONFIG_PAGE_TABLE_CHECK 1130 static inline bool pte_user_accessible_page(pte_t pte) 1131 { 1132 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1133 } 1134 1135 static inline bool pmd_user_accessible_page(pmd_t pmd) 1136 { 1137 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1138 } 1139 1140 static inline bool pud_user_accessible_page(pud_t pud) 1141 { 1142 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1143 } 1144 #endif 1145 1146 /* 1147 * Atomic pte/pmd modifications. 1148 */ 1149 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1150 unsigned long address, 1151 pte_t *ptep) 1152 { 1153 pte_t old_pte, pte; 1154 1155 pte = __ptep_get(ptep); 1156 do { 1157 old_pte = pte; 1158 pte = pte_mkold(pte); 1159 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1160 pte_val(old_pte), pte_val(pte)); 1161 } while (pte_val(pte) != pte_val(old_pte)); 1162 1163 return pte_young(pte); 1164 } 1165 1166 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1167 unsigned long address, pte_t *ptep) 1168 { 1169 int young = __ptep_test_and_clear_young(vma, address, ptep); 1170 1171 if (young) { 1172 /* 1173 * We can elide the trailing DSB here since the worst that can 1174 * happen is that a CPU continues to use the young entry in its 1175 * TLB and we mistakenly reclaim the associated page. The 1176 * window for such an event is bounded by the next 1177 * context-switch, which provides a DSB to complete the TLB 1178 * invalidation. 1179 */ 1180 flush_tlb_page_nosync(vma, address); 1181 } 1182 1183 return young; 1184 } 1185 1186 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1187 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1188 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1189 unsigned long address, 1190 pmd_t *pmdp) 1191 { 1192 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1193 } 1194 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1195 1196 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1197 unsigned long address, pte_t *ptep) 1198 { 1199 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1200 1201 page_table_check_pte_clear(mm, pte); 1202 1203 return pte; 1204 } 1205 1206 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1207 pte_t *ptep, unsigned int nr, int full) 1208 { 1209 for (;;) { 1210 __ptep_get_and_clear(mm, addr, ptep); 1211 if (--nr == 0) 1212 break; 1213 ptep++; 1214 addr += PAGE_SIZE; 1215 } 1216 } 1217 1218 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1219 unsigned long addr, pte_t *ptep, 1220 unsigned int nr, int full) 1221 { 1222 pte_t pte, tmp_pte; 1223 1224 pte = __ptep_get_and_clear(mm, addr, ptep); 1225 while (--nr) { 1226 ptep++; 1227 addr += PAGE_SIZE; 1228 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1229 if (pte_dirty(tmp_pte)) 1230 pte = pte_mkdirty(pte); 1231 if (pte_young(tmp_pte)) 1232 pte = pte_mkyoung(pte); 1233 } 1234 return pte; 1235 } 1236 1237 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1238 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1239 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1240 unsigned long address, pmd_t *pmdp) 1241 { 1242 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1243 1244 page_table_check_pmd_clear(mm, pmd); 1245 1246 return pmd; 1247 } 1248 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1249 1250 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1251 unsigned long address, pte_t *ptep, 1252 pte_t pte) 1253 { 1254 pte_t old_pte; 1255 1256 do { 1257 old_pte = pte; 1258 pte = pte_wrprotect(pte); 1259 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1260 pte_val(old_pte), pte_val(pte)); 1261 } while (pte_val(pte) != pte_val(old_pte)); 1262 } 1263 1264 /* 1265 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1266 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1267 */ 1268 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1269 unsigned long address, pte_t *ptep) 1270 { 1271 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1272 } 1273 1274 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1275 pte_t *ptep, unsigned int nr) 1276 { 1277 unsigned int i; 1278 1279 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1280 __ptep_set_wrprotect(mm, address, ptep); 1281 } 1282 1283 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1284 unsigned long addr, pte_t *ptep, 1285 pte_t pte, cydp_t flags) 1286 { 1287 pte_t old_pte; 1288 1289 do { 1290 old_pte = pte; 1291 1292 if (flags & CYDP_CLEAR_YOUNG) 1293 pte = pte_mkold(pte); 1294 if (flags & CYDP_CLEAR_DIRTY) 1295 pte = pte_mkclean(pte); 1296 1297 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1298 pte_val(old_pte), pte_val(pte)); 1299 } while (pte_val(pte) != pte_val(old_pte)); 1300 } 1301 1302 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1303 unsigned long addr, pte_t *ptep, 1304 unsigned int nr, cydp_t flags) 1305 { 1306 pte_t pte; 1307 1308 for (;;) { 1309 pte = __ptep_get(ptep); 1310 1311 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1312 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1313 else 1314 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1315 1316 if (--nr == 0) 1317 break; 1318 ptep++; 1319 addr += PAGE_SIZE; 1320 } 1321 } 1322 1323 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1324 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1325 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1326 unsigned long address, pmd_t *pmdp) 1327 { 1328 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1329 } 1330 1331 #define pmdp_establish pmdp_establish 1332 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1333 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1334 { 1335 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1336 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1337 } 1338 #endif 1339 1340 /* 1341 * Encode and decode a swap entry: 1342 * bits 0-1: present (must be zero) 1343 * bits 2: remember PG_anon_exclusive 1344 * bit 3: remember uffd-wp state 1345 * bits 6-10: swap type 1346 * bit 11: PTE_PRESENT_INVALID (must be zero) 1347 * bits 12-61: swap offset 1348 */ 1349 #define __SWP_TYPE_SHIFT 6 1350 #define __SWP_TYPE_BITS 5 1351 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1352 #define __SWP_OFFSET_SHIFT 12 1353 #define __SWP_OFFSET_BITS 50 1354 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1355 1356 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1357 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1358 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1359 1360 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1361 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1362 1363 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1364 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1365 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1366 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1367 1368 /* 1369 * Ensure that there are not more swap files than can be encoded in the kernel 1370 * PTEs. 1371 */ 1372 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1373 1374 #ifdef CONFIG_ARM64_MTE 1375 1376 #define __HAVE_ARCH_PREPARE_TO_SWAP 1377 extern int arch_prepare_to_swap(struct folio *folio); 1378 1379 #define __HAVE_ARCH_SWAP_INVALIDATE 1380 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1381 { 1382 if (system_supports_mte()) 1383 mte_invalidate_tags(type, offset); 1384 } 1385 1386 static inline void arch_swap_invalidate_area(int type) 1387 { 1388 if (system_supports_mte()) 1389 mte_invalidate_tags_area(type); 1390 } 1391 1392 #define __HAVE_ARCH_SWAP_RESTORE 1393 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1394 1395 #endif /* CONFIG_ARM64_MTE */ 1396 1397 /* 1398 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1399 */ 1400 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1401 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1402 unsigned int nr) 1403 { 1404 /* 1405 * We don't do anything here, so there's a very small chance of 1406 * us retaking a user fault which we just fixed up. The alternative 1407 * is doing a dsb(ishst), but that penalises the fastpath. 1408 */ 1409 } 1410 1411 #define update_mmu_cache(vma, addr, ptep) \ 1412 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1413 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1414 1415 #ifdef CONFIG_ARM64_PA_BITS_52 1416 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1417 #else 1418 #define phys_to_ttbr(addr) (addr) 1419 #endif 1420 1421 /* 1422 * On arm64 without hardware Access Flag, copying from user will fail because 1423 * the pte is old and cannot be marked young. So we always end up with zeroed 1424 * page after fork() + CoW for pfn mappings. We don't always have a 1425 * hardware-managed access flag on arm64. 1426 */ 1427 #define arch_has_hw_pte_young cpu_has_hw_af 1428 1429 /* 1430 * Experimentally, it's cheap to set the access flag in hardware and we 1431 * benefit from prefaulting mappings as 'old' to start with. 1432 */ 1433 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1434 1435 static inline bool pud_sect_supported(void) 1436 { 1437 return PAGE_SIZE == SZ_4K; 1438 } 1439 1440 1441 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1442 #define ptep_modify_prot_start ptep_modify_prot_start 1443 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1444 unsigned long addr, pte_t *ptep); 1445 1446 #define ptep_modify_prot_commit ptep_modify_prot_commit 1447 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1448 unsigned long addr, pte_t *ptep, 1449 pte_t old_pte, pte_t new_pte); 1450 1451 #ifdef CONFIG_ARM64_CONTPTE 1452 1453 /* 1454 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1455 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1456 * a private implementation detail of the public ptep API (see below). 1457 */ 1458 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1459 pte_t *ptep, pte_t pte); 1460 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1461 pte_t *ptep, pte_t pte); 1462 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1463 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1464 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1465 pte_t *ptep, pte_t pte, unsigned int nr); 1466 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1467 pte_t *ptep, unsigned int nr, int full); 1468 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1469 unsigned long addr, pte_t *ptep, 1470 unsigned int nr, int full); 1471 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1472 unsigned long addr, pte_t *ptep); 1473 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1474 unsigned long addr, pte_t *ptep); 1475 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1476 pte_t *ptep, unsigned int nr); 1477 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1478 unsigned long addr, pte_t *ptep, 1479 pte_t entry, int dirty); 1480 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1481 unsigned long addr, pte_t *ptep, 1482 unsigned int nr, cydp_t flags); 1483 1484 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1485 unsigned long addr, pte_t *ptep, pte_t pte) 1486 { 1487 /* 1488 * Only bother trying if both the virtual and physical addresses are 1489 * aligned and correspond to the last entry in a contig range. The core 1490 * code mostly modifies ranges from low to high, so this is the likely 1491 * the last modification in the contig range, so a good time to fold. 1492 * We can't fold special mappings, because there is no associated folio. 1493 */ 1494 1495 const unsigned long contmask = CONT_PTES - 1; 1496 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1497 1498 if (unlikely(valign)) { 1499 bool palign = (pte_pfn(pte) & contmask) == contmask; 1500 1501 if (unlikely(palign && 1502 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1503 __contpte_try_fold(mm, addr, ptep, pte); 1504 } 1505 } 1506 1507 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1508 unsigned long addr, pte_t *ptep, pte_t pte) 1509 { 1510 if (unlikely(pte_valid_cont(pte))) 1511 __contpte_try_unfold(mm, addr, ptep, pte); 1512 } 1513 1514 #define pte_batch_hint pte_batch_hint 1515 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1516 { 1517 if (!pte_valid_cont(pte)) 1518 return 1; 1519 1520 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1521 } 1522 1523 /* 1524 * The below functions constitute the public API that arm64 presents to the 1525 * core-mm to manipulate PTE entries within their page tables (or at least this 1526 * is the subset of the API that arm64 needs to implement). These public 1527 * versions will automatically and transparently apply the contiguous bit where 1528 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1529 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1530 * private versions, which are prefixed with double underscore. All of these 1531 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1532 * held. Although the contiguous bit is considered private to the 1533 * implementation, it is deliberately allowed to leak through the getters (e.g. 1534 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1535 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1536 * its possible a pte will be passed to a setter with the contiguous bit set, so 1537 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1538 * setting it in the pgtable. 1539 */ 1540 1541 #define ptep_get ptep_get 1542 static inline pte_t ptep_get(pte_t *ptep) 1543 { 1544 pte_t pte = __ptep_get(ptep); 1545 1546 if (likely(!pte_valid_cont(pte))) 1547 return pte; 1548 1549 return contpte_ptep_get(ptep, pte); 1550 } 1551 1552 #define ptep_get_lockless ptep_get_lockless 1553 static inline pte_t ptep_get_lockless(pte_t *ptep) 1554 { 1555 pte_t pte = __ptep_get(ptep); 1556 1557 if (likely(!pte_valid_cont(pte))) 1558 return pte; 1559 1560 return contpte_ptep_get_lockless(ptep); 1561 } 1562 1563 static inline void set_pte(pte_t *ptep, pte_t pte) 1564 { 1565 /* 1566 * We don't have the mm or vaddr so cannot unfold contig entries (since 1567 * it requires tlb maintenance). set_pte() is not used in core code, so 1568 * this should never even be called. Regardless do our best to service 1569 * any call and emit a warning if there is any attempt to set a pte on 1570 * top of an existing contig range. 1571 */ 1572 pte_t orig_pte = __ptep_get(ptep); 1573 1574 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1575 __set_pte(ptep, pte_mknoncont(pte)); 1576 } 1577 1578 #define set_ptes set_ptes 1579 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1580 pte_t *ptep, pte_t pte, unsigned int nr) 1581 { 1582 pte = pte_mknoncont(pte); 1583 1584 if (likely(nr == 1)) { 1585 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1586 __set_ptes(mm, addr, ptep, pte, 1); 1587 contpte_try_fold(mm, addr, ptep, pte); 1588 } else { 1589 contpte_set_ptes(mm, addr, ptep, pte, nr); 1590 } 1591 } 1592 1593 static inline void pte_clear(struct mm_struct *mm, 1594 unsigned long addr, pte_t *ptep) 1595 { 1596 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1597 __pte_clear(mm, addr, ptep); 1598 } 1599 1600 #define clear_full_ptes clear_full_ptes 1601 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1602 pte_t *ptep, unsigned int nr, int full) 1603 { 1604 if (likely(nr == 1)) { 1605 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1606 __clear_full_ptes(mm, addr, ptep, nr, full); 1607 } else { 1608 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1609 } 1610 } 1611 1612 #define get_and_clear_full_ptes get_and_clear_full_ptes 1613 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1614 unsigned long addr, pte_t *ptep, 1615 unsigned int nr, int full) 1616 { 1617 pte_t pte; 1618 1619 if (likely(nr == 1)) { 1620 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1621 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1622 } else { 1623 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1624 } 1625 1626 return pte; 1627 } 1628 1629 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1630 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1631 unsigned long addr, pte_t *ptep) 1632 { 1633 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1634 return __ptep_get_and_clear(mm, addr, ptep); 1635 } 1636 1637 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1638 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1639 unsigned long addr, pte_t *ptep) 1640 { 1641 pte_t orig_pte = __ptep_get(ptep); 1642 1643 if (likely(!pte_valid_cont(orig_pte))) 1644 return __ptep_test_and_clear_young(vma, addr, ptep); 1645 1646 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1647 } 1648 1649 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1650 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1651 unsigned long addr, pte_t *ptep) 1652 { 1653 pte_t orig_pte = __ptep_get(ptep); 1654 1655 if (likely(!pte_valid_cont(orig_pte))) 1656 return __ptep_clear_flush_young(vma, addr, ptep); 1657 1658 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1659 } 1660 1661 #define wrprotect_ptes wrprotect_ptes 1662 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1663 unsigned long addr, pte_t *ptep, unsigned int nr) 1664 { 1665 if (likely(nr == 1)) { 1666 /* 1667 * Optimization: wrprotect_ptes() can only be called for present 1668 * ptes so we only need to check contig bit as condition for 1669 * unfold, and we can remove the contig bit from the pte we read 1670 * to avoid re-reading. This speeds up fork() which is sensitive 1671 * for order-0 folios. Equivalent to contpte_try_unfold(). 1672 */ 1673 pte_t orig_pte = __ptep_get(ptep); 1674 1675 if (unlikely(pte_cont(orig_pte))) { 1676 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1677 orig_pte = pte_mknoncont(orig_pte); 1678 } 1679 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1680 } else { 1681 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1682 } 1683 } 1684 1685 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1686 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1687 unsigned long addr, pte_t *ptep) 1688 { 1689 wrprotect_ptes(mm, addr, ptep, 1); 1690 } 1691 1692 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1693 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1694 unsigned long addr, pte_t *ptep, 1695 pte_t entry, int dirty) 1696 { 1697 pte_t orig_pte = __ptep_get(ptep); 1698 1699 entry = pte_mknoncont(entry); 1700 1701 if (likely(!pte_valid_cont(orig_pte))) 1702 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1703 1704 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1705 } 1706 1707 #define clear_young_dirty_ptes clear_young_dirty_ptes 1708 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1709 unsigned long addr, pte_t *ptep, 1710 unsigned int nr, cydp_t flags) 1711 { 1712 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1713 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1714 else 1715 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1716 } 1717 1718 #else /* CONFIG_ARM64_CONTPTE */ 1719 1720 #define ptep_get __ptep_get 1721 #define set_pte __set_pte 1722 #define set_ptes __set_ptes 1723 #define pte_clear __pte_clear 1724 #define clear_full_ptes __clear_full_ptes 1725 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1726 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1727 #define ptep_get_and_clear __ptep_get_and_clear 1728 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1729 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1730 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1731 #define ptep_clear_flush_young __ptep_clear_flush_young 1732 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1733 #define ptep_set_wrprotect __ptep_set_wrprotect 1734 #define wrprotect_ptes __wrprotect_ptes 1735 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1736 #define ptep_set_access_flags __ptep_set_access_flags 1737 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1738 1739 #endif /* CONFIG_ARM64_CONTPTE */ 1740 1741 #endif /* !__ASSEMBLY__ */ 1742 1743 #endif /* __ASM_PGTABLE_H */ 1744