1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 22 * and fixed mappings 23 */ 24 #define VMALLOC_START (MODULES_END) 25 #define VMALLOC_END (VMEMMAP_START - SZ_256M) 26 27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 28 29 #ifndef __ASSEMBLY__ 30 31 #include <asm/cmpxchg.h> 32 #include <asm/fixmap.h> 33 #include <linux/mmdebug.h> 34 #include <linux/mm_types.h> 35 #include <linux/sched.h> 36 #include <linux/page_table_check.h> 37 38 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 40 41 /* Set stride and tlb_level in flush_*_tlb_range */ 42 #define flush_pmd_tlb_range(vma, addr, end) \ 43 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 44 #define flush_pud_tlb_range(vma, addr, end) \ 45 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 46 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 47 48 static inline bool arch_thp_swp_supported(void) 49 { 50 return !system_supports_mte(); 51 } 52 #define arch_thp_swp_supported arch_thp_swp_supported 53 54 /* 55 * Outside of a few very special situations (e.g. hibernation), we always 56 * use broadcast TLB invalidation instructions, therefore a spurious page 57 * fault on one CPU which has been handled concurrently by another CPU 58 * does not need to perform additional invalidation. 59 */ 60 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 61 62 /* 63 * ZERO_PAGE is a global shared page that is always zero: used 64 * for zero-mapped memory areas etc.. 65 */ 66 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 67 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 71 72 /* 73 * Macros to convert between a physical address and its placement in a 74 * page table entry, taking care of 52-bit addresses. 75 */ 76 #ifdef CONFIG_ARM64_PA_BITS_52 77 static inline phys_addr_t __pte_to_phys(pte_t pte) 78 { 79 return (pte_val(pte) & PTE_ADDR_LOW) | 80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81 } 82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83 { 84 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK; 85 } 86 #else 87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 88 #define __phys_to_pte_val(phys) (phys) 89 #endif 90 91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 92 #define pfn_pte(pfn,prot) \ 93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 94 95 #define pte_none(pte) (!pte_val(pte)) 96 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 107 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 108 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 109 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 110 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 111 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 112 113 #define pte_cont_addr_end(addr, end) \ 114 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 115 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 116 }) 117 118 #define pmd_cont_addr_end(addr, end) \ 119 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 121 }) 122 123 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 124 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 125 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 126 127 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 128 /* 129 * Execute-only user mappings do not have the PTE_USER bit set. All valid 130 * kernel mappings have the PTE_UXN bit set. 131 */ 132 #define pte_valid_not_user(pte) \ 133 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 134 /* 135 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 136 * so that we don't erroneously return false for pages that have been 137 * remapped as PROT_NONE but are yet to be flushed from the TLB. 138 * Note that we can't make any assumptions based on the state of the access 139 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 140 * TLB. 141 */ 142 #define pte_accessible(mm, pte) \ 143 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 144 145 /* 146 * p??_access_permitted() is true for valid user mappings (PTE_USER 147 * bit set, subject to the write permission check). For execute-only 148 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 149 * not set) must return false. PROT_NONE mappings do not have the 150 * PTE_VALID bit set. 151 */ 152 #define pte_access_permitted(pte, write) \ 153 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 154 #define pmd_access_permitted(pmd, write) \ 155 (pte_access_permitted(pmd_pte(pmd), (write))) 156 #define pud_access_permitted(pud, write) \ 157 (pte_access_permitted(pud_pte(pud), (write))) 158 159 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 160 { 161 pte_val(pte) &= ~pgprot_val(prot); 162 return pte; 163 } 164 165 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 166 { 167 pte_val(pte) |= pgprot_val(prot); 168 return pte; 169 } 170 171 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 172 { 173 pmd_val(pmd) &= ~pgprot_val(prot); 174 return pmd; 175 } 176 177 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 178 { 179 pmd_val(pmd) |= pgprot_val(prot); 180 return pmd; 181 } 182 183 static inline pte_t pte_mkwrite(pte_t pte) 184 { 185 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 186 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 187 return pte; 188 } 189 190 static inline pte_t pte_mkclean(pte_t pte) 191 { 192 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 193 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 194 195 return pte; 196 } 197 198 static inline pte_t pte_mkdirty(pte_t pte) 199 { 200 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 201 202 if (pte_write(pte)) 203 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 204 205 return pte; 206 } 207 208 static inline pte_t pte_wrprotect(pte_t pte) 209 { 210 /* 211 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 212 * clear), set the PTE_DIRTY bit. 213 */ 214 if (pte_hw_dirty(pte)) 215 pte = pte_mkdirty(pte); 216 217 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 218 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 219 return pte; 220 } 221 222 static inline pte_t pte_mkold(pte_t pte) 223 { 224 return clear_pte_bit(pte, __pgprot(PTE_AF)); 225 } 226 227 static inline pte_t pte_mkyoung(pte_t pte) 228 { 229 return set_pte_bit(pte, __pgprot(PTE_AF)); 230 } 231 232 static inline pte_t pte_mkspecial(pte_t pte) 233 { 234 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 235 } 236 237 static inline pte_t pte_mkcont(pte_t pte) 238 { 239 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 240 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 241 } 242 243 static inline pte_t pte_mknoncont(pte_t pte) 244 { 245 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 246 } 247 248 static inline pte_t pte_mkpresent(pte_t pte) 249 { 250 return set_pte_bit(pte, __pgprot(PTE_VALID)); 251 } 252 253 static inline pmd_t pmd_mkcont(pmd_t pmd) 254 { 255 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 256 } 257 258 static inline pte_t pte_mkdevmap(pte_t pte) 259 { 260 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 261 } 262 263 static inline void set_pte(pte_t *ptep, pte_t pte) 264 { 265 WRITE_ONCE(*ptep, pte); 266 267 /* 268 * Only if the new pte is valid and kernel, otherwise TLB maintenance 269 * or update_mmu_cache() have the necessary barriers. 270 */ 271 if (pte_valid_not_user(pte)) { 272 dsb(ishst); 273 isb(); 274 } 275 } 276 277 extern void __sync_icache_dcache(pte_t pteval); 278 bool pgattr_change_is_safe(u64 old, u64 new); 279 280 /* 281 * PTE bits configuration in the presence of hardware Dirty Bit Management 282 * (PTE_WRITE == PTE_DBM): 283 * 284 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 285 * 0 0 | 1 0 0 286 * 0 1 | 1 1 0 287 * 1 0 | 1 0 1 288 * 1 1 | 0 1 x 289 * 290 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 291 * the page fault mechanism. Checking the dirty status of a pte becomes: 292 * 293 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 294 */ 295 296 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 297 pte_t pte) 298 { 299 pte_t old_pte; 300 301 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 302 return; 303 304 old_pte = READ_ONCE(*ptep); 305 306 if (!pte_valid(old_pte) || !pte_valid(pte)) 307 return; 308 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 309 return; 310 311 /* 312 * Check for potential race with hardware updates of the pte 313 * (ptep_set_access_flags safely changes valid ptes without going 314 * through an invalid entry). 315 */ 316 VM_WARN_ONCE(!pte_young(pte), 317 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 318 __func__, pte_val(old_pte), pte_val(pte)); 319 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 320 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 321 __func__, pte_val(old_pte), pte_val(pte)); 322 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 323 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 324 __func__, pte_val(old_pte), pte_val(pte)); 325 } 326 327 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 328 pte_t *ptep, pte_t pte) 329 { 330 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 331 __sync_icache_dcache(pte); 332 333 /* 334 * If the PTE would provide user space access to the tags associated 335 * with it then ensure that the MTE tags are synchronised. Although 336 * pte_access_permitted() returns false for exec only mappings, they 337 * don't expose tags (instruction fetches don't check tags). 338 */ 339 if (system_supports_mte() && pte_access_permitted(pte, false) && 340 !pte_special(pte) && pte_tagged(pte)) 341 mte_sync_tags(pte); 342 343 __check_safe_pte_update(mm, ptep, pte); 344 345 set_pte(ptep, pte); 346 } 347 348 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 349 pte_t *ptep, pte_t pte) 350 { 351 page_table_check_pte_set(mm, ptep, pte); 352 return __set_pte_at(mm, addr, ptep, pte); 353 } 354 355 /* 356 * Huge pte definitions. 357 */ 358 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 359 360 /* 361 * Hugetlb definitions. 362 */ 363 #define HUGE_MAX_HSTATE 4 364 #define HPAGE_SHIFT PMD_SHIFT 365 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 366 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 367 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 368 369 static inline pte_t pgd_pte(pgd_t pgd) 370 { 371 return __pte(pgd_val(pgd)); 372 } 373 374 static inline pte_t p4d_pte(p4d_t p4d) 375 { 376 return __pte(p4d_val(p4d)); 377 } 378 379 static inline pte_t pud_pte(pud_t pud) 380 { 381 return __pte(pud_val(pud)); 382 } 383 384 static inline pud_t pte_pud(pte_t pte) 385 { 386 return __pud(pte_val(pte)); 387 } 388 389 static inline pmd_t pud_pmd(pud_t pud) 390 { 391 return __pmd(pud_val(pud)); 392 } 393 394 static inline pte_t pmd_pte(pmd_t pmd) 395 { 396 return __pte(pmd_val(pmd)); 397 } 398 399 static inline pmd_t pte_pmd(pte_t pte) 400 { 401 return __pmd(pte_val(pte)); 402 } 403 404 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 405 { 406 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 407 } 408 409 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 410 { 411 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 412 } 413 414 static inline pte_t pte_swp_mkexclusive(pte_t pte) 415 { 416 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 417 } 418 419 static inline int pte_swp_exclusive(pte_t pte) 420 { 421 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 422 } 423 424 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 425 { 426 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 427 } 428 429 /* 430 * Select all bits except the pfn 431 */ 432 static inline pgprot_t pte_pgprot(pte_t pte) 433 { 434 unsigned long pfn = pte_pfn(pte); 435 436 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 437 } 438 439 #ifdef CONFIG_NUMA_BALANCING 440 /* 441 * See the comment in include/linux/pgtable.h 442 */ 443 static inline int pte_protnone(pte_t pte) 444 { 445 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 446 } 447 448 static inline int pmd_protnone(pmd_t pmd) 449 { 450 return pte_protnone(pmd_pte(pmd)); 451 } 452 #endif 453 454 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 455 456 static inline int pmd_present(pmd_t pmd) 457 { 458 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 459 } 460 461 /* 462 * THP definitions. 463 */ 464 465 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 466 static inline int pmd_trans_huge(pmd_t pmd) 467 { 468 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 469 } 470 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 471 472 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 473 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 474 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 475 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 476 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 477 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 478 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 479 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 480 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 481 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 482 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 483 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 484 485 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 486 { 487 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 488 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 489 490 return pmd; 491 } 492 493 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 494 495 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 496 497 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 498 499 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 500 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 501 #endif 502 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 503 { 504 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 505 } 506 507 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 508 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 509 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 510 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 511 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 512 513 #define pud_young(pud) pte_young(pud_pte(pud)) 514 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 515 #define pud_write(pud) pte_write(pud_pte(pud)) 516 517 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 518 519 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 520 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 521 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 522 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 523 524 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 525 pmd_t *pmdp, pmd_t pmd) 526 { 527 page_table_check_pmd_set(mm, pmdp, pmd); 528 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); 529 } 530 531 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 532 pud_t *pudp, pud_t pud) 533 { 534 page_table_check_pud_set(mm, pudp, pud); 535 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); 536 } 537 538 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 539 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 540 541 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 542 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 543 544 #define __pgprot_modify(prot,mask,bits) \ 545 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 546 547 #define pgprot_nx(prot) \ 548 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 549 550 /* 551 * Mark the prot value as uncacheable and unbufferable. 552 */ 553 #define pgprot_noncached(prot) \ 554 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 555 #define pgprot_writecombine(prot) \ 556 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 557 #define pgprot_device(prot) \ 558 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 559 #define pgprot_tagged(prot) \ 560 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 561 #define pgprot_mhp pgprot_tagged 562 /* 563 * DMA allocations for non-coherent devices use what the Arm architecture calls 564 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 565 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 566 * is intended for MMIO and thus forbids speculation, preserves access size, 567 * requires strict alignment and can also force write responses to come from the 568 * endpoint. 569 */ 570 #define pgprot_dmacoherent(prot) \ 571 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 572 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 573 574 #define __HAVE_PHYS_MEM_ACCESS_PROT 575 struct file; 576 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 577 unsigned long size, pgprot_t vma_prot); 578 579 #define pmd_none(pmd) (!pmd_val(pmd)) 580 581 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 582 PMD_TYPE_TABLE) 583 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 584 PMD_TYPE_SECT) 585 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 586 #define pmd_bad(pmd) (!pmd_table(pmd)) 587 588 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 589 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 590 591 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 592 static inline bool pud_sect(pud_t pud) { return false; } 593 static inline bool pud_table(pud_t pud) { return true; } 594 #else 595 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 596 PUD_TYPE_SECT) 597 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 598 PUD_TYPE_TABLE) 599 #endif 600 601 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 602 extern pgd_t init_pg_end[]; 603 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 604 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 605 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 606 extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 607 608 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 609 610 static inline bool in_swapper_pgdir(void *addr) 611 { 612 return ((unsigned long)addr & PAGE_MASK) == 613 ((unsigned long)swapper_pg_dir & PAGE_MASK); 614 } 615 616 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 617 { 618 #ifdef __PAGETABLE_PMD_FOLDED 619 if (in_swapper_pgdir(pmdp)) { 620 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 621 return; 622 } 623 #endif /* __PAGETABLE_PMD_FOLDED */ 624 625 WRITE_ONCE(*pmdp, pmd); 626 627 if (pmd_valid(pmd)) { 628 dsb(ishst); 629 isb(); 630 } 631 } 632 633 static inline void pmd_clear(pmd_t *pmdp) 634 { 635 set_pmd(pmdp, __pmd(0)); 636 } 637 638 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 639 { 640 return __pmd_to_phys(pmd); 641 } 642 643 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 644 { 645 return (unsigned long)__va(pmd_page_paddr(pmd)); 646 } 647 648 /* Find an entry in the third-level page table. */ 649 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 650 651 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 652 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 653 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 654 655 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 656 657 /* use ONLY for statically allocated translation tables */ 658 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 659 660 /* 661 * Conversion functions: convert a page and protection to a page entry, 662 * and a page entry and page directory to the page they refer to. 663 */ 664 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 665 666 #if CONFIG_PGTABLE_LEVELS > 2 667 668 #define pmd_ERROR(e) \ 669 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 670 671 #define pud_none(pud) (!pud_val(pud)) 672 #define pud_bad(pud) (!pud_table(pud)) 673 #define pud_present(pud) pte_present(pud_pte(pud)) 674 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 675 #define pud_valid(pud) pte_valid(pud_pte(pud)) 676 #define pud_user(pud) pte_user(pud_pte(pud)) 677 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 678 679 static inline void set_pud(pud_t *pudp, pud_t pud) 680 { 681 #ifdef __PAGETABLE_PUD_FOLDED 682 if (in_swapper_pgdir(pudp)) { 683 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 684 return; 685 } 686 #endif /* __PAGETABLE_PUD_FOLDED */ 687 688 WRITE_ONCE(*pudp, pud); 689 690 if (pud_valid(pud)) { 691 dsb(ishst); 692 isb(); 693 } 694 } 695 696 static inline void pud_clear(pud_t *pudp) 697 { 698 set_pud(pudp, __pud(0)); 699 } 700 701 static inline phys_addr_t pud_page_paddr(pud_t pud) 702 { 703 return __pud_to_phys(pud); 704 } 705 706 static inline pmd_t *pud_pgtable(pud_t pud) 707 { 708 return (pmd_t *)__va(pud_page_paddr(pud)); 709 } 710 711 /* Find an entry in the second-level page table. */ 712 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 713 714 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 715 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 716 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 717 718 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 719 720 /* use ONLY for statically allocated translation tables */ 721 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 722 723 #else 724 725 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 726 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 727 728 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 729 #define pmd_set_fixmap(addr) NULL 730 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 731 #define pmd_clear_fixmap() 732 733 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 734 735 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 736 737 #if CONFIG_PGTABLE_LEVELS > 3 738 739 #define pud_ERROR(e) \ 740 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 741 742 #define p4d_none(p4d) (!p4d_val(p4d)) 743 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 744 #define p4d_present(p4d) (p4d_val(p4d)) 745 746 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 747 { 748 if (in_swapper_pgdir(p4dp)) { 749 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 750 return; 751 } 752 753 WRITE_ONCE(*p4dp, p4d); 754 dsb(ishst); 755 isb(); 756 } 757 758 static inline void p4d_clear(p4d_t *p4dp) 759 { 760 set_p4d(p4dp, __p4d(0)); 761 } 762 763 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 764 { 765 return __p4d_to_phys(p4d); 766 } 767 768 static inline pud_t *p4d_pgtable(p4d_t p4d) 769 { 770 return (pud_t *)__va(p4d_page_paddr(p4d)); 771 } 772 773 /* Find an entry in the first-level page table. */ 774 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 775 776 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 777 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 778 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 779 780 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 781 782 /* use ONLY for statically allocated translation tables */ 783 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 784 785 #else 786 787 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 788 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 789 790 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 791 #define pud_set_fixmap(addr) NULL 792 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 793 #define pud_clear_fixmap() 794 795 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 796 797 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 798 799 #define pgd_ERROR(e) \ 800 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 801 802 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 803 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 804 805 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 806 { 807 /* 808 * Normal and Normal-Tagged are two different memory types and indices 809 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 810 */ 811 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 812 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 813 PTE_ATTRINDX_MASK; 814 /* preserve the hardware dirty information */ 815 if (pte_hw_dirty(pte)) 816 pte = pte_mkdirty(pte); 817 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 818 return pte; 819 } 820 821 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 822 { 823 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 824 } 825 826 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 827 extern int ptep_set_access_flags(struct vm_area_struct *vma, 828 unsigned long address, pte_t *ptep, 829 pte_t entry, int dirty); 830 831 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 832 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 833 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 834 unsigned long address, pmd_t *pmdp, 835 pmd_t entry, int dirty) 836 { 837 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 838 } 839 840 static inline int pud_devmap(pud_t pud) 841 { 842 return 0; 843 } 844 845 static inline int pgd_devmap(pgd_t pgd) 846 { 847 return 0; 848 } 849 #endif 850 851 #ifdef CONFIG_PAGE_TABLE_CHECK 852 static inline bool pte_user_accessible_page(pte_t pte) 853 { 854 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 855 } 856 857 static inline bool pmd_user_accessible_page(pmd_t pmd) 858 { 859 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 860 } 861 862 static inline bool pud_user_accessible_page(pud_t pud) 863 { 864 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 865 } 866 #endif 867 868 /* 869 * Atomic pte/pmd modifications. 870 */ 871 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 872 static inline int __ptep_test_and_clear_young(pte_t *ptep) 873 { 874 pte_t old_pte, pte; 875 876 pte = READ_ONCE(*ptep); 877 do { 878 old_pte = pte; 879 pte = pte_mkold(pte); 880 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 881 pte_val(old_pte), pte_val(pte)); 882 } while (pte_val(pte) != pte_val(old_pte)); 883 884 return pte_young(pte); 885 } 886 887 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 888 unsigned long address, 889 pte_t *ptep) 890 { 891 return __ptep_test_and_clear_young(ptep); 892 } 893 894 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 895 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 896 unsigned long address, pte_t *ptep) 897 { 898 int young = ptep_test_and_clear_young(vma, address, ptep); 899 900 if (young) { 901 /* 902 * We can elide the trailing DSB here since the worst that can 903 * happen is that a CPU continues to use the young entry in its 904 * TLB and we mistakenly reclaim the associated page. The 905 * window for such an event is bounded by the next 906 * context-switch, which provides a DSB to complete the TLB 907 * invalidation. 908 */ 909 flush_tlb_page_nosync(vma, address); 910 } 911 912 return young; 913 } 914 915 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 916 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 917 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 918 unsigned long address, 919 pmd_t *pmdp) 920 { 921 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 922 } 923 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 924 925 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 926 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 927 unsigned long address, pte_t *ptep) 928 { 929 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 930 931 page_table_check_pte_clear(mm, pte); 932 933 return pte; 934 } 935 936 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 937 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 938 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 939 unsigned long address, pmd_t *pmdp) 940 { 941 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 942 943 page_table_check_pmd_clear(mm, pmd); 944 945 return pmd; 946 } 947 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 948 949 /* 950 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 951 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 952 */ 953 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 954 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 955 { 956 pte_t old_pte, pte; 957 958 pte = READ_ONCE(*ptep); 959 do { 960 old_pte = pte; 961 pte = pte_wrprotect(pte); 962 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 963 pte_val(old_pte), pte_val(pte)); 964 } while (pte_val(pte) != pte_val(old_pte)); 965 } 966 967 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 968 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 969 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 970 unsigned long address, pmd_t *pmdp) 971 { 972 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 973 } 974 975 #define pmdp_establish pmdp_establish 976 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 977 unsigned long address, pmd_t *pmdp, pmd_t pmd) 978 { 979 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 980 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 981 } 982 #endif 983 984 /* 985 * Encode and decode a swap entry: 986 * bits 0-1: present (must be zero) 987 * bits 2: remember PG_anon_exclusive 988 * bits 3-7: swap type 989 * bits 8-57: swap offset 990 * bit 58: PTE_PROT_NONE (must be zero) 991 */ 992 #define __SWP_TYPE_SHIFT 3 993 #define __SWP_TYPE_BITS 5 994 #define __SWP_OFFSET_BITS 50 995 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 996 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 997 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 998 999 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1000 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1001 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1002 1003 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1004 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1005 1006 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1007 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1008 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1009 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1010 1011 /* 1012 * Ensure that there are not more swap files than can be encoded in the kernel 1013 * PTEs. 1014 */ 1015 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1016 1017 #ifdef CONFIG_ARM64_MTE 1018 1019 #define __HAVE_ARCH_PREPARE_TO_SWAP 1020 static inline int arch_prepare_to_swap(struct page *page) 1021 { 1022 if (system_supports_mte()) 1023 return mte_save_tags(page); 1024 return 0; 1025 } 1026 1027 #define __HAVE_ARCH_SWAP_INVALIDATE 1028 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1029 { 1030 if (system_supports_mte()) 1031 mte_invalidate_tags(type, offset); 1032 } 1033 1034 static inline void arch_swap_invalidate_area(int type) 1035 { 1036 if (system_supports_mte()) 1037 mte_invalidate_tags_area(type); 1038 } 1039 1040 #define __HAVE_ARCH_SWAP_RESTORE 1041 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1042 { 1043 if (system_supports_mte()) 1044 mte_restore_tags(entry, &folio->page); 1045 } 1046 1047 #endif /* CONFIG_ARM64_MTE */ 1048 1049 /* 1050 * On AArch64, the cache coherency is handled via the set_pte_at() function. 1051 */ 1052 static inline void update_mmu_cache(struct vm_area_struct *vma, 1053 unsigned long addr, pte_t *ptep) 1054 { 1055 /* 1056 * We don't do anything here, so there's a very small chance of 1057 * us retaking a user fault which we just fixed up. The alternative 1058 * is doing a dsb(ishst), but that penalises the fastpath. 1059 */ 1060 } 1061 1062 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1063 1064 #ifdef CONFIG_ARM64_PA_BITS_52 1065 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1066 #else 1067 #define phys_to_ttbr(addr) (addr) 1068 #endif 1069 1070 /* 1071 * On arm64 without hardware Access Flag, copying from user will fail because 1072 * the pte is old and cannot be marked young. So we always end up with zeroed 1073 * page after fork() + CoW for pfn mappings. We don't always have a 1074 * hardware-managed access flag on arm64. 1075 */ 1076 #define arch_has_hw_pte_young cpu_has_hw_af 1077 1078 /* 1079 * Experimentally, it's cheap to set the access flag in hardware and we 1080 * benefit from prefaulting mappings as 'old' to start with. 1081 */ 1082 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1083 1084 static inline bool pud_sect_supported(void) 1085 { 1086 return PAGE_SIZE == SZ_4K; 1087 } 1088 1089 1090 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1091 #define ptep_modify_prot_start ptep_modify_prot_start 1092 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1093 unsigned long addr, pte_t *ptep); 1094 1095 #define ptep_modify_prot_commit ptep_modify_prot_commit 1096 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1097 unsigned long addr, pte_t *ptep, 1098 pte_t old_pte, pte_t new_pte); 1099 #endif /* !__ASSEMBLY__ */ 1100 1101 #endif /* __ASM_PGTABLE_H */ 1102