1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 22 * and fixed mappings 23 */ 24 #define VMALLOC_START (MODULES_END) 25 #define VMALLOC_END (VMEMMAP_START - SZ_256M) 26 27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 28 29 #ifndef __ASSEMBLY__ 30 31 #include <asm/cmpxchg.h> 32 #include <asm/fixmap.h> 33 #include <linux/mmdebug.h> 34 #include <linux/mm_types.h> 35 #include <linux/sched.h> 36 #include <linux/page_table_check.h> 37 38 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 40 41 /* Set stride and tlb_level in flush_*_tlb_range */ 42 #define flush_pmd_tlb_range(vma, addr, end) \ 43 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 44 #define flush_pud_tlb_range(vma, addr, end) \ 45 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 46 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 47 48 static inline bool arch_thp_swp_supported(void) 49 { 50 return !system_supports_mte(); 51 } 52 #define arch_thp_swp_supported arch_thp_swp_supported 53 54 /* 55 * Outside of a few very special situations (e.g. hibernation), we always 56 * use broadcast TLB invalidation instructions, therefore a spurious page 57 * fault on one CPU which has been handled concurrently by another CPU 58 * does not need to perform additional invalidation. 59 */ 60 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 61 62 /* 63 * ZERO_PAGE is a global shared page that is always zero: used 64 * for zero-mapped memory areas etc.. 65 */ 66 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 67 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 68 69 #define pte_ERROR(e) \ 70 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 71 72 /* 73 * Macros to convert between a physical address and its placement in a 74 * page table entry, taking care of 52-bit addresses. 75 */ 76 #ifdef CONFIG_ARM64_PA_BITS_52 77 static inline phys_addr_t __pte_to_phys(pte_t pte) 78 { 79 return (pte_val(pte) & PTE_ADDR_LOW) | 80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81 } 82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83 { 84 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK; 85 } 86 #else 87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 88 #define __phys_to_pte_val(phys) (phys) 89 #endif 90 91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 92 #define pfn_pte(pfn,prot) \ 93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 94 95 #define pte_none(pte) (!pte_val(pte)) 96 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 107 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 109 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 110 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 111 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 112 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 113 114 #define pte_cont_addr_end(addr, end) \ 115 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117 }) 118 119 #define pmd_cont_addr_end(addr, end) \ 120 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122 }) 123 124 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 125 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 126 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 127 128 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 129 /* 130 * Execute-only user mappings do not have the PTE_USER bit set. All valid 131 * kernel mappings have the PTE_UXN bit set. 132 */ 133 #define pte_valid_not_user(pte) \ 134 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 135 /* 136 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 137 * so that we don't erroneously return false for pages that have been 138 * remapped as PROT_NONE but are yet to be flushed from the TLB. 139 * Note that we can't make any assumptions based on the state of the access 140 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 141 * TLB. 142 */ 143 #define pte_accessible(mm, pte) \ 144 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 145 146 /* 147 * p??_access_permitted() is true for valid user mappings (PTE_USER 148 * bit set, subject to the write permission check). For execute-only 149 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 150 * not set) must return false. PROT_NONE mappings do not have the 151 * PTE_VALID bit set. 152 */ 153 #define pte_access_permitted(pte, write) \ 154 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 155 #define pmd_access_permitted(pmd, write) \ 156 (pte_access_permitted(pmd_pte(pmd), (write))) 157 #define pud_access_permitted(pud, write) \ 158 (pte_access_permitted(pud_pte(pud), (write))) 159 160 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 161 { 162 pte_val(pte) &= ~pgprot_val(prot); 163 return pte; 164 } 165 166 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 167 { 168 pte_val(pte) |= pgprot_val(prot); 169 return pte; 170 } 171 172 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 173 { 174 pmd_val(pmd) &= ~pgprot_val(prot); 175 return pmd; 176 } 177 178 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 179 { 180 pmd_val(pmd) |= pgprot_val(prot); 181 return pmd; 182 } 183 184 static inline pte_t pte_mkwrite_novma(pte_t pte) 185 { 186 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 187 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 188 return pte; 189 } 190 191 static inline pte_t pte_mkclean(pte_t pte) 192 { 193 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 194 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 195 196 return pte; 197 } 198 199 static inline pte_t pte_mkdirty(pte_t pte) 200 { 201 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 202 203 if (pte_write(pte)) 204 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 205 206 return pte; 207 } 208 209 static inline pte_t pte_wrprotect(pte_t pte) 210 { 211 /* 212 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 213 * clear), set the PTE_DIRTY bit. 214 */ 215 if (pte_hw_dirty(pte)) 216 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 217 218 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 219 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 220 return pte; 221 } 222 223 static inline pte_t pte_mkold(pte_t pte) 224 { 225 return clear_pte_bit(pte, __pgprot(PTE_AF)); 226 } 227 228 static inline pte_t pte_mkyoung(pte_t pte) 229 { 230 return set_pte_bit(pte, __pgprot(PTE_AF)); 231 } 232 233 static inline pte_t pte_mkspecial(pte_t pte) 234 { 235 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 236 } 237 238 static inline pte_t pte_mkcont(pte_t pte) 239 { 240 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 241 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 242 } 243 244 static inline pte_t pte_mknoncont(pte_t pte) 245 { 246 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 247 } 248 249 static inline pte_t pte_mkpresent(pte_t pte) 250 { 251 return set_pte_bit(pte, __pgprot(PTE_VALID)); 252 } 253 254 static inline pmd_t pmd_mkcont(pmd_t pmd) 255 { 256 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 257 } 258 259 static inline pte_t pte_mkdevmap(pte_t pte) 260 { 261 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 262 } 263 264 static inline void set_pte(pte_t *ptep, pte_t pte) 265 { 266 WRITE_ONCE(*ptep, pte); 267 268 /* 269 * Only if the new pte is valid and kernel, otherwise TLB maintenance 270 * or update_mmu_cache() have the necessary barriers. 271 */ 272 if (pte_valid_not_user(pte)) { 273 dsb(ishst); 274 isb(); 275 } 276 } 277 278 extern void __sync_icache_dcache(pte_t pteval); 279 bool pgattr_change_is_safe(u64 old, u64 new); 280 281 /* 282 * PTE bits configuration in the presence of hardware Dirty Bit Management 283 * (PTE_WRITE == PTE_DBM): 284 * 285 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 286 * 0 0 | 1 0 0 287 * 0 1 | 1 1 0 288 * 1 0 | 1 0 1 289 * 1 1 | 0 1 x 290 * 291 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 292 * the page fault mechanism. Checking the dirty status of a pte becomes: 293 * 294 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 295 */ 296 297 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 298 pte_t pte) 299 { 300 pte_t old_pte; 301 302 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 303 return; 304 305 old_pte = READ_ONCE(*ptep); 306 307 if (!pte_valid(old_pte) || !pte_valid(pte)) 308 return; 309 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 310 return; 311 312 /* 313 * Check for potential race with hardware updates of the pte 314 * (ptep_set_access_flags safely changes valid ptes without going 315 * through an invalid entry). 316 */ 317 VM_WARN_ONCE(!pte_young(pte), 318 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 319 __func__, pte_val(old_pte), pte_val(pte)); 320 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 321 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 322 __func__, pte_val(old_pte), pte_val(pte)); 323 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 324 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 325 __func__, pte_val(old_pte), pte_val(pte)); 326 } 327 328 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 329 { 330 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 331 __sync_icache_dcache(pte); 332 333 /* 334 * If the PTE would provide user space access to the tags associated 335 * with it then ensure that the MTE tags are synchronised. Although 336 * pte_access_permitted() returns false for exec only mappings, they 337 * don't expose tags (instruction fetches don't check tags). 338 */ 339 if (system_supports_mte() && pte_access_permitted(pte, false) && 340 !pte_special(pte) && pte_tagged(pte)) 341 mte_sync_tags(pte, nr_pages); 342 } 343 344 static inline void set_ptes(struct mm_struct *mm, 345 unsigned long __always_unused addr, 346 pte_t *ptep, pte_t pte, unsigned int nr) 347 { 348 page_table_check_ptes_set(mm, ptep, pte, nr); 349 __sync_cache_and_tags(pte, nr); 350 351 for (;;) { 352 __check_safe_pte_update(mm, ptep, pte); 353 set_pte(ptep, pte); 354 if (--nr == 0) 355 break; 356 ptep++; 357 pte_val(pte) += PAGE_SIZE; 358 } 359 } 360 #define set_ptes set_ptes 361 362 /* 363 * Huge pte definitions. 364 */ 365 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 366 367 /* 368 * Hugetlb definitions. 369 */ 370 #define HUGE_MAX_HSTATE 4 371 #define HPAGE_SHIFT PMD_SHIFT 372 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 373 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 374 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 375 376 static inline pte_t pgd_pte(pgd_t pgd) 377 { 378 return __pte(pgd_val(pgd)); 379 } 380 381 static inline pte_t p4d_pte(p4d_t p4d) 382 { 383 return __pte(p4d_val(p4d)); 384 } 385 386 static inline pte_t pud_pte(pud_t pud) 387 { 388 return __pte(pud_val(pud)); 389 } 390 391 static inline pud_t pte_pud(pte_t pte) 392 { 393 return __pud(pte_val(pte)); 394 } 395 396 static inline pmd_t pud_pmd(pud_t pud) 397 { 398 return __pmd(pud_val(pud)); 399 } 400 401 static inline pte_t pmd_pte(pmd_t pmd) 402 { 403 return __pte(pmd_val(pmd)); 404 } 405 406 static inline pmd_t pte_pmd(pte_t pte) 407 { 408 return __pmd(pte_val(pte)); 409 } 410 411 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 412 { 413 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 414 } 415 416 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 417 { 418 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 419 } 420 421 static inline pte_t pte_swp_mkexclusive(pte_t pte) 422 { 423 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 424 } 425 426 static inline int pte_swp_exclusive(pte_t pte) 427 { 428 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 429 } 430 431 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 432 { 433 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 434 } 435 436 /* 437 * Select all bits except the pfn 438 */ 439 static inline pgprot_t pte_pgprot(pte_t pte) 440 { 441 unsigned long pfn = pte_pfn(pte); 442 443 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 444 } 445 446 #ifdef CONFIG_NUMA_BALANCING 447 /* 448 * See the comment in include/linux/pgtable.h 449 */ 450 static inline int pte_protnone(pte_t pte) 451 { 452 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 453 } 454 455 static inline int pmd_protnone(pmd_t pmd) 456 { 457 return pte_protnone(pmd_pte(pmd)); 458 } 459 #endif 460 461 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 462 463 static inline int pmd_present(pmd_t pmd) 464 { 465 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 466 } 467 468 /* 469 * THP definitions. 470 */ 471 472 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 473 static inline int pmd_trans_huge(pmd_t pmd) 474 { 475 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 476 } 477 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 478 479 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 480 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 481 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 482 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 483 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 484 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 485 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 486 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 487 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 488 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 489 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 490 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 491 492 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 493 { 494 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 495 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 496 497 return pmd; 498 } 499 500 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 501 502 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 503 504 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 505 506 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 507 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 508 #endif 509 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 510 { 511 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 512 } 513 514 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 515 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 516 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 517 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 518 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 519 520 #define pud_young(pud) pte_young(pud_pte(pud)) 521 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 522 #define pud_write(pud) pte_write(pud_pte(pud)) 523 524 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 525 526 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 527 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 528 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 529 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 530 531 static inline void __set_pte_at(struct mm_struct *mm, 532 unsigned long __always_unused addr, 533 pte_t *ptep, pte_t pte, unsigned int nr) 534 { 535 __sync_cache_and_tags(pte, nr); 536 __check_safe_pte_update(mm, ptep, pte); 537 set_pte(ptep, pte); 538 } 539 540 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 541 pmd_t *pmdp, pmd_t pmd) 542 { 543 page_table_check_pmd_set(mm, pmdp, pmd); 544 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 545 PMD_SIZE >> PAGE_SHIFT); 546 } 547 548 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 549 pud_t *pudp, pud_t pud) 550 { 551 page_table_check_pud_set(mm, pudp, pud); 552 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 553 PUD_SIZE >> PAGE_SHIFT); 554 } 555 556 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 557 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 558 559 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 560 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 561 562 #define __pgprot_modify(prot,mask,bits) \ 563 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 564 565 #define pgprot_nx(prot) \ 566 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 567 568 /* 569 * Mark the prot value as uncacheable and unbufferable. 570 */ 571 #define pgprot_noncached(prot) \ 572 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 573 #define pgprot_writecombine(prot) \ 574 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 575 #define pgprot_device(prot) \ 576 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 577 #define pgprot_tagged(prot) \ 578 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 579 #define pgprot_mhp pgprot_tagged 580 /* 581 * DMA allocations for non-coherent devices use what the Arm architecture calls 582 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 583 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 584 * is intended for MMIO and thus forbids speculation, preserves access size, 585 * requires strict alignment and can also force write responses to come from the 586 * endpoint. 587 */ 588 #define pgprot_dmacoherent(prot) \ 589 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 590 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 591 592 #define __HAVE_PHYS_MEM_ACCESS_PROT 593 struct file; 594 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 595 unsigned long size, pgprot_t vma_prot); 596 597 #define pmd_none(pmd) (!pmd_val(pmd)) 598 599 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 600 PMD_TYPE_TABLE) 601 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 602 PMD_TYPE_SECT) 603 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 604 #define pmd_bad(pmd) (!pmd_table(pmd)) 605 606 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 607 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 608 609 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 610 static inline bool pud_sect(pud_t pud) { return false; } 611 static inline bool pud_table(pud_t pud) { return true; } 612 #else 613 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 614 PUD_TYPE_SECT) 615 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 616 PUD_TYPE_TABLE) 617 #endif 618 619 extern pgd_t init_pg_dir[PTRS_PER_PGD]; 620 extern pgd_t init_pg_end[]; 621 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 622 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 623 extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 624 extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 625 626 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 627 628 static inline bool in_swapper_pgdir(void *addr) 629 { 630 return ((unsigned long)addr & PAGE_MASK) == 631 ((unsigned long)swapper_pg_dir & PAGE_MASK); 632 } 633 634 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 635 { 636 #ifdef __PAGETABLE_PMD_FOLDED 637 if (in_swapper_pgdir(pmdp)) { 638 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 639 return; 640 } 641 #endif /* __PAGETABLE_PMD_FOLDED */ 642 643 WRITE_ONCE(*pmdp, pmd); 644 645 if (pmd_valid(pmd)) { 646 dsb(ishst); 647 isb(); 648 } 649 } 650 651 static inline void pmd_clear(pmd_t *pmdp) 652 { 653 set_pmd(pmdp, __pmd(0)); 654 } 655 656 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 657 { 658 return __pmd_to_phys(pmd); 659 } 660 661 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 662 { 663 return (unsigned long)__va(pmd_page_paddr(pmd)); 664 } 665 666 /* Find an entry in the third-level page table. */ 667 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 668 669 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 670 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 671 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 672 673 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 674 675 /* use ONLY for statically allocated translation tables */ 676 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 677 678 /* 679 * Conversion functions: convert a page and protection to a page entry, 680 * and a page entry and page directory to the page they refer to. 681 */ 682 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 683 684 #if CONFIG_PGTABLE_LEVELS > 2 685 686 #define pmd_ERROR(e) \ 687 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 688 689 #define pud_none(pud) (!pud_val(pud)) 690 #define pud_bad(pud) (!pud_table(pud)) 691 #define pud_present(pud) pte_present(pud_pte(pud)) 692 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 693 #define pud_valid(pud) pte_valid(pud_pte(pud)) 694 #define pud_user(pud) pte_user(pud_pte(pud)) 695 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 696 697 static inline void set_pud(pud_t *pudp, pud_t pud) 698 { 699 #ifdef __PAGETABLE_PUD_FOLDED 700 if (in_swapper_pgdir(pudp)) { 701 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 702 return; 703 } 704 #endif /* __PAGETABLE_PUD_FOLDED */ 705 706 WRITE_ONCE(*pudp, pud); 707 708 if (pud_valid(pud)) { 709 dsb(ishst); 710 isb(); 711 } 712 } 713 714 static inline void pud_clear(pud_t *pudp) 715 { 716 set_pud(pudp, __pud(0)); 717 } 718 719 static inline phys_addr_t pud_page_paddr(pud_t pud) 720 { 721 return __pud_to_phys(pud); 722 } 723 724 static inline pmd_t *pud_pgtable(pud_t pud) 725 { 726 return (pmd_t *)__va(pud_page_paddr(pud)); 727 } 728 729 /* Find an entry in the second-level page table. */ 730 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 731 732 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 733 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 734 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 735 736 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 737 738 /* use ONLY for statically allocated translation tables */ 739 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 740 741 #else 742 743 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 744 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 745 746 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 747 #define pmd_set_fixmap(addr) NULL 748 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 749 #define pmd_clear_fixmap() 750 751 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 752 753 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 754 755 #if CONFIG_PGTABLE_LEVELS > 3 756 757 #define pud_ERROR(e) \ 758 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 759 760 #define p4d_none(p4d) (!p4d_val(p4d)) 761 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 762 #define p4d_present(p4d) (p4d_val(p4d)) 763 764 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 765 { 766 if (in_swapper_pgdir(p4dp)) { 767 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 768 return; 769 } 770 771 WRITE_ONCE(*p4dp, p4d); 772 dsb(ishst); 773 isb(); 774 } 775 776 static inline void p4d_clear(p4d_t *p4dp) 777 { 778 set_p4d(p4dp, __p4d(0)); 779 } 780 781 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 782 { 783 return __p4d_to_phys(p4d); 784 } 785 786 static inline pud_t *p4d_pgtable(p4d_t p4d) 787 { 788 return (pud_t *)__va(p4d_page_paddr(p4d)); 789 } 790 791 /* Find an entry in the first-level page table. */ 792 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 793 794 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 795 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 796 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 797 798 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 799 800 /* use ONLY for statically allocated translation tables */ 801 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 802 803 #else 804 805 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 806 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 807 808 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 809 #define pud_set_fixmap(addr) NULL 810 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 811 #define pud_clear_fixmap() 812 813 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 814 815 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 816 817 #define pgd_ERROR(e) \ 818 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 819 820 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 821 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 822 823 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 824 { 825 /* 826 * Normal and Normal-Tagged are two different memory types and indices 827 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 828 */ 829 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 830 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 831 PTE_ATTRINDX_MASK; 832 /* preserve the hardware dirty information */ 833 if (pte_hw_dirty(pte)) 834 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 835 836 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 837 /* 838 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 839 * dirtiness again. 840 */ 841 if (pte_sw_dirty(pte)) 842 pte = pte_mkdirty(pte); 843 return pte; 844 } 845 846 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 847 { 848 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 849 } 850 851 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 852 extern int ptep_set_access_flags(struct vm_area_struct *vma, 853 unsigned long address, pte_t *ptep, 854 pte_t entry, int dirty); 855 856 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 857 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 858 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 859 unsigned long address, pmd_t *pmdp, 860 pmd_t entry, int dirty) 861 { 862 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 863 } 864 865 static inline int pud_devmap(pud_t pud) 866 { 867 return 0; 868 } 869 870 static inline int pgd_devmap(pgd_t pgd) 871 { 872 return 0; 873 } 874 #endif 875 876 #ifdef CONFIG_PAGE_TABLE_CHECK 877 static inline bool pte_user_accessible_page(pte_t pte) 878 { 879 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 880 } 881 882 static inline bool pmd_user_accessible_page(pmd_t pmd) 883 { 884 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 885 } 886 887 static inline bool pud_user_accessible_page(pud_t pud) 888 { 889 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 890 } 891 #endif 892 893 /* 894 * Atomic pte/pmd modifications. 895 */ 896 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 897 static inline int __ptep_test_and_clear_young(pte_t *ptep) 898 { 899 pte_t old_pte, pte; 900 901 pte = READ_ONCE(*ptep); 902 do { 903 old_pte = pte; 904 pte = pte_mkold(pte); 905 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 906 pte_val(old_pte), pte_val(pte)); 907 } while (pte_val(pte) != pte_val(old_pte)); 908 909 return pte_young(pte); 910 } 911 912 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 913 unsigned long address, 914 pte_t *ptep) 915 { 916 return __ptep_test_and_clear_young(ptep); 917 } 918 919 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 920 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 921 unsigned long address, pte_t *ptep) 922 { 923 int young = ptep_test_and_clear_young(vma, address, ptep); 924 925 if (young) { 926 /* 927 * We can elide the trailing DSB here since the worst that can 928 * happen is that a CPU continues to use the young entry in its 929 * TLB and we mistakenly reclaim the associated page. The 930 * window for such an event is bounded by the next 931 * context-switch, which provides a DSB to complete the TLB 932 * invalidation. 933 */ 934 flush_tlb_page_nosync(vma, address); 935 } 936 937 return young; 938 } 939 940 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 941 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 942 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 943 unsigned long address, 944 pmd_t *pmdp) 945 { 946 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 947 } 948 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 949 950 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 951 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 952 unsigned long address, pte_t *ptep) 953 { 954 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 955 956 page_table_check_pte_clear(mm, pte); 957 958 return pte; 959 } 960 961 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 962 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 963 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 964 unsigned long address, pmd_t *pmdp) 965 { 966 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 967 968 page_table_check_pmd_clear(mm, pmd); 969 970 return pmd; 971 } 972 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 973 974 /* 975 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 976 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 977 */ 978 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 979 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 980 { 981 pte_t old_pte, pte; 982 983 pte = READ_ONCE(*ptep); 984 do { 985 old_pte = pte; 986 pte = pte_wrprotect(pte); 987 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 988 pte_val(old_pte), pte_val(pte)); 989 } while (pte_val(pte) != pte_val(old_pte)); 990 } 991 992 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 993 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 994 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 995 unsigned long address, pmd_t *pmdp) 996 { 997 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 998 } 999 1000 #define pmdp_establish pmdp_establish 1001 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1002 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1003 { 1004 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1005 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1006 } 1007 #endif 1008 1009 /* 1010 * Encode and decode a swap entry: 1011 * bits 0-1: present (must be zero) 1012 * bits 2: remember PG_anon_exclusive 1013 * bits 3-7: swap type 1014 * bits 8-57: swap offset 1015 * bit 58: PTE_PROT_NONE (must be zero) 1016 */ 1017 #define __SWP_TYPE_SHIFT 3 1018 #define __SWP_TYPE_BITS 5 1019 #define __SWP_OFFSET_BITS 50 1020 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1021 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1022 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1023 1024 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1025 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1026 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1027 1028 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1029 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1030 1031 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1032 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1033 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1034 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1035 1036 /* 1037 * Ensure that there are not more swap files than can be encoded in the kernel 1038 * PTEs. 1039 */ 1040 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1041 1042 #ifdef CONFIG_ARM64_MTE 1043 1044 #define __HAVE_ARCH_PREPARE_TO_SWAP 1045 static inline int arch_prepare_to_swap(struct page *page) 1046 { 1047 if (system_supports_mte()) 1048 return mte_save_tags(page); 1049 return 0; 1050 } 1051 1052 #define __HAVE_ARCH_SWAP_INVALIDATE 1053 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1054 { 1055 if (system_supports_mte()) 1056 mte_invalidate_tags(type, offset); 1057 } 1058 1059 static inline void arch_swap_invalidate_area(int type) 1060 { 1061 if (system_supports_mte()) 1062 mte_invalidate_tags_area(type); 1063 } 1064 1065 #define __HAVE_ARCH_SWAP_RESTORE 1066 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1067 { 1068 if (system_supports_mte()) 1069 mte_restore_tags(entry, &folio->page); 1070 } 1071 1072 #endif /* CONFIG_ARM64_MTE */ 1073 1074 /* 1075 * On AArch64, the cache coherency is handled via the set_pte_at() function. 1076 */ 1077 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1078 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1079 unsigned int nr) 1080 { 1081 /* 1082 * We don't do anything here, so there's a very small chance of 1083 * us retaking a user fault which we just fixed up. The alternative 1084 * is doing a dsb(ishst), but that penalises the fastpath. 1085 */ 1086 } 1087 1088 #define update_mmu_cache(vma, addr, ptep) \ 1089 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1090 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1091 1092 #ifdef CONFIG_ARM64_PA_BITS_52 1093 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1094 #else 1095 #define phys_to_ttbr(addr) (addr) 1096 #endif 1097 1098 /* 1099 * On arm64 without hardware Access Flag, copying from user will fail because 1100 * the pte is old and cannot be marked young. So we always end up with zeroed 1101 * page after fork() + CoW for pfn mappings. We don't always have a 1102 * hardware-managed access flag on arm64. 1103 */ 1104 #define arch_has_hw_pte_young cpu_has_hw_af 1105 1106 /* 1107 * Experimentally, it's cheap to set the access flag in hardware and we 1108 * benefit from prefaulting mappings as 'old' to start with. 1109 */ 1110 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1111 1112 static inline bool pud_sect_supported(void) 1113 { 1114 return PAGE_SIZE == SZ_4K; 1115 } 1116 1117 1118 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1119 #define ptep_modify_prot_start ptep_modify_prot_start 1120 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1121 unsigned long addr, pte_t *ptep); 1122 1123 #define ptep_modify_prot_commit ptep_modify_prot_commit 1124 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1125 unsigned long addr, pte_t *ptep, 1126 pte_t old_pte, pte_t new_pte); 1127 #endif /* !__ASSEMBLY__ */ 1128 1129 #endif /* __ASM_PGTABLE_H */ 1130