1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * Outside of a few very special situations (e.g. hibernation), we always 55 * use broadcast TLB invalidation instructions, therefore a spurious page 56 * fault on one CPU which has been handled concurrently by another CPU 57 * does not need to perform additional invalidation. 58 */ 59 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 60 61 /* 62 * ZERO_PAGE is a global shared page that is always zero: used 63 * for zero-mapped memory areas etc.. 64 */ 65 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 66 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 70 71 #ifdef CONFIG_ARM64_PA_BITS_52 72 static inline phys_addr_t __pte_to_phys(pte_t pte) 73 { 74 pte_val(pte) &= ~PTE_MAYBE_SHARED; 75 return (pte_val(pte) & PTE_ADDR_LOW) | 76 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 77 } 78 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 79 { 80 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 81 } 82 #else 83 static inline phys_addr_t __pte_to_phys(pte_t pte) 84 { 85 return pte_val(pte) & PTE_ADDR_LOW; 86 } 87 88 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 89 { 90 return phys; 91 } 92 #endif 93 94 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 95 #define pfn_pte(pfn,prot) \ 96 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 97 98 #define pte_none(pte) (!pte_val(pte)) 99 #define __pte_clear(mm, addr, ptep) \ 100 __set_pte(ptep, __pte(0)) 101 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 102 103 /* 104 * The following only work if pte_present(). Undefined behaviour otherwise. 105 */ 106 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 107 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 108 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 109 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 110 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 111 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 112 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 113 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 114 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 115 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 116 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 117 118 #define pte_cont_addr_end(addr, end) \ 119 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 121 }) 122 123 #define pmd_cont_addr_end(addr, end) \ 124 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 125 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 126 }) 127 128 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 129 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 130 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 131 132 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 133 #define pte_present_invalid(pte) \ 134 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 135 /* 136 * Execute-only user mappings do not have the PTE_USER bit set. All valid 137 * kernel mappings have the PTE_UXN bit set. 138 */ 139 #define pte_valid_not_user(pte) \ 140 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 141 /* 142 * Returns true if the pte is valid and has the contiguous bit set. 143 */ 144 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 145 /* 146 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 147 * so that we don't erroneously return false for pages that have been 148 * remapped as PROT_NONE but are yet to be flushed from the TLB. 149 * Note that we can't make any assumptions based on the state of the access 150 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 151 * TLB. 152 */ 153 #define pte_accessible(mm, pte) \ 154 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 155 156 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 157 { 158 u64 por; 159 160 if (!system_supports_poe()) 161 return true; 162 163 por = read_sysreg_s(SYS_POR_EL0); 164 165 if (write) 166 return por_elx_allows_write(por, pkey); 167 168 if (execute) 169 return por_elx_allows_exec(por, pkey); 170 171 return por_elx_allows_read(por, pkey); 172 } 173 174 /* 175 * p??_access_permitted() is true for valid user mappings (PTE_USER 176 * bit set, subject to the write permission check). For execute-only 177 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 178 * not set) must return false. PROT_NONE mappings do not have the 179 * PTE_VALID bit set. 180 */ 181 #define pte_access_permitted_no_overlay(pte, write) \ 182 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 183 #define pte_access_permitted(pte, write) \ 184 (pte_access_permitted_no_overlay(pte, write) && \ 185 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 186 #define pmd_access_permitted(pmd, write) \ 187 (pte_access_permitted(pmd_pte(pmd), (write))) 188 #define pud_access_permitted(pud, write) \ 189 (pte_access_permitted(pud_pte(pud), (write))) 190 191 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 192 { 193 pte_val(pte) &= ~pgprot_val(prot); 194 return pte; 195 } 196 197 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 198 { 199 pte_val(pte) |= pgprot_val(prot); 200 return pte; 201 } 202 203 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 204 { 205 pmd_val(pmd) &= ~pgprot_val(prot); 206 return pmd; 207 } 208 209 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 210 { 211 pmd_val(pmd) |= pgprot_val(prot); 212 return pmd; 213 } 214 215 static inline pte_t pte_mkwrite_novma(pte_t pte) 216 { 217 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 218 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 219 return pte; 220 } 221 222 static inline pte_t pte_mkclean(pte_t pte) 223 { 224 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 225 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 226 227 return pte; 228 } 229 230 static inline pte_t pte_mkdirty(pte_t pte) 231 { 232 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 233 234 if (pte_write(pte)) 235 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 236 237 return pte; 238 } 239 240 static inline pte_t pte_wrprotect(pte_t pte) 241 { 242 /* 243 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 244 * clear), set the PTE_DIRTY bit. 245 */ 246 if (pte_hw_dirty(pte)) 247 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 248 249 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 250 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 251 return pte; 252 } 253 254 static inline pte_t pte_mkold(pte_t pte) 255 { 256 return clear_pte_bit(pte, __pgprot(PTE_AF)); 257 } 258 259 static inline pte_t pte_mkyoung(pte_t pte) 260 { 261 return set_pte_bit(pte, __pgprot(PTE_AF)); 262 } 263 264 static inline pte_t pte_mkspecial(pte_t pte) 265 { 266 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 267 } 268 269 static inline pte_t pte_mkcont(pte_t pte) 270 { 271 return set_pte_bit(pte, __pgprot(PTE_CONT)); 272 } 273 274 static inline pte_t pte_mknoncont(pte_t pte) 275 { 276 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 277 } 278 279 static inline pte_t pte_mkvalid(pte_t pte) 280 { 281 return set_pte_bit(pte, __pgprot(PTE_VALID)); 282 } 283 284 static inline pte_t pte_mkinvalid(pte_t pte) 285 { 286 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 287 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 288 return pte; 289 } 290 291 static inline pmd_t pmd_mkcont(pmd_t pmd) 292 { 293 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 294 } 295 296 static inline pte_t pte_mkdevmap(pte_t pte) 297 { 298 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 299 } 300 301 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 302 static inline int pte_uffd_wp(pte_t pte) 303 { 304 return !!(pte_val(pte) & PTE_UFFD_WP); 305 } 306 307 static inline pte_t pte_mkuffd_wp(pte_t pte) 308 { 309 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 310 } 311 312 static inline pte_t pte_clear_uffd_wp(pte_t pte) 313 { 314 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 315 } 316 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 317 318 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 319 { 320 WRITE_ONCE(*ptep, pte); 321 } 322 323 static inline void __set_pte(pte_t *ptep, pte_t pte) 324 { 325 __set_pte_nosync(ptep, pte); 326 327 /* 328 * Only if the new pte is valid and kernel, otherwise TLB maintenance 329 * or update_mmu_cache() have the necessary barriers. 330 */ 331 if (pte_valid_not_user(pte)) { 332 dsb(ishst); 333 isb(); 334 } 335 } 336 337 static inline pte_t __ptep_get(pte_t *ptep) 338 { 339 return READ_ONCE(*ptep); 340 } 341 342 extern void __sync_icache_dcache(pte_t pteval); 343 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 344 345 /* 346 * PTE bits configuration in the presence of hardware Dirty Bit Management 347 * (PTE_WRITE == PTE_DBM): 348 * 349 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 350 * 0 0 | 1 0 0 351 * 0 1 | 1 1 0 352 * 1 0 | 1 0 1 353 * 1 1 | 0 1 x 354 * 355 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 356 * the page fault mechanism. Checking the dirty status of a pte becomes: 357 * 358 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 359 */ 360 361 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 362 pte_t pte) 363 { 364 pte_t old_pte; 365 366 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 367 return; 368 369 old_pte = __ptep_get(ptep); 370 371 if (!pte_valid(old_pte) || !pte_valid(pte)) 372 return; 373 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 374 return; 375 376 /* 377 * Check for potential race with hardware updates of the pte 378 * (__ptep_set_access_flags safely changes valid ptes without going 379 * through an invalid entry). 380 */ 381 VM_WARN_ONCE(!pte_young(pte), 382 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 383 __func__, pte_val(old_pte), pte_val(pte)); 384 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 385 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 386 __func__, pte_val(old_pte), pte_val(pte)); 387 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 388 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 389 __func__, pte_val(old_pte), pte_val(pte)); 390 } 391 392 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 393 { 394 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 395 __sync_icache_dcache(pte); 396 397 /* 398 * If the PTE would provide user space access to the tags associated 399 * with it then ensure that the MTE tags are synchronised. Although 400 * pte_access_permitted_no_overlay() returns false for exec only 401 * mappings, they don't expose tags (instruction fetches don't check 402 * tags). 403 */ 404 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 405 !pte_special(pte) && pte_tagged(pte)) 406 mte_sync_tags(pte, nr_pages); 407 } 408 409 /* 410 * Select all bits except the pfn 411 */ 412 #define pte_pgprot pte_pgprot 413 static inline pgprot_t pte_pgprot(pte_t pte) 414 { 415 unsigned long pfn = pte_pfn(pte); 416 417 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 418 } 419 420 #define pte_advance_pfn pte_advance_pfn 421 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 422 { 423 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 424 } 425 426 static inline void __set_ptes(struct mm_struct *mm, 427 unsigned long __always_unused addr, 428 pte_t *ptep, pte_t pte, unsigned int nr) 429 { 430 page_table_check_ptes_set(mm, ptep, pte, nr); 431 __sync_cache_and_tags(pte, nr); 432 433 for (;;) { 434 __check_safe_pte_update(mm, ptep, pte); 435 __set_pte(ptep, pte); 436 if (--nr == 0) 437 break; 438 ptep++; 439 pte = pte_advance_pfn(pte, 1); 440 } 441 } 442 443 /* 444 * Hugetlb definitions. 445 */ 446 #define HUGE_MAX_HSTATE 4 447 #define HPAGE_SHIFT PMD_SHIFT 448 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 449 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 450 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 451 452 static inline pte_t pgd_pte(pgd_t pgd) 453 { 454 return __pte(pgd_val(pgd)); 455 } 456 457 static inline pte_t p4d_pte(p4d_t p4d) 458 { 459 return __pte(p4d_val(p4d)); 460 } 461 462 static inline pte_t pud_pte(pud_t pud) 463 { 464 return __pte(pud_val(pud)); 465 } 466 467 static inline pud_t pte_pud(pte_t pte) 468 { 469 return __pud(pte_val(pte)); 470 } 471 472 static inline pmd_t pud_pmd(pud_t pud) 473 { 474 return __pmd(pud_val(pud)); 475 } 476 477 static inline pte_t pmd_pte(pmd_t pmd) 478 { 479 return __pte(pmd_val(pmd)); 480 } 481 482 static inline pmd_t pte_pmd(pte_t pte) 483 { 484 return __pmd(pte_val(pte)); 485 } 486 487 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 488 { 489 return __pgprot((pgprot_val(prot) & ~PUD_TYPE_MASK) | PUD_TYPE_SECT); 490 } 491 492 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 493 { 494 return __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); 495 } 496 497 static inline pte_t pte_swp_mkexclusive(pte_t pte) 498 { 499 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 500 } 501 502 static inline int pte_swp_exclusive(pte_t pte) 503 { 504 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 505 } 506 507 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 508 { 509 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 510 } 511 512 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 513 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 514 { 515 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 516 } 517 518 static inline int pte_swp_uffd_wp(pte_t pte) 519 { 520 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 521 } 522 523 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 524 { 525 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 526 } 527 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 528 529 #ifdef CONFIG_NUMA_BALANCING 530 /* 531 * See the comment in include/linux/pgtable.h 532 */ 533 static inline int pte_protnone(pte_t pte) 534 { 535 /* 536 * pte_present_invalid() tells us that the pte is invalid from HW 537 * perspective but present from SW perspective, so the fields are to be 538 * interpretted as per the HW layout. The second 2 checks are the unique 539 * encoding that we use for PROT_NONE. It is insufficient to only use 540 * the first check because we share the same encoding scheme with pmds 541 * which support pmd_mkinvalid(), so can be present-invalid without 542 * being PROT_NONE. 543 */ 544 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 545 } 546 547 static inline int pmd_protnone(pmd_t pmd) 548 { 549 return pte_protnone(pmd_pte(pmd)); 550 } 551 #endif 552 553 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 554 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 555 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 556 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 557 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 558 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 559 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 560 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 561 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 562 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 563 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 564 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 565 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 566 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 567 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 568 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 569 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 570 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 571 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 572 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 573 #define pmd_swp_clear_uffd_wp(pmd) \ 574 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 575 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 576 577 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 578 579 static inline pmd_t pmd_mkhuge(pmd_t pmd) 580 { 581 /* 582 * It's possible that the pmd is present-invalid on entry 583 * and in that case it needs to remain present-invalid on 584 * exit. So ensure the VALID bit does not get modified. 585 */ 586 pmdval_t mask = PMD_TYPE_MASK & ~PTE_VALID; 587 pmdval_t val = PMD_TYPE_SECT & ~PTE_VALID; 588 589 return __pmd((pmd_val(pmd) & ~mask) | val); 590 } 591 592 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 593 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 594 #endif 595 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 596 { 597 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 598 } 599 600 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 601 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 602 static inline pmd_t pmd_mkspecial(pmd_t pmd) 603 { 604 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 605 } 606 #endif 607 608 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 609 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 610 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 611 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 612 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 613 614 #define pud_young(pud) pte_young(pud_pte(pud)) 615 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 616 #define pud_write(pud) pte_write(pud_pte(pud)) 617 618 static inline pud_t pud_mkhuge(pud_t pud) 619 { 620 /* 621 * It's possible that the pud is present-invalid on entry 622 * and in that case it needs to remain present-invalid on 623 * exit. So ensure the VALID bit does not get modified. 624 */ 625 pudval_t mask = PUD_TYPE_MASK & ~PTE_VALID; 626 pudval_t val = PUD_TYPE_SECT & ~PTE_VALID; 627 628 return __pud((pud_val(pud) & ~mask) | val); 629 } 630 631 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 632 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 633 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 634 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 635 636 #ifdef CONFIG_ARCH_SUPPORTS_PUD_PFNMAP 637 #define pud_special(pte) pte_special(pud_pte(pud)) 638 #define pud_mkspecial(pte) pte_pud(pte_mkspecial(pud_pte(pud))) 639 #endif 640 641 #define pmd_pgprot pmd_pgprot 642 static inline pgprot_t pmd_pgprot(pmd_t pmd) 643 { 644 unsigned long pfn = pmd_pfn(pmd); 645 646 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 647 } 648 649 #define pud_pgprot pud_pgprot 650 static inline pgprot_t pud_pgprot(pud_t pud) 651 { 652 unsigned long pfn = pud_pfn(pud); 653 654 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 655 } 656 657 static inline void __set_pte_at(struct mm_struct *mm, 658 unsigned long __always_unused addr, 659 pte_t *ptep, pte_t pte, unsigned int nr) 660 { 661 __sync_cache_and_tags(pte, nr); 662 __check_safe_pte_update(mm, ptep, pte); 663 __set_pte(ptep, pte); 664 } 665 666 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 667 pmd_t *pmdp, pmd_t pmd) 668 { 669 page_table_check_pmd_set(mm, pmdp, pmd); 670 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 671 PMD_SIZE >> PAGE_SHIFT); 672 } 673 674 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 675 pud_t *pudp, pud_t pud) 676 { 677 page_table_check_pud_set(mm, pudp, pud); 678 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 679 PUD_SIZE >> PAGE_SHIFT); 680 } 681 682 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 683 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 684 685 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 686 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 687 688 #define __pgprot_modify(prot,mask,bits) \ 689 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 690 691 #define pgprot_nx(prot) \ 692 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 693 694 #define pgprot_decrypted(prot) \ 695 __pgprot_modify(prot, PROT_NS_SHARED, PROT_NS_SHARED) 696 #define pgprot_encrypted(prot) \ 697 __pgprot_modify(prot, PROT_NS_SHARED, 0) 698 699 /* 700 * Mark the prot value as uncacheable and unbufferable. 701 */ 702 #define pgprot_noncached(prot) \ 703 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 704 #define pgprot_writecombine(prot) \ 705 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 706 #define pgprot_device(prot) \ 707 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 708 #define pgprot_tagged(prot) \ 709 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 710 #define pgprot_mhp pgprot_tagged 711 /* 712 * DMA allocations for non-coherent devices use what the Arm architecture calls 713 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 714 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 715 * is intended for MMIO and thus forbids speculation, preserves access size, 716 * requires strict alignment and can also force write responses to come from the 717 * endpoint. 718 */ 719 #define pgprot_dmacoherent(prot) \ 720 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 721 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 722 723 #define __HAVE_PHYS_MEM_ACCESS_PROT 724 struct file; 725 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 726 unsigned long size, pgprot_t vma_prot); 727 728 #define pmd_none(pmd) (!pmd_val(pmd)) 729 730 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 731 PMD_TYPE_TABLE) 732 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 733 PMD_TYPE_SECT) 734 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 735 #define pmd_bad(pmd) (!pmd_table(pmd)) 736 737 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 738 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 739 740 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 741 static inline int pmd_trans_huge(pmd_t pmd) 742 { 743 /* 744 * If pmd is present-invalid, pmd_table() won't detect it 745 * as a table, so force the valid bit for the comparison. 746 */ 747 return pmd_val(pmd) && pmd_present(pmd) && 748 !pmd_table(__pmd(pmd_val(pmd) | PTE_VALID)); 749 } 750 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 751 752 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 753 static inline bool pud_sect(pud_t pud) { return false; } 754 static inline bool pud_table(pud_t pud) { return true; } 755 #else 756 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 757 PUD_TYPE_SECT) 758 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 759 PUD_TYPE_TABLE) 760 #endif 761 762 extern pgd_t init_pg_dir[]; 763 extern pgd_t init_pg_end[]; 764 extern pgd_t swapper_pg_dir[]; 765 extern pgd_t idmap_pg_dir[]; 766 extern pgd_t tramp_pg_dir[]; 767 extern pgd_t reserved_pg_dir[]; 768 769 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 770 771 static inline bool in_swapper_pgdir(void *addr) 772 { 773 return ((unsigned long)addr & PAGE_MASK) == 774 ((unsigned long)swapper_pg_dir & PAGE_MASK); 775 } 776 777 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 778 { 779 #ifdef __PAGETABLE_PMD_FOLDED 780 if (in_swapper_pgdir(pmdp)) { 781 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 782 return; 783 } 784 #endif /* __PAGETABLE_PMD_FOLDED */ 785 786 WRITE_ONCE(*pmdp, pmd); 787 788 if (pmd_valid(pmd)) { 789 dsb(ishst); 790 isb(); 791 } 792 } 793 794 static inline void pmd_clear(pmd_t *pmdp) 795 { 796 set_pmd(pmdp, __pmd(0)); 797 } 798 799 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 800 { 801 return __pmd_to_phys(pmd); 802 } 803 804 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 805 { 806 return (unsigned long)__va(pmd_page_paddr(pmd)); 807 } 808 809 /* Find an entry in the third-level page table. */ 810 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 811 812 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 813 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 814 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 815 816 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 817 818 /* use ONLY for statically allocated translation tables */ 819 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 820 821 /* 822 * Conversion functions: convert a page and protection to a page entry, 823 * and a page entry and page directory to the page they refer to. 824 */ 825 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 826 827 #if CONFIG_PGTABLE_LEVELS > 2 828 829 #define pmd_ERROR(e) \ 830 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 831 832 #define pud_none(pud) (!pud_val(pud)) 833 #define pud_bad(pud) ((pud_val(pud) & PUD_TYPE_MASK) != \ 834 PUD_TYPE_TABLE) 835 #define pud_present(pud) pte_present(pud_pte(pud)) 836 #ifndef __PAGETABLE_PMD_FOLDED 837 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 838 #else 839 #define pud_leaf(pud) false 840 #endif 841 #define pud_valid(pud) pte_valid(pud_pte(pud)) 842 #define pud_user(pud) pte_user(pud_pte(pud)) 843 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 844 845 static inline bool pgtable_l4_enabled(void); 846 847 static inline void set_pud(pud_t *pudp, pud_t pud) 848 { 849 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 850 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 851 return; 852 } 853 854 WRITE_ONCE(*pudp, pud); 855 856 if (pud_valid(pud)) { 857 dsb(ishst); 858 isb(); 859 } 860 } 861 862 static inline void pud_clear(pud_t *pudp) 863 { 864 set_pud(pudp, __pud(0)); 865 } 866 867 static inline phys_addr_t pud_page_paddr(pud_t pud) 868 { 869 return __pud_to_phys(pud); 870 } 871 872 static inline pmd_t *pud_pgtable(pud_t pud) 873 { 874 return (pmd_t *)__va(pud_page_paddr(pud)); 875 } 876 877 /* Find an entry in the second-level page table. */ 878 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 879 880 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 881 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 882 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 883 884 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 885 886 /* use ONLY for statically allocated translation tables */ 887 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 888 889 #else 890 891 #define pud_valid(pud) false 892 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 893 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 894 895 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 896 #define pmd_set_fixmap(addr) NULL 897 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 898 #define pmd_clear_fixmap() 899 900 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 901 902 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 903 904 #if CONFIG_PGTABLE_LEVELS > 3 905 906 static __always_inline bool pgtable_l4_enabled(void) 907 { 908 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 909 return true; 910 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 911 return vabits_actual == VA_BITS; 912 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 913 } 914 915 static inline bool mm_pud_folded(const struct mm_struct *mm) 916 { 917 return !pgtable_l4_enabled(); 918 } 919 #define mm_pud_folded mm_pud_folded 920 921 #define pud_ERROR(e) \ 922 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 923 924 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 925 #define p4d_bad(p4d) (pgtable_l4_enabled() && \ 926 ((p4d_val(p4d) & P4D_TYPE_MASK) != \ 927 P4D_TYPE_TABLE)) 928 #define p4d_present(p4d) (!p4d_none(p4d)) 929 930 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 931 { 932 if (in_swapper_pgdir(p4dp)) { 933 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 934 return; 935 } 936 937 WRITE_ONCE(*p4dp, p4d); 938 dsb(ishst); 939 isb(); 940 } 941 942 static inline void p4d_clear(p4d_t *p4dp) 943 { 944 if (pgtable_l4_enabled()) 945 set_p4d(p4dp, __p4d(0)); 946 } 947 948 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 949 { 950 return __p4d_to_phys(p4d); 951 } 952 953 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 954 955 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 956 { 957 /* Ensure that 'p4dp' indexes a page table according to 'addr' */ 958 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D); 959 960 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 961 } 962 963 static inline pud_t *p4d_pgtable(p4d_t p4d) 964 { 965 return (pud_t *)__va(p4d_page_paddr(p4d)); 966 } 967 968 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 969 { 970 BUG_ON(!pgtable_l4_enabled()); 971 972 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 973 } 974 975 static inline 976 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 977 { 978 if (!pgtable_l4_enabled()) 979 return p4d_to_folded_pud(p4dp, addr); 980 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 981 } 982 #define pud_offset_lockless pud_offset_lockless 983 984 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 985 { 986 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 987 } 988 #define pud_offset pud_offset 989 990 static inline pud_t *pud_set_fixmap(unsigned long addr) 991 { 992 if (!pgtable_l4_enabled()) 993 return NULL; 994 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 995 } 996 997 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 998 { 999 if (!pgtable_l4_enabled()) 1000 return p4d_to_folded_pud(p4dp, addr); 1001 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 1002 } 1003 1004 static inline void pud_clear_fixmap(void) 1005 { 1006 if (pgtable_l4_enabled()) 1007 clear_fixmap(FIX_PUD); 1008 } 1009 1010 /* use ONLY for statically allocated translation tables */ 1011 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 1012 { 1013 if (!pgtable_l4_enabled()) 1014 return p4d_to_folded_pud(p4dp, addr); 1015 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 1016 } 1017 1018 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 1019 1020 #else 1021 1022 static inline bool pgtable_l4_enabled(void) { return false; } 1023 1024 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 1025 1026 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 1027 #define pud_set_fixmap(addr) NULL 1028 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 1029 #define pud_clear_fixmap() 1030 1031 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 1032 1033 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1034 1035 #if CONFIG_PGTABLE_LEVELS > 4 1036 1037 static __always_inline bool pgtable_l5_enabled(void) 1038 { 1039 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1040 return vabits_actual == VA_BITS; 1041 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1042 } 1043 1044 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1045 { 1046 return !pgtable_l5_enabled(); 1047 } 1048 #define mm_p4d_folded mm_p4d_folded 1049 1050 #define p4d_ERROR(e) \ 1051 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1052 1053 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1054 #define pgd_bad(pgd) (pgtable_l5_enabled() && \ 1055 ((pgd_val(pgd) & PGD_TYPE_MASK) != \ 1056 PGD_TYPE_TABLE)) 1057 #define pgd_present(pgd) (!pgd_none(pgd)) 1058 1059 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1060 { 1061 if (in_swapper_pgdir(pgdp)) { 1062 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1063 return; 1064 } 1065 1066 WRITE_ONCE(*pgdp, pgd); 1067 dsb(ishst); 1068 isb(); 1069 } 1070 1071 static inline void pgd_clear(pgd_t *pgdp) 1072 { 1073 if (pgtable_l5_enabled()) 1074 set_pgd(pgdp, __pgd(0)); 1075 } 1076 1077 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1078 { 1079 return __pgd_to_phys(pgd); 1080 } 1081 1082 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1083 1084 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1085 { 1086 /* Ensure that 'pgdp' indexes a page table according to 'addr' */ 1087 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD); 1088 1089 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1090 } 1091 1092 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1093 { 1094 BUG_ON(!pgtable_l5_enabled()); 1095 1096 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1097 } 1098 1099 static inline 1100 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1101 { 1102 if (!pgtable_l5_enabled()) 1103 return pgd_to_folded_p4d(pgdp, addr); 1104 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1105 } 1106 #define p4d_offset_lockless p4d_offset_lockless 1107 1108 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1109 { 1110 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1111 } 1112 1113 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1114 { 1115 if (!pgtable_l5_enabled()) 1116 return NULL; 1117 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1118 } 1119 1120 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1121 { 1122 if (!pgtable_l5_enabled()) 1123 return pgd_to_folded_p4d(pgdp, addr); 1124 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1125 } 1126 1127 static inline void p4d_clear_fixmap(void) 1128 { 1129 if (pgtable_l5_enabled()) 1130 clear_fixmap(FIX_P4D); 1131 } 1132 1133 /* use ONLY for statically allocated translation tables */ 1134 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1135 { 1136 if (!pgtable_l5_enabled()) 1137 return pgd_to_folded_p4d(pgdp, addr); 1138 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1139 } 1140 1141 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1142 1143 #else 1144 1145 static inline bool pgtable_l5_enabled(void) { return false; } 1146 1147 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1148 1149 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1150 #define p4d_set_fixmap(addr) NULL 1151 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1152 #define p4d_clear_fixmap() 1153 1154 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1155 1156 static inline 1157 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1158 { 1159 /* 1160 * With runtime folding of the pud, pud_offset_lockless() passes 1161 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1162 * will offset the pointer assuming that it points into 1163 * a page-table page. However, the fast GUP path passes us a 1164 * pgd_t allocated on the stack and so we must use the original 1165 * pointer in 'pgdp' to construct the p4d pointer instead of 1166 * using the generic p4d_offset_lockless() implementation. 1167 * 1168 * Note: reusing the original pointer means that we may 1169 * dereference the same (live) page-table entry multiple times. 1170 * This is safe because it is still only loaded once in the 1171 * context of each level and the CPU guarantees same-address 1172 * read-after-read ordering. 1173 */ 1174 return p4d_offset(pgdp, addr); 1175 } 1176 #define p4d_offset_lockless p4d_offset_lockless_folded 1177 1178 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1179 1180 #define pgd_ERROR(e) \ 1181 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1182 1183 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1184 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1185 1186 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1187 { 1188 /* 1189 * Normal and Normal-Tagged are two different memory types and indices 1190 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1191 */ 1192 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1193 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1194 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1195 1196 /* preserve the hardware dirty information */ 1197 if (pte_hw_dirty(pte)) 1198 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1199 1200 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1201 /* 1202 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1203 * dirtiness again. 1204 */ 1205 if (pte_sw_dirty(pte)) 1206 pte = pte_mkdirty(pte); 1207 return pte; 1208 } 1209 1210 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1211 { 1212 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1213 } 1214 1215 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1216 unsigned long address, pte_t *ptep, 1217 pte_t entry, int dirty); 1218 1219 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1220 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1221 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1222 unsigned long address, pmd_t *pmdp, 1223 pmd_t entry, int dirty) 1224 { 1225 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1226 pmd_pte(entry), dirty); 1227 } 1228 1229 static inline int pud_devmap(pud_t pud) 1230 { 1231 return 0; 1232 } 1233 1234 static inline int pgd_devmap(pgd_t pgd) 1235 { 1236 return 0; 1237 } 1238 #endif 1239 1240 #ifdef CONFIG_PAGE_TABLE_CHECK 1241 static inline bool pte_user_accessible_page(pte_t pte) 1242 { 1243 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1244 } 1245 1246 static inline bool pmd_user_accessible_page(pmd_t pmd) 1247 { 1248 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1249 } 1250 1251 static inline bool pud_user_accessible_page(pud_t pud) 1252 { 1253 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1254 } 1255 #endif 1256 1257 /* 1258 * Atomic pte/pmd modifications. 1259 */ 1260 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1261 unsigned long address, 1262 pte_t *ptep) 1263 { 1264 pte_t old_pte, pte; 1265 1266 pte = __ptep_get(ptep); 1267 do { 1268 old_pte = pte; 1269 pte = pte_mkold(pte); 1270 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1271 pte_val(old_pte), pte_val(pte)); 1272 } while (pte_val(pte) != pte_val(old_pte)); 1273 1274 return pte_young(pte); 1275 } 1276 1277 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1278 unsigned long address, pte_t *ptep) 1279 { 1280 int young = __ptep_test_and_clear_young(vma, address, ptep); 1281 1282 if (young) { 1283 /* 1284 * We can elide the trailing DSB here since the worst that can 1285 * happen is that a CPU continues to use the young entry in its 1286 * TLB and we mistakenly reclaim the associated page. The 1287 * window for such an event is bounded by the next 1288 * context-switch, which provides a DSB to complete the TLB 1289 * invalidation. 1290 */ 1291 flush_tlb_page_nosync(vma, address); 1292 } 1293 1294 return young; 1295 } 1296 1297 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 1298 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1299 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1300 unsigned long address, 1301 pmd_t *pmdp) 1302 { 1303 /* Operation applies to PMD table entry only if FEAT_HAFT is enabled */ 1304 VM_WARN_ON(pmd_table(READ_ONCE(*pmdp)) && !system_supports_haft()); 1305 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1306 } 1307 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 1308 1309 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1310 unsigned long address, pte_t *ptep) 1311 { 1312 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1313 1314 page_table_check_pte_clear(mm, pte); 1315 1316 return pte; 1317 } 1318 1319 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1320 pte_t *ptep, unsigned int nr, int full) 1321 { 1322 for (;;) { 1323 __ptep_get_and_clear(mm, addr, ptep); 1324 if (--nr == 0) 1325 break; 1326 ptep++; 1327 addr += PAGE_SIZE; 1328 } 1329 } 1330 1331 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1332 unsigned long addr, pte_t *ptep, 1333 unsigned int nr, int full) 1334 { 1335 pte_t pte, tmp_pte; 1336 1337 pte = __ptep_get_and_clear(mm, addr, ptep); 1338 while (--nr) { 1339 ptep++; 1340 addr += PAGE_SIZE; 1341 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1342 if (pte_dirty(tmp_pte)) 1343 pte = pte_mkdirty(pte); 1344 if (pte_young(tmp_pte)) 1345 pte = pte_mkyoung(pte); 1346 } 1347 return pte; 1348 } 1349 1350 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1351 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1352 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1353 unsigned long address, pmd_t *pmdp) 1354 { 1355 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1356 1357 page_table_check_pmd_clear(mm, pmd); 1358 1359 return pmd; 1360 } 1361 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1362 1363 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1364 unsigned long address, pte_t *ptep, 1365 pte_t pte) 1366 { 1367 pte_t old_pte; 1368 1369 do { 1370 old_pte = pte; 1371 pte = pte_wrprotect(pte); 1372 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1373 pte_val(old_pte), pte_val(pte)); 1374 } while (pte_val(pte) != pte_val(old_pte)); 1375 } 1376 1377 /* 1378 * __ptep_set_wrprotect - mark read-only while transferring potential hardware 1379 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1380 */ 1381 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1382 unsigned long address, pte_t *ptep) 1383 { 1384 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1385 } 1386 1387 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1388 pte_t *ptep, unsigned int nr) 1389 { 1390 unsigned int i; 1391 1392 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1393 __ptep_set_wrprotect(mm, address, ptep); 1394 } 1395 1396 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1397 unsigned long addr, pte_t *ptep, 1398 pte_t pte, cydp_t flags) 1399 { 1400 pte_t old_pte; 1401 1402 do { 1403 old_pte = pte; 1404 1405 if (flags & CYDP_CLEAR_YOUNG) 1406 pte = pte_mkold(pte); 1407 if (flags & CYDP_CLEAR_DIRTY) 1408 pte = pte_mkclean(pte); 1409 1410 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1411 pte_val(old_pte), pte_val(pte)); 1412 } while (pte_val(pte) != pte_val(old_pte)); 1413 } 1414 1415 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1416 unsigned long addr, pte_t *ptep, 1417 unsigned int nr, cydp_t flags) 1418 { 1419 pte_t pte; 1420 1421 for (;;) { 1422 pte = __ptep_get(ptep); 1423 1424 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1425 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1426 else 1427 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1428 1429 if (--nr == 0) 1430 break; 1431 ptep++; 1432 addr += PAGE_SIZE; 1433 } 1434 } 1435 1436 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1437 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1438 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1439 unsigned long address, pmd_t *pmdp) 1440 { 1441 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1442 } 1443 1444 #define pmdp_establish pmdp_establish 1445 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1446 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1447 { 1448 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1449 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1450 } 1451 #endif 1452 1453 /* 1454 * Encode and decode a swap entry: 1455 * bits 0-1: present (must be zero) 1456 * bits 2: remember PG_anon_exclusive 1457 * bit 3: remember uffd-wp state 1458 * bits 6-10: swap type 1459 * bit 11: PTE_PRESENT_INVALID (must be zero) 1460 * bits 12-61: swap offset 1461 */ 1462 #define __SWP_TYPE_SHIFT 6 1463 #define __SWP_TYPE_BITS 5 1464 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1465 #define __SWP_OFFSET_SHIFT 12 1466 #define __SWP_OFFSET_BITS 50 1467 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1468 1469 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1470 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1471 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1472 1473 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1474 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1475 1476 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1477 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1478 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1479 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1480 1481 /* 1482 * Ensure that there are not more swap files than can be encoded in the kernel 1483 * PTEs. 1484 */ 1485 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1486 1487 #ifdef CONFIG_ARM64_MTE 1488 1489 #define __HAVE_ARCH_PREPARE_TO_SWAP 1490 extern int arch_prepare_to_swap(struct folio *folio); 1491 1492 #define __HAVE_ARCH_SWAP_INVALIDATE 1493 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1494 { 1495 if (system_supports_mte()) 1496 mte_invalidate_tags(type, offset); 1497 } 1498 1499 static inline void arch_swap_invalidate_area(int type) 1500 { 1501 if (system_supports_mte()) 1502 mte_invalidate_tags_area(type); 1503 } 1504 1505 #define __HAVE_ARCH_SWAP_RESTORE 1506 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1507 1508 #endif /* CONFIG_ARM64_MTE */ 1509 1510 /* 1511 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1512 */ 1513 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1514 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1515 unsigned int nr) 1516 { 1517 /* 1518 * We don't do anything here, so there's a very small chance of 1519 * us retaking a user fault which we just fixed up. The alternative 1520 * is doing a dsb(ishst), but that penalises the fastpath. 1521 */ 1522 } 1523 1524 #define update_mmu_cache(vma, addr, ptep) \ 1525 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1526 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1527 1528 #ifdef CONFIG_ARM64_PA_BITS_52 1529 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1530 #else 1531 #define phys_to_ttbr(addr) (addr) 1532 #endif 1533 1534 /* 1535 * On arm64 without hardware Access Flag, copying from user will fail because 1536 * the pte is old and cannot be marked young. So we always end up with zeroed 1537 * page after fork() + CoW for pfn mappings. We don't always have a 1538 * hardware-managed access flag on arm64. 1539 */ 1540 #define arch_has_hw_pte_young cpu_has_hw_af 1541 1542 #ifdef CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG 1543 #define arch_has_hw_nonleaf_pmd_young system_supports_haft 1544 #endif 1545 1546 /* 1547 * Experimentally, it's cheap to set the access flag in hardware and we 1548 * benefit from prefaulting mappings as 'old' to start with. 1549 */ 1550 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1551 1552 static inline bool pud_sect_supported(void) 1553 { 1554 return PAGE_SIZE == SZ_4K; 1555 } 1556 1557 1558 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1559 #define ptep_modify_prot_start ptep_modify_prot_start 1560 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1561 unsigned long addr, pte_t *ptep); 1562 1563 #define ptep_modify_prot_commit ptep_modify_prot_commit 1564 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1565 unsigned long addr, pte_t *ptep, 1566 pte_t old_pte, pte_t new_pte); 1567 1568 #ifdef CONFIG_ARM64_CONTPTE 1569 1570 /* 1571 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1572 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1573 * a private implementation detail of the public ptep API (see below). 1574 */ 1575 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1576 pte_t *ptep, pte_t pte); 1577 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1578 pte_t *ptep, pte_t pte); 1579 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1580 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1581 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1582 pte_t *ptep, pte_t pte, unsigned int nr); 1583 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1584 pte_t *ptep, unsigned int nr, int full); 1585 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1586 unsigned long addr, pte_t *ptep, 1587 unsigned int nr, int full); 1588 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1589 unsigned long addr, pte_t *ptep); 1590 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1591 unsigned long addr, pte_t *ptep); 1592 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1593 pte_t *ptep, unsigned int nr); 1594 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1595 unsigned long addr, pte_t *ptep, 1596 pte_t entry, int dirty); 1597 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1598 unsigned long addr, pte_t *ptep, 1599 unsigned int nr, cydp_t flags); 1600 1601 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1602 unsigned long addr, pte_t *ptep, pte_t pte) 1603 { 1604 /* 1605 * Only bother trying if both the virtual and physical addresses are 1606 * aligned and correspond to the last entry in a contig range. The core 1607 * code mostly modifies ranges from low to high, so this is the likely 1608 * the last modification in the contig range, so a good time to fold. 1609 * We can't fold special mappings, because there is no associated folio. 1610 */ 1611 1612 const unsigned long contmask = CONT_PTES - 1; 1613 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1614 1615 if (unlikely(valign)) { 1616 bool palign = (pte_pfn(pte) & contmask) == contmask; 1617 1618 if (unlikely(palign && 1619 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1620 __contpte_try_fold(mm, addr, ptep, pte); 1621 } 1622 } 1623 1624 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1625 unsigned long addr, pte_t *ptep, pte_t pte) 1626 { 1627 if (unlikely(pte_valid_cont(pte))) 1628 __contpte_try_unfold(mm, addr, ptep, pte); 1629 } 1630 1631 #define pte_batch_hint pte_batch_hint 1632 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1633 { 1634 if (!pte_valid_cont(pte)) 1635 return 1; 1636 1637 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1638 } 1639 1640 /* 1641 * The below functions constitute the public API that arm64 presents to the 1642 * core-mm to manipulate PTE entries within their page tables (or at least this 1643 * is the subset of the API that arm64 needs to implement). These public 1644 * versions will automatically and transparently apply the contiguous bit where 1645 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1646 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1647 * private versions, which are prefixed with double underscore. All of these 1648 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1649 * held. Although the contiguous bit is considered private to the 1650 * implementation, it is deliberately allowed to leak through the getters (e.g. 1651 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1652 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1653 * its possible a pte will be passed to a setter with the contiguous bit set, so 1654 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1655 * setting it in the pgtable. 1656 */ 1657 1658 #define ptep_get ptep_get 1659 static inline pte_t ptep_get(pte_t *ptep) 1660 { 1661 pte_t pte = __ptep_get(ptep); 1662 1663 if (likely(!pte_valid_cont(pte))) 1664 return pte; 1665 1666 return contpte_ptep_get(ptep, pte); 1667 } 1668 1669 #define ptep_get_lockless ptep_get_lockless 1670 static inline pte_t ptep_get_lockless(pte_t *ptep) 1671 { 1672 pte_t pte = __ptep_get(ptep); 1673 1674 if (likely(!pte_valid_cont(pte))) 1675 return pte; 1676 1677 return contpte_ptep_get_lockless(ptep); 1678 } 1679 1680 static inline void set_pte(pte_t *ptep, pte_t pte) 1681 { 1682 /* 1683 * We don't have the mm or vaddr so cannot unfold contig entries (since 1684 * it requires tlb maintenance). set_pte() is not used in core code, so 1685 * this should never even be called. Regardless do our best to service 1686 * any call and emit a warning if there is any attempt to set a pte on 1687 * top of an existing contig range. 1688 */ 1689 pte_t orig_pte = __ptep_get(ptep); 1690 1691 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1692 __set_pte(ptep, pte_mknoncont(pte)); 1693 } 1694 1695 #define set_ptes set_ptes 1696 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1697 pte_t *ptep, pte_t pte, unsigned int nr) 1698 { 1699 pte = pte_mknoncont(pte); 1700 1701 if (likely(nr == 1)) { 1702 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1703 __set_ptes(mm, addr, ptep, pte, 1); 1704 contpte_try_fold(mm, addr, ptep, pte); 1705 } else { 1706 contpte_set_ptes(mm, addr, ptep, pte, nr); 1707 } 1708 } 1709 1710 static inline void pte_clear(struct mm_struct *mm, 1711 unsigned long addr, pte_t *ptep) 1712 { 1713 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1714 __pte_clear(mm, addr, ptep); 1715 } 1716 1717 #define clear_full_ptes clear_full_ptes 1718 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1719 pte_t *ptep, unsigned int nr, int full) 1720 { 1721 if (likely(nr == 1)) { 1722 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1723 __clear_full_ptes(mm, addr, ptep, nr, full); 1724 } else { 1725 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1726 } 1727 } 1728 1729 #define get_and_clear_full_ptes get_and_clear_full_ptes 1730 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1731 unsigned long addr, pte_t *ptep, 1732 unsigned int nr, int full) 1733 { 1734 pte_t pte; 1735 1736 if (likely(nr == 1)) { 1737 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1738 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1739 } else { 1740 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1741 } 1742 1743 return pte; 1744 } 1745 1746 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1747 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1748 unsigned long addr, pte_t *ptep) 1749 { 1750 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1751 return __ptep_get_and_clear(mm, addr, ptep); 1752 } 1753 1754 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1755 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1756 unsigned long addr, pte_t *ptep) 1757 { 1758 pte_t orig_pte = __ptep_get(ptep); 1759 1760 if (likely(!pte_valid_cont(orig_pte))) 1761 return __ptep_test_and_clear_young(vma, addr, ptep); 1762 1763 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1764 } 1765 1766 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1767 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1768 unsigned long addr, pte_t *ptep) 1769 { 1770 pte_t orig_pte = __ptep_get(ptep); 1771 1772 if (likely(!pte_valid_cont(orig_pte))) 1773 return __ptep_clear_flush_young(vma, addr, ptep); 1774 1775 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1776 } 1777 1778 #define wrprotect_ptes wrprotect_ptes 1779 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1780 unsigned long addr, pte_t *ptep, unsigned int nr) 1781 { 1782 if (likely(nr == 1)) { 1783 /* 1784 * Optimization: wrprotect_ptes() can only be called for present 1785 * ptes so we only need to check contig bit as condition for 1786 * unfold, and we can remove the contig bit from the pte we read 1787 * to avoid re-reading. This speeds up fork() which is sensitive 1788 * for order-0 folios. Equivalent to contpte_try_unfold(). 1789 */ 1790 pte_t orig_pte = __ptep_get(ptep); 1791 1792 if (unlikely(pte_cont(orig_pte))) { 1793 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1794 orig_pte = pte_mknoncont(orig_pte); 1795 } 1796 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1797 } else { 1798 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1799 } 1800 } 1801 1802 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1803 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1804 unsigned long addr, pte_t *ptep) 1805 { 1806 wrprotect_ptes(mm, addr, ptep, 1); 1807 } 1808 1809 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1810 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1811 unsigned long addr, pte_t *ptep, 1812 pte_t entry, int dirty) 1813 { 1814 pte_t orig_pte = __ptep_get(ptep); 1815 1816 entry = pte_mknoncont(entry); 1817 1818 if (likely(!pte_valid_cont(orig_pte))) 1819 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1820 1821 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1822 } 1823 1824 #define clear_young_dirty_ptes clear_young_dirty_ptes 1825 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1826 unsigned long addr, pte_t *ptep, 1827 unsigned int nr, cydp_t flags) 1828 { 1829 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1830 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1831 else 1832 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1833 } 1834 1835 #else /* CONFIG_ARM64_CONTPTE */ 1836 1837 #define ptep_get __ptep_get 1838 #define set_pte __set_pte 1839 #define set_ptes __set_ptes 1840 #define pte_clear __pte_clear 1841 #define clear_full_ptes __clear_full_ptes 1842 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1843 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1844 #define ptep_get_and_clear __ptep_get_and_clear 1845 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1846 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1847 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1848 #define ptep_clear_flush_young __ptep_clear_flush_young 1849 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1850 #define ptep_set_wrprotect __ptep_set_wrprotect 1851 #define wrprotect_ptes __wrprotect_ptes 1852 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1853 #define ptep_set_access_flags __ptep_set_access_flags 1854 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1855 1856 #endif /* CONFIG_ARM64_CONTPTE */ 1857 1858 #endif /* !__ASSEMBLY__ */ 1859 1860 #endif /* __ASM_PGTABLE_H */ 1861