1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLER__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 static inline void emit_pte_barriers(void) 44 { 45 /* 46 * These barriers are emitted under certain conditions after a pte entry 47 * was modified (see e.g. __set_pte_complete()). The dsb makes the store 48 * visible to the table walker. The isb ensures that any previous 49 * speculative "invalid translation" marker that is in the CPU's 50 * pipeline gets cleared, so that any access to that address after 51 * setting the pte to valid won't cause a spurious fault. If the thread 52 * gets preempted after storing to the pgtable but before emitting these 53 * barriers, __switch_to() emits a dsb which ensure the walker gets to 54 * see the store. There is no guarantee of an isb being issued though. 55 * This is safe because it will still get issued (albeit on a 56 * potentially different CPU) when the thread starts running again, 57 * before any access to the address. 58 */ 59 dsb(ishst); 60 isb(); 61 } 62 63 static inline void queue_pte_barriers(void) 64 { 65 if (is_lazy_mmu_mode_active()) { 66 /* Avoid the atomic op if already set. */ 67 if (!test_thread_flag(TIF_LAZY_MMU_PENDING)) 68 set_thread_flag(TIF_LAZY_MMU_PENDING); 69 } else { 70 emit_pte_barriers(); 71 } 72 } 73 74 static inline void arch_enter_lazy_mmu_mode(void) {} 75 76 static inline void arch_flush_lazy_mmu_mode(void) 77 { 78 if (test_and_clear_thread_flag(TIF_LAZY_MMU_PENDING)) 79 emit_pte_barriers(); 80 } 81 82 static inline void arch_leave_lazy_mmu_mode(void) 83 { 84 arch_flush_lazy_mmu_mode(); 85 } 86 87 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 88 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 89 90 /* Set stride and tlb_level in flush_*_tlb_range */ 91 #define flush_pmd_tlb_range(vma, addr, end) \ 92 __flush_tlb_range(vma, addr, end, PMD_SIZE, 2, TLBF_NONE) 93 #define flush_pud_tlb_range(vma, addr, end) \ 94 __flush_tlb_range(vma, addr, end, PUD_SIZE, 1, TLBF_NONE) 95 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 96 97 /* 98 * We use local TLB invalidation instruction when reusing page in 99 * write protection fault handler to avoid TLBI broadcast in the hot 100 * path. This will cause spurious page faults if stale read-only TLB 101 * entries exist. 102 */ 103 #define flush_tlb_fix_spurious_fault(vma, address, ptep) \ 104 __flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY) 105 106 #define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp) \ 107 __flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2, \ 108 TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE) 109 110 #define pte_ERROR(e) \ 111 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 112 113 #ifdef CONFIG_ARM64_PA_BITS_52 114 static inline phys_addr_t __pte_to_phys(pte_t pte) 115 { 116 pte_val(pte) &= ~PTE_MAYBE_SHARED; 117 return (pte_val(pte) & PTE_ADDR_LOW) | 118 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 119 } 120 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 121 { 122 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 123 } 124 #else 125 static inline phys_addr_t __pte_to_phys(pte_t pte) 126 { 127 return pte_val(pte) & PTE_ADDR_LOW; 128 } 129 130 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 131 { 132 return phys; 133 } 134 #endif 135 136 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 137 #define pfn_pte(pfn,prot) \ 138 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 139 140 #define pte_none(pte) (!pte_val(pte)) 141 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 142 143 /* 144 * The following only work if pte_present(). Undefined behaviour otherwise. 145 */ 146 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 147 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 148 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 149 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 150 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 151 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 152 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 153 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 154 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 155 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 156 157 #define pte_cont_addr_end(addr, end) \ 158 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 159 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 160 }) 161 162 #define pmd_cont_addr_end(addr, end) \ 163 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 164 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 165 }) 166 167 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 168 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 169 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 170 171 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 172 #define pte_present_invalid(pte) \ 173 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 174 /* 175 * Execute-only user mappings do not have the PTE_USER bit set. All valid 176 * kernel mappings have the PTE_UXN bit set. 177 */ 178 #define pte_valid_not_user(pte) \ 179 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 180 /* 181 * Returns true if the pte is valid and has the contiguous bit set. 182 */ 183 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 184 /* 185 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 186 * so that we don't erroneously return false for pages that have been 187 * remapped as PROT_NONE but are yet to be flushed from the TLB. 188 * Note that we can't make any assumptions based on the state of the access 189 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 190 * TLB. 191 */ 192 #define pte_accessible(mm, pte) \ 193 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 194 195 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 196 { 197 u64 por; 198 199 if (!system_supports_poe()) 200 return true; 201 202 por = read_sysreg_s(SYS_POR_EL0); 203 204 if (write) 205 return por_elx_allows_write(por, pkey); 206 207 if (execute) 208 return por_elx_allows_exec(por, pkey); 209 210 return por_elx_allows_read(por, pkey); 211 } 212 213 /* 214 * p??_access_permitted() is true for valid user mappings (PTE_USER 215 * bit set, subject to the write permission check). For execute-only 216 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 217 * not set) must return false. PROT_NONE mappings do not have the 218 * PTE_VALID bit set. 219 */ 220 #define pte_access_permitted_no_overlay(pte, write) \ 221 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 222 #define pte_access_permitted(pte, write) \ 223 (pte_access_permitted_no_overlay(pte, write) && \ 224 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 225 #define pmd_access_permitted(pmd, write) \ 226 (pte_access_permitted(pmd_pte(pmd), (write))) 227 #define pud_access_permitted(pud, write) \ 228 (pte_access_permitted(pud_pte(pud), (write))) 229 230 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 231 { 232 pte_val(pte) &= ~pgprot_val(prot); 233 return pte; 234 } 235 236 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 237 { 238 pte_val(pte) |= pgprot_val(prot); 239 return pte; 240 } 241 242 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 243 { 244 pmd_val(pmd) &= ~pgprot_val(prot); 245 return pmd; 246 } 247 248 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 249 { 250 pmd_val(pmd) |= pgprot_val(prot); 251 return pmd; 252 } 253 254 static inline pte_t pte_mkwrite_novma(pte_t pte) 255 { 256 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 257 if (pte_sw_dirty(pte)) 258 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 259 return pte; 260 } 261 262 static inline pte_t pte_mkclean(pte_t pte) 263 { 264 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 265 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 266 267 return pte; 268 } 269 270 static inline pte_t pte_mkdirty(pte_t pte) 271 { 272 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 273 274 if (pte_write(pte)) 275 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 276 277 return pte; 278 } 279 280 static inline pte_t pte_wrprotect(pte_t pte) 281 { 282 /* 283 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 284 * clear), set the PTE_DIRTY bit. 285 */ 286 if (pte_hw_dirty(pte)) 287 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 288 289 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 290 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 291 return pte; 292 } 293 294 static inline pte_t pte_mkold(pte_t pte) 295 { 296 return clear_pte_bit(pte, __pgprot(PTE_AF)); 297 } 298 299 static inline pte_t pte_mkyoung(pte_t pte) 300 { 301 return set_pte_bit(pte, __pgprot(PTE_AF)); 302 } 303 304 static inline pte_t pte_mkspecial(pte_t pte) 305 { 306 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 307 } 308 309 static inline pte_t pte_mkcont(pte_t pte) 310 { 311 return set_pte_bit(pte, __pgprot(PTE_CONT)); 312 } 313 314 static inline pte_t pte_mknoncont(pte_t pte) 315 { 316 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 317 } 318 319 static inline pte_t pte_mkvalid_k(pte_t pte) 320 { 321 pte = clear_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 322 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_VALID_KERNEL)); 323 return pte; 324 } 325 326 static inline pte_t pte_mkinvalid(pte_t pte) 327 { 328 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 329 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 330 return pte; 331 } 332 333 static inline pmd_t pmd_mkcont(pmd_t pmd) 334 { 335 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 336 } 337 338 static inline pmd_t pmd_mknoncont(pmd_t pmd) 339 { 340 return __pmd(pmd_val(pmd) & ~PMD_SECT_CONT); 341 } 342 343 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 344 static inline int pte_uffd(pte_t pte) 345 { 346 return !!(pte_val(pte) & PTE_UFFD); 347 } 348 349 static inline pte_t pte_mkuffd(pte_t pte) 350 { 351 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD))); 352 } 353 354 static inline pte_t pte_clear_uffd(pte_t pte) 355 { 356 return clear_pte_bit(pte, __pgprot(PTE_UFFD)); 357 } 358 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 359 360 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 361 { 362 WRITE_ONCE(*ptep, pte); 363 } 364 365 static inline void __set_pte_complete(pte_t pte) 366 { 367 /* 368 * Only if the new pte is valid and kernel, otherwise TLB maintenance 369 * has the necessary barriers. 370 */ 371 if (pte_valid_not_user(pte)) 372 queue_pte_barriers(); 373 } 374 375 static inline void __set_pte(pte_t *ptep, pte_t pte) 376 { 377 __set_pte_nosync(ptep, pte); 378 __set_pte_complete(pte); 379 } 380 381 static inline pte_t __ptep_get(pte_t *ptep) 382 { 383 return READ_ONCE(*ptep); 384 } 385 386 extern void __sync_icache_dcache(pte_t pteval); 387 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 388 389 /* 390 * PTE bits configuration in the presence of hardware Dirty Bit Management 391 * (PTE_WRITE == PTE_DBM): 392 * 393 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 394 * 0 0 | 1 0 0 395 * 0 1 | 1 1 0 396 * 1 0 | 1 0 1 397 * 1 1 | 0 1 x 398 * 399 * When hardware DBM is not present, the software PTE_DIRTY bit is updated via 400 * the page fault mechanism. Checking the dirty status of a pte becomes: 401 * 402 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 403 */ 404 405 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 406 pte_t pte) 407 { 408 pte_t old_pte; 409 410 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 411 return; 412 413 old_pte = __ptep_get(ptep); 414 415 if (!pte_valid(old_pte) || !pte_valid(pte)) 416 return; 417 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 418 return; 419 420 /* 421 * Check for potential race with hardware updates of the pte 422 * (__ptep_set_access_flags safely changes valid ptes without going 423 * through an invalid entry). 424 */ 425 VM_WARN_ONCE(!pte_young(pte), 426 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 427 __func__, pte_val(old_pte), pte_val(pte)); 428 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 429 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 430 __func__, pte_val(old_pte), pte_val(pte)); 431 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 432 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 433 __func__, pte_val(old_pte), pte_val(pte)); 434 } 435 436 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 437 { 438 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 439 __sync_icache_dcache(pte); 440 441 /* 442 * If the PTE would provide user space access to the tags associated 443 * with it then ensure that the MTE tags are synchronised. Although 444 * pte_access_permitted_no_overlay() returns false for exec only 445 * mappings, they don't expose tags (instruction fetches don't check 446 * tags). 447 */ 448 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 449 !pte_special(pte) && pte_tagged(pte)) 450 mte_sync_tags(pte, nr_pages); 451 } 452 453 /* 454 * Select all bits except the pfn 455 */ 456 #define pte_pgprot pte_pgprot 457 static inline pgprot_t pte_pgprot(pte_t pte) 458 { 459 unsigned long pfn = pte_pfn(pte); 460 461 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 462 } 463 464 #define pte_advance_pfn pte_advance_pfn 465 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 466 { 467 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 468 } 469 470 /* 471 * Hugetlb definitions. 472 */ 473 #define HUGE_MAX_HSTATE 4 474 #define HPAGE_SHIFT PMD_SHIFT 475 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 476 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 477 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 478 479 static inline pte_t pgd_pte(pgd_t pgd) 480 { 481 return __pte(pgd_val(pgd)); 482 } 483 484 static inline pte_t p4d_pte(p4d_t p4d) 485 { 486 return __pte(p4d_val(p4d)); 487 } 488 489 static inline pte_t pud_pte(pud_t pud) 490 { 491 return __pte(pud_val(pud)); 492 } 493 494 static inline pud_t pte_pud(pte_t pte) 495 { 496 return __pud(pte_val(pte)); 497 } 498 499 static inline pmd_t pud_pmd(pud_t pud) 500 { 501 return __pmd(pud_val(pud)); 502 } 503 504 static inline pte_t pmd_pte(pmd_t pmd) 505 { 506 return __pte(pmd_val(pmd)); 507 } 508 509 static inline pmd_t pte_pmd(pte_t pte) 510 { 511 return __pmd(pte_val(pte)); 512 } 513 514 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 515 { 516 return __pgprot((pgprot_val(prot) & ~PUD_TYPE_MASK) | PUD_TYPE_SECT); 517 } 518 519 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 520 { 521 return __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); 522 } 523 524 static inline pte_t pte_swp_mkexclusive(pte_t pte) 525 { 526 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 527 } 528 529 static inline bool pte_swp_exclusive(pte_t pte) 530 { 531 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 532 } 533 534 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 535 { 536 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 537 } 538 539 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 540 static inline pte_t pte_swp_mkuffd(pte_t pte) 541 { 542 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD)); 543 } 544 545 static inline int pte_swp_uffd(pte_t pte) 546 { 547 return !!(pte_val(pte) & PTE_SWP_UFFD); 548 } 549 550 static inline pte_t pte_swp_clear_uffd(pte_t pte) 551 { 552 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD)); 553 } 554 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 555 556 #ifdef CONFIG_ARCH_HAS_PTE_PROTNONE 557 static inline int pte_protnone(pte_t pte) 558 { 559 /* 560 * pte_present_invalid() tells us that the pte is invalid from HW 561 * perspective but present from SW perspective, so the fields are to be 562 * interpreted as per the HW layout. The second 2 checks are the unique 563 * encoding that we use for PROT_NONE. It is insufficient to only use 564 * the first check because we share the same encoding scheme with pmds 565 * which support pmd_mkinvalid(), so can be present-invalid without 566 * being PROT_NONE. 567 */ 568 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 569 } 570 571 static inline int pmd_protnone(pmd_t pmd) 572 { 573 return pte_protnone(pmd_pte(pmd)); 574 } 575 #endif /* CONFIG_ARCH_HAS_PTE_PROTNONE */ 576 577 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 578 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 579 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 580 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 581 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 582 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 583 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 584 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 585 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 586 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 587 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 588 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 589 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 590 #define pmd_mkvalid_k(pmd) pte_pmd(pte_mkvalid_k(pmd_pte(pmd))) 591 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 592 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 593 #define pmd_uffd(pmd) pte_uffd(pmd_pte(pmd)) 594 #define pmd_mkuffd(pmd) pte_pmd(pte_mkuffd(pmd_pte(pmd))) 595 #define pmd_clear_uffd(pmd) pte_pmd(pte_clear_uffd(pmd_pte(pmd))) 596 #define pmd_swp_uffd(pmd) pte_swp_uffd(pmd_pte(pmd)) 597 #define pmd_swp_mkuffd(pmd) pte_pmd(pte_swp_mkuffd(pmd_pte(pmd))) 598 #define pmd_swp_clear_uffd(pmd) \ 599 pte_pmd(pte_swp_clear_uffd(pmd_pte(pmd))) 600 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 601 602 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 603 604 static inline pmd_t pmd_mkhuge(pmd_t pmd) 605 { 606 /* 607 * It's possible that the pmd is present-invalid on entry 608 * and in that case it needs to remain present-invalid on 609 * exit. So ensure the VALID bit does not get modified. 610 */ 611 pmdval_t mask = PMD_TYPE_MASK & ~PTE_VALID; 612 pmdval_t val = PMD_TYPE_SECT & ~PTE_VALID; 613 614 return __pmd((pmd_val(pmd) & ~mask) | val); 615 } 616 617 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 618 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 619 static inline pmd_t pmd_mkspecial(pmd_t pmd) 620 { 621 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 622 } 623 #endif 624 625 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 626 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 627 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 628 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 629 630 #define pud_young(pud) pte_young(pud_pte(pud)) 631 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 632 #define pud_mkwrite_novma(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) 633 #define pud_mkvalid_k(pud) pte_pud(pte_mkvalid_k(pud_pte(pud))) 634 #define pud_write(pud) pte_write(pud_pte(pud)) 635 636 static inline pud_t pud_mkhuge(pud_t pud) 637 { 638 /* 639 * It's possible that the pud is present-invalid on entry 640 * and in that case it needs to remain present-invalid on 641 * exit. So ensure the VALID bit does not get modified. 642 */ 643 pudval_t mask = PUD_TYPE_MASK & ~PTE_VALID; 644 pudval_t val = PUD_TYPE_SECT & ~PTE_VALID; 645 646 return __pud((pud_val(pud) & ~mask) | val); 647 } 648 649 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 650 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 651 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 652 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 653 654 #define pmd_pgprot pmd_pgprot 655 static inline pgprot_t pmd_pgprot(pmd_t pmd) 656 { 657 unsigned long pfn = pmd_pfn(pmd); 658 659 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 660 } 661 662 #define pud_pgprot pud_pgprot 663 static inline pgprot_t pud_pgprot(pud_t pud) 664 { 665 unsigned long pfn = pud_pfn(pud); 666 667 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 668 } 669 670 static inline void __set_ptes_anysz(struct mm_struct *mm, unsigned long addr, 671 pte_t *ptep, pte_t pte, unsigned int nr, 672 unsigned long pgsize) 673 { 674 unsigned long stride = pgsize >> PAGE_SHIFT; 675 676 switch (pgsize) { 677 case PAGE_SIZE: 678 page_table_check_ptes_set(mm, addr, ptep, pte, nr); 679 break; 680 case PMD_SIZE: 681 page_table_check_pmds_set(mm, addr, (pmd_t *)ptep, 682 pte_pmd(pte), nr); 683 break; 684 #ifndef __PAGETABLE_PMD_FOLDED 685 case PUD_SIZE: 686 page_table_check_puds_set(mm, addr, (pud_t *)ptep, 687 pte_pud(pte), nr); 688 break; 689 #endif 690 default: 691 VM_WARN_ON(1); 692 } 693 694 __sync_cache_and_tags(pte, nr * stride); 695 696 for (;;) { 697 __check_safe_pte_update(mm, ptep, pte); 698 __set_pte_nosync(ptep, pte); 699 if (--nr == 0) 700 break; 701 ptep++; 702 pte = pte_advance_pfn(pte, stride); 703 } 704 705 __set_pte_complete(pte); 706 } 707 708 static inline void __set_ptes(struct mm_struct *mm, unsigned long addr, 709 pte_t *ptep, pte_t pte, unsigned int nr) 710 { 711 __set_ptes_anysz(mm, addr, ptep, pte, nr, PAGE_SIZE); 712 } 713 714 static inline void __set_pmds(struct mm_struct *mm, unsigned long addr, 715 pmd_t *pmdp, pmd_t pmd, unsigned int nr) 716 { 717 __set_ptes_anysz(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), nr, PMD_SIZE); 718 } 719 #define set_pmd_at(mm, addr, pmdp, pmd) __set_pmds(mm, addr, pmdp, pmd, 1) 720 721 static inline void __set_puds(struct mm_struct *mm, unsigned long addr, 722 pud_t *pudp, pud_t pud, unsigned int nr) 723 { 724 __set_ptes_anysz(mm, addr, (pte_t *)pudp, pud_pte(pud), nr, PUD_SIZE); 725 } 726 #define set_pud_at(mm, addr, pudp, pud) __set_puds(mm, addr, pudp, pud, 1) 727 728 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 729 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 730 731 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 732 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 733 734 #define __pgprot_modify(prot,mask,bits) \ 735 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 736 737 #define pgprot_nx(prot) \ 738 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 739 740 #define pgprot_decrypted(prot) \ 741 __pgprot_modify(prot, PROT_NS_SHARED, PROT_NS_SHARED) 742 #define pgprot_encrypted(prot) \ 743 __pgprot_modify(prot, PROT_NS_SHARED, 0) 744 745 /* 746 * Mark the prot value as uncacheable and unbufferable. 747 */ 748 #define pgprot_noncached(prot) \ 749 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 750 #define pgprot_writecombine(prot) \ 751 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 752 #define pgprot_device(prot) \ 753 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 754 #define pgprot_tagged(prot) \ 755 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 756 #define pgprot_mhp pgprot_tagged 757 /* 758 * DMA allocations for non-coherent devices use what the Arm architecture calls 759 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 760 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 761 * is intended for MMIO and thus forbids speculation, preserves access size, 762 * requires strict alignment and can also force write responses to come from the 763 * endpoint. 764 */ 765 #define pgprot_dmacoherent(prot) \ 766 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 767 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 768 769 #define __HAVE_PHYS_MEM_ACCESS_PROT 770 struct file; 771 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 772 unsigned long size, pgprot_t vma_prot); 773 774 #define pmd_none(pmd) (!pmd_val(pmd)) 775 776 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 777 PMD_TYPE_TABLE) 778 779 #define pmd_leaf pmd_leaf 780 static inline bool pmd_leaf(pmd_t pmd) 781 { 782 return pmd_present(pmd) && !pmd_table(pmd); 783 } 784 785 #define pmd_bad(pmd) (!pmd_table(pmd)) 786 787 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 788 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 789 790 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 791 static inline int pmd_trans_huge(pmd_t pmd) 792 { 793 /* 794 * If pmd is present-invalid, pmd_table() won't detect it 795 * as a table, so force the valid bit for the comparison. 796 */ 797 return pmd_present(pmd) && !pmd_table(__pmd(pmd_val(pmd) | PTE_VALID)); 798 } 799 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 800 801 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 802 static inline bool pud_table(pud_t pud) { return true; } 803 #else 804 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 805 PUD_TYPE_TABLE) 806 #endif 807 808 extern pgd_t swapper_pg_dir[]; 809 extern pgd_t idmap_pg_dir[]; 810 extern pgd_t tramp_pg_dir[]; 811 extern pgd_t reserved_pg_dir[]; 812 813 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 814 815 static inline bool in_swapper_pgdir(void *addr) 816 { 817 return ((unsigned long)addr & PAGE_MASK) == 818 ((unsigned long)swapper_pg_dir & PAGE_MASK); 819 } 820 821 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 822 { 823 #ifdef __PAGETABLE_PMD_FOLDED 824 if (in_swapper_pgdir(pmdp)) { 825 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 826 return; 827 } 828 #endif /* __PAGETABLE_PMD_FOLDED */ 829 830 WRITE_ONCE(*pmdp, pmd); 831 832 if (pmd_valid(pmd)) 833 queue_pte_barriers(); 834 } 835 836 static inline void pmd_clear(pmd_t *pmdp) 837 { 838 set_pmd(pmdp, __pmd(0)); 839 } 840 841 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 842 { 843 return __pmd_to_phys(pmd); 844 } 845 846 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 847 { 848 return (unsigned long)__va(pmd_page_paddr(pmd)); 849 } 850 851 /* Find an entry in the third-level page table. */ 852 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 853 854 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 855 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 856 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 857 858 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 859 860 /* use ONLY for statically allocated translation tables */ 861 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 862 863 #if CONFIG_PGTABLE_LEVELS > 2 864 865 #define pmd_ERROR(e) \ 866 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 867 868 #define pud_none(pud) (!pud_val(pud)) 869 #define pud_bad(pud) ((pud_val(pud) & PUD_TYPE_MASK) != \ 870 PUD_TYPE_TABLE) 871 #define pud_present(pud) pte_present(pud_pte(pud)) 872 #ifndef __PAGETABLE_PMD_FOLDED 873 #define pud_leaf pud_leaf 874 static inline bool pud_leaf(pud_t pud) 875 { 876 return pud_present(pud) && !pud_table(pud); 877 } 878 #else 879 #define pud_leaf(pud) false 880 #endif 881 #define pud_valid(pud) pte_valid(pud_pte(pud)) 882 #define pud_user(pud) pte_user(pud_pte(pud)) 883 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 884 885 static inline bool pgtable_l4_enabled(void); 886 887 static inline void set_pud(pud_t *pudp, pud_t pud) 888 { 889 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 890 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 891 return; 892 } 893 894 WRITE_ONCE(*pudp, pud); 895 896 if (pud_valid(pud)) 897 queue_pte_barriers(); 898 } 899 900 static inline void pud_clear(pud_t *pudp) 901 { 902 set_pud(pudp, __pud(0)); 903 } 904 905 static inline phys_addr_t pud_page_paddr(pud_t pud) 906 { 907 return __pud_to_phys(pud); 908 } 909 910 static inline pmd_t *pud_pgtable(pud_t pud) 911 { 912 return (pmd_t *)__va(pud_page_paddr(pud)); 913 } 914 915 /* Find an entry in the second-level page table. */ 916 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 917 918 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 919 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 920 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 921 922 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 923 924 /* use ONLY for statically allocated translation tables */ 925 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 926 927 #else 928 929 #define pud_valid(pud) false 930 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 931 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 932 933 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 934 #define pmd_set_fixmap(addr) NULL 935 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 936 #define pmd_clear_fixmap() 937 938 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 939 940 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 941 942 #if CONFIG_PGTABLE_LEVELS > 3 943 944 static __always_inline bool pgtable_l4_enabled(void) 945 { 946 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 947 return true; 948 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 949 return vabits_actual == VA_BITS; 950 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 951 } 952 953 static inline bool mm_pud_folded(const struct mm_struct *mm) 954 { 955 return !pgtable_l4_enabled(); 956 } 957 #define mm_pud_folded mm_pud_folded 958 959 #define pud_ERROR(e) \ 960 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 961 962 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 963 #define p4d_bad(p4d) (pgtable_l4_enabled() && \ 964 ((p4d_val(p4d) & P4D_TYPE_MASK) != \ 965 P4D_TYPE_TABLE)) 966 #define p4d_present(p4d) (!p4d_none(p4d)) 967 968 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 969 { 970 if (in_swapper_pgdir(p4dp)) { 971 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 972 return; 973 } 974 975 WRITE_ONCE(*p4dp, p4d); 976 queue_pte_barriers(); 977 } 978 979 static inline void p4d_clear(p4d_t *p4dp) 980 { 981 if (pgtable_l4_enabled()) 982 set_p4d(p4dp, __p4d(0)); 983 } 984 985 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 986 { 987 return __p4d_to_phys(p4d); 988 } 989 990 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 991 992 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 993 { 994 /* Ensure that 'p4dp' indexes a page table according to 'addr' */ 995 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D); 996 997 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 998 } 999 1000 static inline pud_t *p4d_pgtable(p4d_t p4d) 1001 { 1002 return (pud_t *)__va(p4d_page_paddr(p4d)); 1003 } 1004 1005 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 1006 { 1007 VM_WARN_ON_ONCE(!pgtable_l4_enabled()); 1008 1009 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 1010 } 1011 1012 static inline 1013 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 1014 { 1015 if (!pgtable_l4_enabled()) 1016 return p4d_to_folded_pud(p4dp, addr); 1017 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 1018 } 1019 #define pud_offset_lockless pud_offset_lockless 1020 1021 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 1022 { 1023 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 1024 } 1025 #define pud_offset pud_offset 1026 1027 static inline pud_t *pud_set_fixmap(unsigned long addr) 1028 { 1029 if (!pgtable_l4_enabled()) 1030 return NULL; 1031 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 1032 } 1033 1034 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 1035 { 1036 if (!pgtable_l4_enabled()) 1037 return p4d_to_folded_pud(p4dp, addr); 1038 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 1039 } 1040 1041 static inline void pud_clear_fixmap(void) 1042 { 1043 if (pgtable_l4_enabled()) 1044 clear_fixmap(FIX_PUD); 1045 } 1046 1047 /* use ONLY for statically allocated translation tables */ 1048 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 1049 { 1050 if (!pgtable_l4_enabled()) 1051 return p4d_to_folded_pud(p4dp, addr); 1052 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 1053 } 1054 1055 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 1056 1057 #else 1058 1059 static inline bool pgtable_l4_enabled(void) { return false; } 1060 1061 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 1062 1063 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 1064 #define pud_set_fixmap(addr) NULL 1065 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 1066 #define pud_clear_fixmap() 1067 1068 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 1069 1070 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1071 1072 #if CONFIG_PGTABLE_LEVELS > 4 1073 1074 static __always_inline bool pgtable_l5_enabled(void) 1075 { 1076 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1077 return vabits_actual == VA_BITS; 1078 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1079 } 1080 1081 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1082 { 1083 return !pgtable_l5_enabled(); 1084 } 1085 #define mm_p4d_folded mm_p4d_folded 1086 1087 #define p4d_ERROR(e) \ 1088 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1089 1090 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1091 #define pgd_bad(pgd) (pgtable_l5_enabled() && \ 1092 ((pgd_val(pgd) & PGD_TYPE_MASK) != \ 1093 PGD_TYPE_TABLE)) 1094 #define pgd_present(pgd) (!pgd_none(pgd)) 1095 1096 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1097 { 1098 if (in_swapper_pgdir(pgdp)) { 1099 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1100 return; 1101 } 1102 1103 WRITE_ONCE(*pgdp, pgd); 1104 queue_pte_barriers(); 1105 } 1106 1107 static inline void pgd_clear(pgd_t *pgdp) 1108 { 1109 if (pgtable_l5_enabled()) 1110 set_pgd(pgdp, __pgd(0)); 1111 } 1112 1113 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1114 { 1115 return __pgd_to_phys(pgd); 1116 } 1117 1118 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1119 1120 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1121 { 1122 /* Ensure that 'pgdp' indexes a page table according to 'addr' */ 1123 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD); 1124 1125 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1126 } 1127 1128 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1129 { 1130 VM_WARN_ON_ONCE(!pgtable_l5_enabled()); 1131 1132 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1133 } 1134 1135 static inline 1136 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1137 { 1138 if (!pgtable_l5_enabled()) 1139 return pgd_to_folded_p4d(pgdp, addr); 1140 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1141 } 1142 #define p4d_offset_lockless p4d_offset_lockless 1143 1144 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1145 { 1146 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1147 } 1148 1149 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1150 { 1151 if (!pgtable_l5_enabled()) 1152 return NULL; 1153 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1154 } 1155 1156 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1157 { 1158 if (!pgtable_l5_enabled()) 1159 return pgd_to_folded_p4d(pgdp, addr); 1160 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1161 } 1162 1163 static inline void p4d_clear_fixmap(void) 1164 { 1165 if (pgtable_l5_enabled()) 1166 clear_fixmap(FIX_P4D); 1167 } 1168 1169 /* use ONLY for statically allocated translation tables */ 1170 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1171 { 1172 if (!pgtable_l5_enabled()) 1173 return pgd_to_folded_p4d(pgdp, addr); 1174 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1175 } 1176 1177 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1178 1179 #else 1180 1181 static inline bool pgtable_l5_enabled(void) { return false; } 1182 1183 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1184 1185 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1186 #define p4d_set_fixmap(addr) NULL 1187 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1188 #define p4d_clear_fixmap() 1189 1190 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1191 1192 static inline 1193 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1194 { 1195 /* 1196 * With runtime folding of the pud, pud_offset_lockless() passes 1197 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1198 * will offset the pointer assuming that it points into 1199 * a page-table page. However, the fast GUP path passes us a 1200 * pgd_t allocated on the stack and so we must use the original 1201 * pointer in 'pgdp' to construct the p4d pointer instead of 1202 * using the generic p4d_offset_lockless() implementation. 1203 * 1204 * Note: reusing the original pointer means that we may 1205 * dereference the same (live) page-table entry multiple times. 1206 * This is safe because it is still only loaded once in the 1207 * context of each level and the CPU guarantees same-address 1208 * read-after-read ordering. 1209 */ 1210 return p4d_offset(pgdp, addr); 1211 } 1212 #define p4d_offset_lockless p4d_offset_lockless_folded 1213 1214 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1215 1216 #define pgd_ERROR(e) \ 1217 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1218 1219 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1220 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1221 1222 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1223 { 1224 /* 1225 * Normal and Normal-Tagged are two different memory types and indices 1226 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1227 */ 1228 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1229 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1230 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1231 1232 /* preserve the hardware dirty information */ 1233 if (pte_hw_dirty(pte)) 1234 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1235 1236 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1237 /* 1238 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1239 * dirtiness again. 1240 */ 1241 if (pte_sw_dirty(pte)) 1242 pte = pte_mkdirty(pte); 1243 return pte; 1244 } 1245 1246 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1247 { 1248 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1249 } 1250 1251 extern int __ptep_set_access_flags_anysz(struct vm_area_struct *vma, 1252 unsigned long address, pte_t *ptep, 1253 pte_t entry, int dirty, 1254 unsigned long pgsize); 1255 1256 static inline int __ptep_set_access_flags(struct vm_area_struct *vma, 1257 unsigned long address, pte_t *ptep, 1258 pte_t entry, int dirty) 1259 { 1260 return __ptep_set_access_flags_anysz(vma, address, ptep, entry, dirty, 1261 PAGE_SIZE); 1262 } 1263 1264 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1265 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1266 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1267 unsigned long address, pmd_t *pmdp, 1268 pmd_t entry, int dirty) 1269 { 1270 return __ptep_set_access_flags_anysz(vma, address, (pte_t *)pmdp, 1271 pmd_pte(entry), dirty, PMD_SIZE); 1272 } 1273 #endif 1274 1275 #ifdef CONFIG_PAGE_TABLE_CHECK 1276 static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte) 1277 { 1278 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1279 } 1280 1281 static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd) 1282 { 1283 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1284 } 1285 1286 static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud) 1287 { 1288 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1289 } 1290 #endif 1291 1292 /* 1293 * Atomic pte/pmd modifications. 1294 */ 1295 1296 static inline void __pte_clear(struct mm_struct *mm, 1297 unsigned long addr, pte_t *ptep) 1298 { 1299 __set_pte(ptep, __pte(0)); 1300 } 1301 1302 static inline bool __ptep_test_and_clear_young(struct vm_area_struct *vma, 1303 unsigned long address, pte_t *ptep) 1304 { 1305 pte_t old_pte, pte; 1306 1307 pte = __ptep_get(ptep); 1308 do { 1309 old_pte = pte; 1310 pte = pte_mkold(pte); 1311 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1312 pte_val(old_pte), pte_val(pte)); 1313 } while (pte_val(pte) != pte_val(old_pte)); 1314 1315 return pte_young(pte); 1316 } 1317 1318 static inline bool __ptep_clear_flush_young(struct vm_area_struct *vma, 1319 unsigned long address, pte_t *ptep) 1320 { 1321 bool young = __ptep_test_and_clear_young(vma, address, ptep); 1322 1323 if (young) { 1324 /* 1325 * We can elide the trailing DSB here since the worst that can 1326 * happen is that a CPU continues to use the young entry in its 1327 * TLB and we mistakenly reclaim the associated page. The 1328 * window for such an event is bounded by the next 1329 * context-switch, which provides a DSB to complete the TLB 1330 * invalidation. 1331 */ 1332 __flush_tlb_page(vma, address, TLBF_NOSYNC); 1333 } 1334 1335 return young; 1336 } 1337 1338 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 1339 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1340 static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma, 1341 unsigned long address, pmd_t *pmdp) 1342 { 1343 /* Operation applies to PMD table entry only if FEAT_HAFT is enabled */ 1344 VM_WARN_ON(pmd_table(READ_ONCE(*pmdp)) && !system_supports_haft()); 1345 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1346 } 1347 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 1348 1349 static inline pte_t __ptep_get_and_clear_anysz(struct mm_struct *mm, 1350 unsigned long address, 1351 pte_t *ptep, 1352 unsigned long pgsize) 1353 { 1354 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1355 1356 switch (pgsize) { 1357 case PAGE_SIZE: 1358 page_table_check_pte_clear(mm, address, pte); 1359 break; 1360 case PMD_SIZE: 1361 page_table_check_pmd_clear(mm, address, pte_pmd(pte)); 1362 break; 1363 #ifndef __PAGETABLE_PMD_FOLDED 1364 case PUD_SIZE: 1365 page_table_check_pud_clear(mm, address, pte_pud(pte)); 1366 break; 1367 #endif 1368 default: 1369 VM_WARN_ON(1); 1370 } 1371 1372 return pte; 1373 } 1374 1375 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1376 unsigned long address, pte_t *ptep) 1377 { 1378 return __ptep_get_and_clear_anysz(mm, address, ptep, PAGE_SIZE); 1379 } 1380 1381 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1382 pte_t *ptep, unsigned int nr, int full) 1383 { 1384 for (;;) { 1385 __ptep_get_and_clear(mm, addr, ptep); 1386 if (--nr == 0) 1387 break; 1388 ptep++; 1389 addr += PAGE_SIZE; 1390 } 1391 } 1392 1393 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1394 unsigned long addr, pte_t *ptep, 1395 unsigned int nr, int full) 1396 { 1397 pte_t pte, tmp_pte; 1398 1399 pte = __ptep_get_and_clear(mm, addr, ptep); 1400 while (--nr) { 1401 ptep++; 1402 addr += PAGE_SIZE; 1403 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1404 if (pte_dirty(tmp_pte)) 1405 pte = pte_mkdirty(pte); 1406 if (pte_young(tmp_pte)) 1407 pte = pte_mkyoung(pte); 1408 } 1409 return pte; 1410 } 1411 1412 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1413 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1414 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1415 unsigned long address, pmd_t *pmdp) 1416 { 1417 return pte_pmd(__ptep_get_and_clear_anysz(mm, address, (pte_t *)pmdp, PMD_SIZE)); 1418 } 1419 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1420 1421 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1422 unsigned long address, pte_t *ptep, 1423 pte_t pte) 1424 { 1425 pte_t old_pte; 1426 1427 do { 1428 old_pte = pte; 1429 pte = pte_wrprotect(pte); 1430 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1431 pte_val(old_pte), pte_val(pte)); 1432 } while (pte_val(pte) != pte_val(old_pte)); 1433 } 1434 1435 /* 1436 * __ptep_set_wrprotect - mark read-only while transferring potential hardware 1437 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1438 */ 1439 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1440 unsigned long address, pte_t *ptep) 1441 { 1442 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1443 } 1444 1445 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1446 pte_t *ptep, unsigned int nr) 1447 { 1448 unsigned int i; 1449 1450 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1451 __ptep_set_wrprotect(mm, address, ptep); 1452 } 1453 1454 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1455 unsigned long addr, pte_t *ptep, 1456 pte_t pte, cydp_t flags) 1457 { 1458 pte_t old_pte; 1459 1460 do { 1461 old_pte = pte; 1462 1463 if (flags & CYDP_CLEAR_YOUNG) 1464 pte = pte_mkold(pte); 1465 if (flags & CYDP_CLEAR_DIRTY) 1466 pte = pte_mkclean(pte); 1467 1468 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1469 pte_val(old_pte), pte_val(pte)); 1470 } while (pte_val(pte) != pte_val(old_pte)); 1471 } 1472 1473 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1474 unsigned long addr, pte_t *ptep, 1475 unsigned int nr, cydp_t flags) 1476 { 1477 pte_t pte; 1478 1479 for (;;) { 1480 pte = __ptep_get(ptep); 1481 1482 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1483 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1484 else 1485 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1486 1487 if (--nr == 0) 1488 break; 1489 ptep++; 1490 addr += PAGE_SIZE; 1491 } 1492 } 1493 1494 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1495 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1496 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1497 unsigned long address, pmd_t *pmdp) 1498 { 1499 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1500 } 1501 1502 #define pmdp_establish pmdp_establish 1503 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1504 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1505 { 1506 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 1507 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1508 } 1509 #endif 1510 1511 /* 1512 * Encode and decode a swap entry: 1513 * bits 0-1: present (must be zero) 1514 * bits 2: remember PG_anon_exclusive 1515 * bit 3: remember uffd state 1516 * bits 6-10: swap type 1517 * bit 11: PTE_PRESENT_INVALID (must be zero) 1518 * bits 12-61: swap offset 1519 */ 1520 #define __SWP_TYPE_SHIFT 6 1521 #define __SWP_TYPE_BITS 5 1522 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1523 #define __SWP_OFFSET_SHIFT 12 1524 #define __SWP_OFFSET_BITS 50 1525 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1526 1527 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1528 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1529 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1530 1531 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1532 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1533 1534 #ifdef CONFIG_ARCH_HAS_PMD_SOFTLEAVES 1535 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1536 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1537 #endif /* CONFIG_ARCH_HAS_PMD_SOFTLEAVES */ 1538 1539 /* 1540 * Ensure that there are not more swap files than can be encoded in the kernel 1541 * PTEs. 1542 */ 1543 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1544 1545 #ifdef CONFIG_ARM64_MTE 1546 1547 #define __HAVE_ARCH_PREPARE_TO_SWAP 1548 extern int arch_prepare_to_swap(struct folio *folio); 1549 1550 #define __HAVE_ARCH_SWAP_INVALIDATE 1551 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1552 { 1553 if (system_supports_mte()) 1554 mte_invalidate_tags(type, offset); 1555 } 1556 1557 static inline void arch_swap_invalidate_area(int type) 1558 { 1559 if (system_supports_mte()) 1560 mte_invalidate_tags_area(type); 1561 } 1562 1563 #define __HAVE_ARCH_SWAP_RESTORE 1564 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1565 1566 #endif /* CONFIG_ARM64_MTE */ 1567 1568 /* 1569 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1570 */ 1571 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1572 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1573 unsigned int nr) 1574 { 1575 /* 1576 * We don't do anything here, so there's a very small chance of 1577 * us retaking a user fault which we just fixed up. The alternative 1578 * is doing a dsb(ishst), but that penalises the fastpath. 1579 */ 1580 } 1581 1582 #define update_mmu_cache(vma, addr, ptep) \ 1583 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1584 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1585 1586 #ifdef CONFIG_ARM64_PA_BITS_52 1587 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1588 #else 1589 #define phys_to_ttbr(addr) (addr) 1590 #endif 1591 1592 /* 1593 * On arm64 without hardware Access Flag, copying from user will fail because 1594 * the pte is old and cannot be marked young. So we always end up with zeroed 1595 * page after fork() + CoW for pfn mappings. We don't always have a 1596 * hardware-managed access flag on arm64. 1597 */ 1598 #define arch_has_hw_pte_young cpu_has_hw_af 1599 1600 #ifdef CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG 1601 #define arch_has_hw_nonleaf_pmd_young system_supports_haft 1602 #endif 1603 1604 /* 1605 * Experimentally, it's cheap to set the access flag in hardware and we 1606 * benefit from prefaulting mappings as 'old' to start with. 1607 */ 1608 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1609 1610 /* 1611 * Request exec memory is read into pagecache in at least 64K folios. This size 1612 * can be contpte-mapped when 4K base pages are in use (16 pages into 1 iTLB 1613 * entry), and HPA can coalesce it (4 pages into 1 TLB entry) when 16K base 1614 * pages are in use. 1615 */ 1616 #define exec_folio_order() ilog2(SZ_64K >> PAGE_SHIFT) 1617 1618 static inline bool pud_sect_supported(void) 1619 { 1620 return PAGE_SIZE == SZ_4K; 1621 } 1622 1623 1624 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1625 #define ptep_modify_prot_start ptep_modify_prot_start 1626 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1627 unsigned long addr, pte_t *ptep); 1628 1629 #define ptep_modify_prot_commit ptep_modify_prot_commit 1630 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1631 unsigned long addr, pte_t *ptep, 1632 pte_t old_pte, pte_t new_pte); 1633 1634 #define modify_prot_start_ptes modify_prot_start_ptes 1635 extern pte_t modify_prot_start_ptes(struct vm_area_struct *vma, 1636 unsigned long addr, pte_t *ptep, 1637 unsigned int nr); 1638 1639 #define modify_prot_commit_ptes modify_prot_commit_ptes 1640 extern void modify_prot_commit_ptes(struct vm_area_struct *vma, unsigned long addr, 1641 pte_t *ptep, pte_t old_pte, pte_t pte, 1642 unsigned int nr); 1643 1644 #ifdef CONFIG_ARM64_CONTPTE 1645 1646 /* 1647 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1648 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1649 * a private implementation detail of the public ptep API (see below). 1650 */ 1651 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1652 pte_t *ptep, pte_t pte); 1653 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1654 pte_t *ptep, pte_t pte); 1655 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1656 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1657 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1658 pte_t *ptep, pte_t pte, unsigned int nr); 1659 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1660 pte_t *ptep, unsigned int nr, int full); 1661 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1662 unsigned long addr, pte_t *ptep, 1663 unsigned int nr, int full); 1664 bool contpte_test_and_clear_young_ptes(struct vm_area_struct *vma, 1665 unsigned long addr, pte_t *ptep, unsigned int nr); 1666 bool contpte_clear_flush_young_ptes(struct vm_area_struct *vma, 1667 unsigned long addr, pte_t *ptep, unsigned int nr); 1668 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1669 pte_t *ptep, unsigned int nr); 1670 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1671 unsigned long addr, pte_t *ptep, 1672 pte_t entry, int dirty); 1673 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1674 unsigned long addr, pte_t *ptep, 1675 unsigned int nr, cydp_t flags); 1676 1677 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1678 unsigned long addr, pte_t *ptep, pte_t pte) 1679 { 1680 /* 1681 * Only bother trying if both the virtual and physical addresses are 1682 * aligned and correspond to the last entry in a contig range. The core 1683 * code mostly modifies ranges from low to high, so this is the likely 1684 * the last modification in the contig range, so a good time to fold. 1685 * We can't fold special mappings, because there is no associated folio. 1686 */ 1687 1688 const unsigned long contmask = CONT_PTES - 1; 1689 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1690 1691 if (unlikely(valign)) { 1692 bool palign = (pte_pfn(pte) & contmask) == contmask; 1693 1694 if (unlikely(palign && 1695 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1696 __contpte_try_fold(mm, addr, ptep, pte); 1697 } 1698 } 1699 1700 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1701 unsigned long addr, pte_t *ptep, pte_t pte) 1702 { 1703 if (unlikely(pte_valid_cont(pte))) 1704 __contpte_try_unfold(mm, addr, ptep, pte); 1705 } 1706 1707 #define pte_batch_hint pte_batch_hint 1708 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1709 { 1710 if (!pte_valid_cont(pte)) 1711 return 1; 1712 1713 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1714 } 1715 1716 /* 1717 * The below functions constitute the public API that arm64 presents to the 1718 * core-mm to manipulate PTE entries within their page tables (or at least this 1719 * is the subset of the API that arm64 needs to implement). These public 1720 * versions will automatically and transparently apply the contiguous bit where 1721 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1722 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1723 * private versions, which are prefixed with double underscore. All of these 1724 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1725 * held. Although the contiguous bit is considered private to the 1726 * implementation, it is deliberately allowed to leak through the getters (e.g. 1727 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1728 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1729 * its possible a pte will be passed to a setter with the contiguous bit set, so 1730 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1731 * setting it in the pgtable. 1732 */ 1733 1734 #define ptep_get ptep_get 1735 static inline pte_t ptep_get(pte_t *ptep) 1736 { 1737 pte_t pte = __ptep_get(ptep); 1738 1739 if (likely(!pte_valid_cont(pte))) 1740 return pte; 1741 1742 return contpte_ptep_get(ptep, pte); 1743 } 1744 1745 #define ptep_get_lockless ptep_get_lockless 1746 static inline pte_t ptep_get_lockless(pte_t *ptep) 1747 { 1748 pte_t pte = __ptep_get(ptep); 1749 1750 if (likely(!pte_valid_cont(pte))) 1751 return pte; 1752 1753 return contpte_ptep_get_lockless(ptep); 1754 } 1755 1756 static inline void set_pte(pte_t *ptep, pte_t pte) 1757 { 1758 /* 1759 * We don't have the mm or vaddr so cannot unfold contig entries (since 1760 * it requires tlb maintenance). set_pte() is not used in core code, so 1761 * this should never even be called. Regardless do our best to service 1762 * any call and emit a warning if there is any attempt to set a pte on 1763 * top of an existing contig range. 1764 */ 1765 pte_t orig_pte = __ptep_get(ptep); 1766 1767 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1768 __set_pte(ptep, pte_mknoncont(pte)); 1769 } 1770 1771 #define set_ptes set_ptes 1772 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1773 pte_t *ptep, pte_t pte, unsigned int nr) 1774 { 1775 pte = pte_mknoncont(pte); 1776 1777 if (likely(nr == 1)) { 1778 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1779 __set_ptes(mm, addr, ptep, pte, 1); 1780 contpte_try_fold(mm, addr, ptep, pte); 1781 } else { 1782 contpte_set_ptes(mm, addr, ptep, pte, nr); 1783 } 1784 } 1785 1786 static inline void pte_clear(struct mm_struct *mm, 1787 unsigned long addr, pte_t *ptep) 1788 { 1789 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1790 __pte_clear(mm, addr, ptep); 1791 } 1792 1793 #define clear_full_ptes clear_full_ptes 1794 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1795 pte_t *ptep, unsigned int nr, int full) 1796 { 1797 if (likely(nr == 1)) { 1798 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1799 __clear_full_ptes(mm, addr, ptep, nr, full); 1800 } else { 1801 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1802 } 1803 } 1804 1805 #define get_and_clear_full_ptes get_and_clear_full_ptes 1806 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1807 unsigned long addr, pte_t *ptep, 1808 unsigned int nr, int full) 1809 { 1810 pte_t pte; 1811 1812 if (likely(nr == 1)) { 1813 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1814 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1815 } else { 1816 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1817 } 1818 1819 return pte; 1820 } 1821 1822 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1823 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1824 unsigned long addr, pte_t *ptep) 1825 { 1826 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1827 return __ptep_get_and_clear(mm, addr, ptep); 1828 } 1829 1830 static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte) 1831 { 1832 pteval_t old = 0; 1833 1834 if (!try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte))) 1835 return false; 1836 1837 /* 1838 * The store must be complete by the time this returns, but the caller 1839 * may be in lazy MMU mode, where __set_pte_complete() would defer the 1840 * barriers. Issue them directly. 1841 */ 1842 emit_pte_barriers(); 1843 return true; 1844 } 1845 #define ptep_try_set ptep_try_set 1846 1847 /* 1848 * arm64 mandates break-before-make: a cleared kernel PTE must have its TLB 1849 * invalidated before a different page is installed in its place. The broadcast 1850 * TLBI is an instruction, not an IPI, so this is safe with interrupts disabled. 1851 */ 1852 static inline void flush_tlb_before_set(unsigned long addr) 1853 { 1854 flush_tlb_kernel_range(addr, addr + PAGE_SIZE); 1855 } 1856 #define flush_tlb_before_set flush_tlb_before_set 1857 1858 #define test_and_clear_young_ptes test_and_clear_young_ptes 1859 static inline bool test_and_clear_young_ptes(struct vm_area_struct *vma, 1860 unsigned long addr, pte_t *ptep, unsigned int nr) 1861 { 1862 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1863 return __ptep_test_and_clear_young(vma, addr, ptep); 1864 1865 return contpte_test_and_clear_young_ptes(vma, addr, ptep, nr); 1866 } 1867 1868 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1869 static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma, 1870 unsigned long addr, pte_t *ptep) 1871 { 1872 return test_and_clear_young_ptes(vma, addr, ptep, 1); 1873 } 1874 1875 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1876 static inline bool ptep_clear_flush_young(struct vm_area_struct *vma, 1877 unsigned long addr, pte_t *ptep) 1878 { 1879 pte_t orig_pte = __ptep_get(ptep); 1880 1881 if (likely(!pte_valid_cont(orig_pte))) 1882 return __ptep_clear_flush_young(vma, addr, ptep); 1883 1884 return contpte_clear_flush_young_ptes(vma, addr, ptep, 1); 1885 } 1886 1887 #define clear_flush_young_ptes clear_flush_young_ptes 1888 static inline bool clear_flush_young_ptes(struct vm_area_struct *vma, 1889 unsigned long addr, pte_t *ptep, unsigned int nr) 1890 { 1891 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1892 return __ptep_clear_flush_young(vma, addr, ptep); 1893 1894 return contpte_clear_flush_young_ptes(vma, addr, ptep, nr); 1895 } 1896 1897 #define wrprotect_ptes wrprotect_ptes 1898 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1899 unsigned long addr, pte_t *ptep, unsigned int nr) 1900 { 1901 if (likely(nr == 1)) { 1902 /* 1903 * Optimization: wrprotect_ptes() can only be called for present 1904 * ptes so we only need to check contig bit as condition for 1905 * unfold, and we can remove the contig bit from the pte we read 1906 * to avoid re-reading. This speeds up fork() which is sensitive 1907 * for order-0 folios. Equivalent to contpte_try_unfold(). 1908 */ 1909 pte_t orig_pte = __ptep_get(ptep); 1910 1911 if (unlikely(pte_cont(orig_pte))) { 1912 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1913 orig_pte = pte_mknoncont(orig_pte); 1914 } 1915 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1916 } else { 1917 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1918 } 1919 } 1920 1921 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1922 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1923 unsigned long addr, pte_t *ptep) 1924 { 1925 wrprotect_ptes(mm, addr, ptep, 1); 1926 } 1927 1928 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1929 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1930 unsigned long addr, pte_t *ptep, 1931 pte_t entry, int dirty) 1932 { 1933 pte_t orig_pte = __ptep_get(ptep); 1934 1935 entry = pte_mknoncont(entry); 1936 1937 if (likely(!pte_valid_cont(orig_pte))) 1938 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1939 1940 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1941 } 1942 1943 #define clear_young_dirty_ptes clear_young_dirty_ptes 1944 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1945 unsigned long addr, pte_t *ptep, 1946 unsigned int nr, cydp_t flags) 1947 { 1948 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1949 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1950 else 1951 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1952 } 1953 1954 #else /* CONFIG_ARM64_CONTPTE */ 1955 1956 #define ptep_get __ptep_get 1957 #define set_pte __set_pte 1958 #define set_ptes __set_ptes 1959 #define pte_clear __pte_clear 1960 #define clear_full_ptes __clear_full_ptes 1961 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1962 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1963 #define ptep_get_and_clear __ptep_get_and_clear 1964 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1965 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1966 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1967 #define ptep_clear_flush_young __ptep_clear_flush_young 1968 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1969 #define ptep_set_wrprotect __ptep_set_wrprotect 1970 #define wrprotect_ptes __wrprotect_ptes 1971 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1972 #define ptep_set_access_flags __ptep_set_access_flags 1973 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1974 1975 #endif /* CONFIG_ARM64_CONTPTE */ 1976 1977 #endif /* !__ASSEMBLER__ */ 1978 1979 #endif /* __ASM_PGTABLE_H */ 1980