1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 /* 53 * Outside of a few very special situations (e.g. hibernation), we always 54 * use broadcast TLB invalidation instructions, therefore a spurious page 55 * fault on one CPU which has been handled concurrently by another CPU 56 * does not need to perform additional invalidation. 57 */ 58 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 59 60 /* 61 * ZERO_PAGE is a global shared page that is always zero: used 62 * for zero-mapped memory areas etc.. 63 */ 64 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 65 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 66 67 #define pte_ERROR(e) \ 68 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 69 70 /* 71 * Macros to convert between a physical address and its placement in a 72 * page table entry, taking care of 52-bit addresses. 73 */ 74 #ifdef CONFIG_ARM64_PA_BITS_52 75 static inline phys_addr_t __pte_to_phys(pte_t pte) 76 { 77 pte_val(pte) &= ~PTE_MAYBE_SHARED; 78 return (pte_val(pte) & PTE_ADDR_LOW) | 79 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 80 } 81 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 82 { 83 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 84 } 85 #else 86 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 87 #define __phys_to_pte_val(phys) (phys) 88 #endif 89 90 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 91 #define pfn_pte(pfn,prot) \ 92 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 93 94 #define pte_none(pte) (!pte_val(pte)) 95 #define __pte_clear(mm, addr, ptep) \ 96 __set_pte(ptep, __pte(0)) 97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 98 99 /* 100 * The following only work if pte_present(). Undefined behaviour otherwise. 101 */ 102 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 107 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 109 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 110 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 111 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 112 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 113 114 #define pte_cont_addr_end(addr, end) \ 115 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117 }) 118 119 #define pmd_cont_addr_end(addr, end) \ 120 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122 }) 123 124 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 125 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 126 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 127 128 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 129 /* 130 * Execute-only user mappings do not have the PTE_USER bit set. All valid 131 * kernel mappings have the PTE_UXN bit set. 132 */ 133 #define pte_valid_not_user(pte) \ 134 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 135 /* 136 * Returns true if the pte is valid and has the contiguous bit set. 137 */ 138 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 139 /* 140 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 141 * so that we don't erroneously return false for pages that have been 142 * remapped as PROT_NONE but are yet to be flushed from the TLB. 143 * Note that we can't make any assumptions based on the state of the access 144 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 145 * TLB. 146 */ 147 #define pte_accessible(mm, pte) \ 148 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 149 150 /* 151 * p??_access_permitted() is true for valid user mappings (PTE_USER 152 * bit set, subject to the write permission check). For execute-only 153 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 154 * not set) must return false. PROT_NONE mappings do not have the 155 * PTE_VALID bit set. 156 */ 157 #define pte_access_permitted(pte, write) \ 158 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 159 #define pmd_access_permitted(pmd, write) \ 160 (pte_access_permitted(pmd_pte(pmd), (write))) 161 #define pud_access_permitted(pud, write) \ 162 (pte_access_permitted(pud_pte(pud), (write))) 163 164 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 165 { 166 pte_val(pte) &= ~pgprot_val(prot); 167 return pte; 168 } 169 170 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 171 { 172 pte_val(pte) |= pgprot_val(prot); 173 return pte; 174 } 175 176 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 177 { 178 pmd_val(pmd) &= ~pgprot_val(prot); 179 return pmd; 180 } 181 182 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 183 { 184 pmd_val(pmd) |= pgprot_val(prot); 185 return pmd; 186 } 187 188 static inline pte_t pte_mkwrite_novma(pte_t pte) 189 { 190 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 191 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 192 return pte; 193 } 194 195 static inline pte_t pte_mkclean(pte_t pte) 196 { 197 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 198 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 199 200 return pte; 201 } 202 203 static inline pte_t pte_mkdirty(pte_t pte) 204 { 205 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 206 207 if (pte_write(pte)) 208 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 209 210 return pte; 211 } 212 213 static inline pte_t pte_wrprotect(pte_t pte) 214 { 215 /* 216 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 217 * clear), set the PTE_DIRTY bit. 218 */ 219 if (pte_hw_dirty(pte)) 220 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 221 222 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 223 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 224 return pte; 225 } 226 227 static inline pte_t pte_mkold(pte_t pte) 228 { 229 return clear_pte_bit(pte, __pgprot(PTE_AF)); 230 } 231 232 static inline pte_t pte_mkyoung(pte_t pte) 233 { 234 return set_pte_bit(pte, __pgprot(PTE_AF)); 235 } 236 237 static inline pte_t pte_mkspecial(pte_t pte) 238 { 239 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 240 } 241 242 static inline pte_t pte_mkcont(pte_t pte) 243 { 244 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 245 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 246 } 247 248 static inline pte_t pte_mknoncont(pte_t pte) 249 { 250 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 251 } 252 253 static inline pte_t pte_mkpresent(pte_t pte) 254 { 255 return set_pte_bit(pte, __pgprot(PTE_VALID)); 256 } 257 258 static inline pmd_t pmd_mkcont(pmd_t pmd) 259 { 260 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 261 } 262 263 static inline pte_t pte_mkdevmap(pte_t pte) 264 { 265 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 266 } 267 268 static inline void __set_pte(pte_t *ptep, pte_t pte) 269 { 270 WRITE_ONCE(*ptep, pte); 271 272 /* 273 * Only if the new pte is valid and kernel, otherwise TLB maintenance 274 * or update_mmu_cache() have the necessary barriers. 275 */ 276 if (pte_valid_not_user(pte)) { 277 dsb(ishst); 278 isb(); 279 } 280 } 281 282 static inline pte_t __ptep_get(pte_t *ptep) 283 { 284 return READ_ONCE(*ptep); 285 } 286 287 extern void __sync_icache_dcache(pte_t pteval); 288 bool pgattr_change_is_safe(u64 old, u64 new); 289 290 /* 291 * PTE bits configuration in the presence of hardware Dirty Bit Management 292 * (PTE_WRITE == PTE_DBM): 293 * 294 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 295 * 0 0 | 1 0 0 296 * 0 1 | 1 1 0 297 * 1 0 | 1 0 1 298 * 1 1 | 0 1 x 299 * 300 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 301 * the page fault mechanism. Checking the dirty status of a pte becomes: 302 * 303 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 304 */ 305 306 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 307 pte_t pte) 308 { 309 pte_t old_pte; 310 311 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 312 return; 313 314 old_pte = __ptep_get(ptep); 315 316 if (!pte_valid(old_pte) || !pte_valid(pte)) 317 return; 318 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 319 return; 320 321 /* 322 * Check for potential race with hardware updates of the pte 323 * (__ptep_set_access_flags safely changes valid ptes without going 324 * through an invalid entry). 325 */ 326 VM_WARN_ONCE(!pte_young(pte), 327 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 328 __func__, pte_val(old_pte), pte_val(pte)); 329 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 330 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 331 __func__, pte_val(old_pte), pte_val(pte)); 332 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 333 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 334 __func__, pte_val(old_pte), pte_val(pte)); 335 } 336 337 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 338 { 339 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 340 __sync_icache_dcache(pte); 341 342 /* 343 * If the PTE would provide user space access to the tags associated 344 * with it then ensure that the MTE tags are synchronised. Although 345 * pte_access_permitted() returns false for exec only mappings, they 346 * don't expose tags (instruction fetches don't check tags). 347 */ 348 if (system_supports_mte() && pte_access_permitted(pte, false) && 349 !pte_special(pte) && pte_tagged(pte)) 350 mte_sync_tags(pte, nr_pages); 351 } 352 353 /* 354 * Select all bits except the pfn 355 */ 356 static inline pgprot_t pte_pgprot(pte_t pte) 357 { 358 unsigned long pfn = pte_pfn(pte); 359 360 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 361 } 362 363 #define pte_advance_pfn pte_advance_pfn 364 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 365 { 366 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 367 } 368 369 static inline void __set_ptes(struct mm_struct *mm, 370 unsigned long __always_unused addr, 371 pte_t *ptep, pte_t pte, unsigned int nr) 372 { 373 page_table_check_ptes_set(mm, ptep, pte, nr); 374 __sync_cache_and_tags(pte, nr); 375 376 for (;;) { 377 __check_safe_pte_update(mm, ptep, pte); 378 __set_pte(ptep, pte); 379 if (--nr == 0) 380 break; 381 ptep++; 382 pte = pte_advance_pfn(pte, 1); 383 } 384 } 385 386 /* 387 * Huge pte definitions. 388 */ 389 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 390 391 /* 392 * Hugetlb definitions. 393 */ 394 #define HUGE_MAX_HSTATE 4 395 #define HPAGE_SHIFT PMD_SHIFT 396 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 397 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 398 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 399 400 static inline pte_t pgd_pte(pgd_t pgd) 401 { 402 return __pte(pgd_val(pgd)); 403 } 404 405 static inline pte_t p4d_pte(p4d_t p4d) 406 { 407 return __pte(p4d_val(p4d)); 408 } 409 410 static inline pte_t pud_pte(pud_t pud) 411 { 412 return __pte(pud_val(pud)); 413 } 414 415 static inline pud_t pte_pud(pte_t pte) 416 { 417 return __pud(pte_val(pte)); 418 } 419 420 static inline pmd_t pud_pmd(pud_t pud) 421 { 422 return __pmd(pud_val(pud)); 423 } 424 425 static inline pte_t pmd_pte(pmd_t pmd) 426 { 427 return __pte(pmd_val(pmd)); 428 } 429 430 static inline pmd_t pte_pmd(pte_t pte) 431 { 432 return __pmd(pte_val(pte)); 433 } 434 435 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 436 { 437 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 438 } 439 440 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 441 { 442 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 443 } 444 445 static inline pte_t pte_swp_mkexclusive(pte_t pte) 446 { 447 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 448 } 449 450 static inline int pte_swp_exclusive(pte_t pte) 451 { 452 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 453 } 454 455 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 456 { 457 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 458 } 459 460 #ifdef CONFIG_NUMA_BALANCING 461 /* 462 * See the comment in include/linux/pgtable.h 463 */ 464 static inline int pte_protnone(pte_t pte) 465 { 466 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 467 } 468 469 static inline int pmd_protnone(pmd_t pmd) 470 { 471 return pte_protnone(pmd_pte(pmd)); 472 } 473 #endif 474 475 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 476 477 static inline int pmd_present(pmd_t pmd) 478 { 479 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 480 } 481 482 /* 483 * THP definitions. 484 */ 485 486 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 487 static inline int pmd_trans_huge(pmd_t pmd) 488 { 489 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 490 } 491 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 492 493 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 494 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 495 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 496 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 497 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 498 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 499 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 500 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 501 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 502 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 503 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 504 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 505 506 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 507 { 508 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 509 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 510 511 return pmd; 512 } 513 514 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 515 516 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 517 518 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 519 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 520 #endif 521 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 522 { 523 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 524 } 525 526 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 527 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 528 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 529 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 530 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 531 532 #define pud_young(pud) pte_young(pud_pte(pud)) 533 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 534 #define pud_write(pud) pte_write(pud_pte(pud)) 535 536 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 537 538 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 539 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 540 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 541 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 542 543 static inline void __set_pte_at(struct mm_struct *mm, 544 unsigned long __always_unused addr, 545 pte_t *ptep, pte_t pte, unsigned int nr) 546 { 547 __sync_cache_and_tags(pte, nr); 548 __check_safe_pte_update(mm, ptep, pte); 549 __set_pte(ptep, pte); 550 } 551 552 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 553 pmd_t *pmdp, pmd_t pmd) 554 { 555 page_table_check_pmd_set(mm, pmdp, pmd); 556 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 557 PMD_SIZE >> PAGE_SHIFT); 558 } 559 560 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 561 pud_t *pudp, pud_t pud) 562 { 563 page_table_check_pud_set(mm, pudp, pud); 564 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 565 PUD_SIZE >> PAGE_SHIFT); 566 } 567 568 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 569 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 570 571 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 572 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 573 574 #define __pgprot_modify(prot,mask,bits) \ 575 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 576 577 #define pgprot_nx(prot) \ 578 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 579 580 /* 581 * Mark the prot value as uncacheable and unbufferable. 582 */ 583 #define pgprot_noncached(prot) \ 584 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 585 #define pgprot_writecombine(prot) \ 586 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 587 #define pgprot_device(prot) \ 588 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 589 #define pgprot_tagged(prot) \ 590 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 591 #define pgprot_mhp pgprot_tagged 592 /* 593 * DMA allocations for non-coherent devices use what the Arm architecture calls 594 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 595 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 596 * is intended for MMIO and thus forbids speculation, preserves access size, 597 * requires strict alignment and can also force write responses to come from the 598 * endpoint. 599 */ 600 #define pgprot_dmacoherent(prot) \ 601 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 602 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 603 604 #define __HAVE_PHYS_MEM_ACCESS_PROT 605 struct file; 606 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 607 unsigned long size, pgprot_t vma_prot); 608 609 #define pmd_none(pmd) (!pmd_val(pmd)) 610 611 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 612 PMD_TYPE_TABLE) 613 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 614 PMD_TYPE_SECT) 615 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 616 #define pmd_bad(pmd) (!pmd_table(pmd)) 617 618 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 619 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 620 621 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 622 static inline bool pud_sect(pud_t pud) { return false; } 623 static inline bool pud_table(pud_t pud) { return true; } 624 #else 625 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 626 PUD_TYPE_SECT) 627 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 628 PUD_TYPE_TABLE) 629 #endif 630 631 extern pgd_t init_pg_dir[]; 632 extern pgd_t init_pg_end[]; 633 extern pgd_t swapper_pg_dir[]; 634 extern pgd_t idmap_pg_dir[]; 635 extern pgd_t tramp_pg_dir[]; 636 extern pgd_t reserved_pg_dir[]; 637 638 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 639 640 static inline bool in_swapper_pgdir(void *addr) 641 { 642 return ((unsigned long)addr & PAGE_MASK) == 643 ((unsigned long)swapper_pg_dir & PAGE_MASK); 644 } 645 646 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 647 { 648 #ifdef __PAGETABLE_PMD_FOLDED 649 if (in_swapper_pgdir(pmdp)) { 650 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 651 return; 652 } 653 #endif /* __PAGETABLE_PMD_FOLDED */ 654 655 WRITE_ONCE(*pmdp, pmd); 656 657 if (pmd_valid(pmd)) { 658 dsb(ishst); 659 isb(); 660 } 661 } 662 663 static inline void pmd_clear(pmd_t *pmdp) 664 { 665 set_pmd(pmdp, __pmd(0)); 666 } 667 668 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 669 { 670 return __pmd_to_phys(pmd); 671 } 672 673 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 674 { 675 return (unsigned long)__va(pmd_page_paddr(pmd)); 676 } 677 678 /* Find an entry in the third-level page table. */ 679 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 680 681 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 682 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 683 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 684 685 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 686 687 /* use ONLY for statically allocated translation tables */ 688 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 689 690 /* 691 * Conversion functions: convert a page and protection to a page entry, 692 * and a page entry and page directory to the page they refer to. 693 */ 694 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 695 696 #if CONFIG_PGTABLE_LEVELS > 2 697 698 #define pmd_ERROR(e) \ 699 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 700 701 #define pud_none(pud) (!pud_val(pud)) 702 #define pud_bad(pud) (!pud_table(pud)) 703 #define pud_present(pud) pte_present(pud_pte(pud)) 704 #ifndef __PAGETABLE_PMD_FOLDED 705 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 706 #else 707 #define pud_leaf(pud) false 708 #endif 709 #define pud_valid(pud) pte_valid(pud_pte(pud)) 710 #define pud_user(pud) pte_user(pud_pte(pud)) 711 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 712 713 static inline bool pgtable_l4_enabled(void); 714 715 static inline void set_pud(pud_t *pudp, pud_t pud) 716 { 717 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 718 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 719 return; 720 } 721 722 WRITE_ONCE(*pudp, pud); 723 724 if (pud_valid(pud)) { 725 dsb(ishst); 726 isb(); 727 } 728 } 729 730 static inline void pud_clear(pud_t *pudp) 731 { 732 set_pud(pudp, __pud(0)); 733 } 734 735 static inline phys_addr_t pud_page_paddr(pud_t pud) 736 { 737 return __pud_to_phys(pud); 738 } 739 740 static inline pmd_t *pud_pgtable(pud_t pud) 741 { 742 return (pmd_t *)__va(pud_page_paddr(pud)); 743 } 744 745 /* Find an entry in the second-level page table. */ 746 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 747 748 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 749 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 750 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 751 752 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 753 754 /* use ONLY for statically allocated translation tables */ 755 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 756 757 #else 758 759 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 760 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 761 762 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 763 #define pmd_set_fixmap(addr) NULL 764 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 765 #define pmd_clear_fixmap() 766 767 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 768 769 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 770 771 #if CONFIG_PGTABLE_LEVELS > 3 772 773 static __always_inline bool pgtable_l4_enabled(void) 774 { 775 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 776 return true; 777 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 778 return vabits_actual == VA_BITS; 779 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 780 } 781 782 static inline bool mm_pud_folded(const struct mm_struct *mm) 783 { 784 return !pgtable_l4_enabled(); 785 } 786 #define mm_pud_folded mm_pud_folded 787 788 #define pud_ERROR(e) \ 789 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 790 791 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 792 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 793 #define p4d_present(p4d) (!p4d_none(p4d)) 794 795 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 796 { 797 if (in_swapper_pgdir(p4dp)) { 798 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 799 return; 800 } 801 802 WRITE_ONCE(*p4dp, p4d); 803 dsb(ishst); 804 isb(); 805 } 806 807 static inline void p4d_clear(p4d_t *p4dp) 808 { 809 if (pgtable_l4_enabled()) 810 set_p4d(p4dp, __p4d(0)); 811 } 812 813 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 814 { 815 return __p4d_to_phys(p4d); 816 } 817 818 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 819 820 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 821 { 822 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 823 } 824 825 static inline pud_t *p4d_pgtable(p4d_t p4d) 826 { 827 return (pud_t *)__va(p4d_page_paddr(p4d)); 828 } 829 830 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 831 { 832 BUG_ON(!pgtable_l4_enabled()); 833 834 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 835 } 836 837 static inline 838 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 839 { 840 if (!pgtable_l4_enabled()) 841 return p4d_to_folded_pud(p4dp, addr); 842 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 843 } 844 #define pud_offset_lockless pud_offset_lockless 845 846 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 847 { 848 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 849 } 850 #define pud_offset pud_offset 851 852 static inline pud_t *pud_set_fixmap(unsigned long addr) 853 { 854 if (!pgtable_l4_enabled()) 855 return NULL; 856 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 857 } 858 859 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 860 { 861 if (!pgtable_l4_enabled()) 862 return p4d_to_folded_pud(p4dp, addr); 863 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 864 } 865 866 static inline void pud_clear_fixmap(void) 867 { 868 if (pgtable_l4_enabled()) 869 clear_fixmap(FIX_PUD); 870 } 871 872 /* use ONLY for statically allocated translation tables */ 873 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 874 { 875 if (!pgtable_l4_enabled()) 876 return p4d_to_folded_pud(p4dp, addr); 877 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 878 } 879 880 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 881 882 #else 883 884 static inline bool pgtable_l4_enabled(void) { return false; } 885 886 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 887 888 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 889 #define pud_set_fixmap(addr) NULL 890 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 891 #define pud_clear_fixmap() 892 893 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 894 895 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 896 897 #if CONFIG_PGTABLE_LEVELS > 4 898 899 static __always_inline bool pgtable_l5_enabled(void) 900 { 901 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 902 return vabits_actual == VA_BITS; 903 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 904 } 905 906 static inline bool mm_p4d_folded(const struct mm_struct *mm) 907 { 908 return !pgtable_l5_enabled(); 909 } 910 #define mm_p4d_folded mm_p4d_folded 911 912 #define p4d_ERROR(e) \ 913 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 914 915 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 916 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 917 #define pgd_present(pgd) (!pgd_none(pgd)) 918 919 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 920 { 921 if (in_swapper_pgdir(pgdp)) { 922 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 923 return; 924 } 925 926 WRITE_ONCE(*pgdp, pgd); 927 dsb(ishst); 928 isb(); 929 } 930 931 static inline void pgd_clear(pgd_t *pgdp) 932 { 933 if (pgtable_l5_enabled()) 934 set_pgd(pgdp, __pgd(0)); 935 } 936 937 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 938 { 939 return __pgd_to_phys(pgd); 940 } 941 942 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 943 944 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 945 { 946 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 947 } 948 949 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 950 { 951 BUG_ON(!pgtable_l5_enabled()); 952 953 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 954 } 955 956 static inline 957 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 958 { 959 if (!pgtable_l5_enabled()) 960 return pgd_to_folded_p4d(pgdp, addr); 961 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 962 } 963 #define p4d_offset_lockless p4d_offset_lockless 964 965 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 966 { 967 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 968 } 969 970 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 971 { 972 if (!pgtable_l5_enabled()) 973 return NULL; 974 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 975 } 976 977 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 978 { 979 if (!pgtable_l5_enabled()) 980 return pgd_to_folded_p4d(pgdp, addr); 981 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 982 } 983 984 static inline void p4d_clear_fixmap(void) 985 { 986 if (pgtable_l5_enabled()) 987 clear_fixmap(FIX_P4D); 988 } 989 990 /* use ONLY for statically allocated translation tables */ 991 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 992 { 993 if (!pgtable_l5_enabled()) 994 return pgd_to_folded_p4d(pgdp, addr); 995 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 996 } 997 998 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 999 1000 #else 1001 1002 static inline bool pgtable_l5_enabled(void) { return false; } 1003 1004 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1005 #define p4d_set_fixmap(addr) NULL 1006 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1007 #define p4d_clear_fixmap() 1008 1009 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1010 1011 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1012 1013 #define pgd_ERROR(e) \ 1014 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1015 1016 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1017 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1018 1019 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1020 { 1021 /* 1022 * Normal and Normal-Tagged are two different memory types and indices 1023 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1024 */ 1025 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1026 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 1027 PTE_ATTRINDX_MASK; 1028 /* preserve the hardware dirty information */ 1029 if (pte_hw_dirty(pte)) 1030 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1031 1032 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1033 /* 1034 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1035 * dirtiness again. 1036 */ 1037 if (pte_sw_dirty(pte)) 1038 pte = pte_mkdirty(pte); 1039 return pte; 1040 } 1041 1042 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1043 { 1044 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1045 } 1046 1047 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1048 unsigned long address, pte_t *ptep, 1049 pte_t entry, int dirty); 1050 1051 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1052 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1053 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1054 unsigned long address, pmd_t *pmdp, 1055 pmd_t entry, int dirty) 1056 { 1057 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1058 pmd_pte(entry), dirty); 1059 } 1060 1061 static inline int pud_devmap(pud_t pud) 1062 { 1063 return 0; 1064 } 1065 1066 static inline int pgd_devmap(pgd_t pgd) 1067 { 1068 return 0; 1069 } 1070 #endif 1071 1072 #ifdef CONFIG_PAGE_TABLE_CHECK 1073 static inline bool pte_user_accessible_page(pte_t pte) 1074 { 1075 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 1076 } 1077 1078 static inline bool pmd_user_accessible_page(pmd_t pmd) 1079 { 1080 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1081 } 1082 1083 static inline bool pud_user_accessible_page(pud_t pud) 1084 { 1085 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 1086 } 1087 #endif 1088 1089 /* 1090 * Atomic pte/pmd modifications. 1091 */ 1092 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1093 unsigned long address, 1094 pte_t *ptep) 1095 { 1096 pte_t old_pte, pte; 1097 1098 pte = __ptep_get(ptep); 1099 do { 1100 old_pte = pte; 1101 pte = pte_mkold(pte); 1102 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1103 pte_val(old_pte), pte_val(pte)); 1104 } while (pte_val(pte) != pte_val(old_pte)); 1105 1106 return pte_young(pte); 1107 } 1108 1109 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1110 unsigned long address, pte_t *ptep) 1111 { 1112 int young = __ptep_test_and_clear_young(vma, address, ptep); 1113 1114 if (young) { 1115 /* 1116 * We can elide the trailing DSB here since the worst that can 1117 * happen is that a CPU continues to use the young entry in its 1118 * TLB and we mistakenly reclaim the associated page. The 1119 * window for such an event is bounded by the next 1120 * context-switch, which provides a DSB to complete the TLB 1121 * invalidation. 1122 */ 1123 flush_tlb_page_nosync(vma, address); 1124 } 1125 1126 return young; 1127 } 1128 1129 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1130 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1131 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1132 unsigned long address, 1133 pmd_t *pmdp) 1134 { 1135 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1136 } 1137 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1138 1139 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1140 unsigned long address, pte_t *ptep) 1141 { 1142 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1143 1144 page_table_check_pte_clear(mm, pte); 1145 1146 return pte; 1147 } 1148 1149 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1150 pte_t *ptep, unsigned int nr, int full) 1151 { 1152 for (;;) { 1153 __ptep_get_and_clear(mm, addr, ptep); 1154 if (--nr == 0) 1155 break; 1156 ptep++; 1157 addr += PAGE_SIZE; 1158 } 1159 } 1160 1161 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1162 unsigned long addr, pte_t *ptep, 1163 unsigned int nr, int full) 1164 { 1165 pte_t pte, tmp_pte; 1166 1167 pte = __ptep_get_and_clear(mm, addr, ptep); 1168 while (--nr) { 1169 ptep++; 1170 addr += PAGE_SIZE; 1171 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1172 if (pte_dirty(tmp_pte)) 1173 pte = pte_mkdirty(pte); 1174 if (pte_young(tmp_pte)) 1175 pte = pte_mkyoung(pte); 1176 } 1177 return pte; 1178 } 1179 1180 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1181 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1182 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1183 unsigned long address, pmd_t *pmdp) 1184 { 1185 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1186 1187 page_table_check_pmd_clear(mm, pmd); 1188 1189 return pmd; 1190 } 1191 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1192 1193 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1194 unsigned long address, pte_t *ptep, 1195 pte_t pte) 1196 { 1197 pte_t old_pte; 1198 1199 do { 1200 old_pte = pte; 1201 pte = pte_wrprotect(pte); 1202 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1203 pte_val(old_pte), pte_val(pte)); 1204 } while (pte_val(pte) != pte_val(old_pte)); 1205 } 1206 1207 /* 1208 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1209 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1210 */ 1211 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1212 unsigned long address, pte_t *ptep) 1213 { 1214 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1215 } 1216 1217 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1218 pte_t *ptep, unsigned int nr) 1219 { 1220 unsigned int i; 1221 1222 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1223 __ptep_set_wrprotect(mm, address, ptep); 1224 } 1225 1226 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1227 unsigned long addr, pte_t *ptep, 1228 pte_t pte, cydp_t flags) 1229 { 1230 pte_t old_pte; 1231 1232 do { 1233 old_pte = pte; 1234 1235 if (flags & CYDP_CLEAR_YOUNG) 1236 pte = pte_mkold(pte); 1237 if (flags & CYDP_CLEAR_DIRTY) 1238 pte = pte_mkclean(pte); 1239 1240 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1241 pte_val(old_pte), pte_val(pte)); 1242 } while (pte_val(pte) != pte_val(old_pte)); 1243 } 1244 1245 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1246 unsigned long addr, pte_t *ptep, 1247 unsigned int nr, cydp_t flags) 1248 { 1249 pte_t pte; 1250 1251 for (;;) { 1252 pte = __ptep_get(ptep); 1253 1254 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1255 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1256 else 1257 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1258 1259 if (--nr == 0) 1260 break; 1261 ptep++; 1262 addr += PAGE_SIZE; 1263 } 1264 } 1265 1266 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1267 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1268 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1269 unsigned long address, pmd_t *pmdp) 1270 { 1271 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1272 } 1273 1274 #define pmdp_establish pmdp_establish 1275 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1276 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1277 { 1278 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1279 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1280 } 1281 #endif 1282 1283 /* 1284 * Encode and decode a swap entry: 1285 * bits 0-1: present (must be zero) 1286 * bits 2: remember PG_anon_exclusive 1287 * bits 3-7: swap type 1288 * bits 8-57: swap offset 1289 * bit 58: PTE_PROT_NONE (must be zero) 1290 */ 1291 #define __SWP_TYPE_SHIFT 3 1292 #define __SWP_TYPE_BITS 5 1293 #define __SWP_OFFSET_BITS 50 1294 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1295 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1296 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1297 1298 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1299 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1300 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1301 1302 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1303 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1304 1305 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1306 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1307 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1308 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1309 1310 /* 1311 * Ensure that there are not more swap files than can be encoded in the kernel 1312 * PTEs. 1313 */ 1314 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1315 1316 #ifdef CONFIG_ARM64_MTE 1317 1318 #define __HAVE_ARCH_PREPARE_TO_SWAP 1319 extern int arch_prepare_to_swap(struct folio *folio); 1320 1321 #define __HAVE_ARCH_SWAP_INVALIDATE 1322 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1323 { 1324 if (system_supports_mte()) 1325 mte_invalidate_tags(type, offset); 1326 } 1327 1328 static inline void arch_swap_invalidate_area(int type) 1329 { 1330 if (system_supports_mte()) 1331 mte_invalidate_tags_area(type); 1332 } 1333 1334 #define __HAVE_ARCH_SWAP_RESTORE 1335 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1336 1337 #endif /* CONFIG_ARM64_MTE */ 1338 1339 /* 1340 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1341 */ 1342 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1343 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1344 unsigned int nr) 1345 { 1346 /* 1347 * We don't do anything here, so there's a very small chance of 1348 * us retaking a user fault which we just fixed up. The alternative 1349 * is doing a dsb(ishst), but that penalises the fastpath. 1350 */ 1351 } 1352 1353 #define update_mmu_cache(vma, addr, ptep) \ 1354 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1355 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1356 1357 #ifdef CONFIG_ARM64_PA_BITS_52 1358 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1359 #else 1360 #define phys_to_ttbr(addr) (addr) 1361 #endif 1362 1363 /* 1364 * On arm64 without hardware Access Flag, copying from user will fail because 1365 * the pte is old and cannot be marked young. So we always end up with zeroed 1366 * page after fork() + CoW for pfn mappings. We don't always have a 1367 * hardware-managed access flag on arm64. 1368 */ 1369 #define arch_has_hw_pte_young cpu_has_hw_af 1370 1371 /* 1372 * Experimentally, it's cheap to set the access flag in hardware and we 1373 * benefit from prefaulting mappings as 'old' to start with. 1374 */ 1375 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1376 1377 static inline bool pud_sect_supported(void) 1378 { 1379 return PAGE_SIZE == SZ_4K; 1380 } 1381 1382 1383 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1384 #define ptep_modify_prot_start ptep_modify_prot_start 1385 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1386 unsigned long addr, pte_t *ptep); 1387 1388 #define ptep_modify_prot_commit ptep_modify_prot_commit 1389 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1390 unsigned long addr, pte_t *ptep, 1391 pte_t old_pte, pte_t new_pte); 1392 1393 #ifdef CONFIG_ARM64_CONTPTE 1394 1395 /* 1396 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1397 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1398 * a private implementation detail of the public ptep API (see below). 1399 */ 1400 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1401 pte_t *ptep, pte_t pte); 1402 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1403 pte_t *ptep, pte_t pte); 1404 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1405 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1406 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1407 pte_t *ptep, pte_t pte, unsigned int nr); 1408 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1409 pte_t *ptep, unsigned int nr, int full); 1410 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1411 unsigned long addr, pte_t *ptep, 1412 unsigned int nr, int full); 1413 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1414 unsigned long addr, pte_t *ptep); 1415 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1416 unsigned long addr, pte_t *ptep); 1417 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1418 pte_t *ptep, unsigned int nr); 1419 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1420 unsigned long addr, pte_t *ptep, 1421 pte_t entry, int dirty); 1422 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1423 unsigned long addr, pte_t *ptep, 1424 unsigned int nr, cydp_t flags); 1425 1426 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1427 unsigned long addr, pte_t *ptep, pte_t pte) 1428 { 1429 /* 1430 * Only bother trying if both the virtual and physical addresses are 1431 * aligned and correspond to the last entry in a contig range. The core 1432 * code mostly modifies ranges from low to high, so this is the likely 1433 * the last modification in the contig range, so a good time to fold. 1434 * We can't fold special mappings, because there is no associated folio. 1435 */ 1436 1437 const unsigned long contmask = CONT_PTES - 1; 1438 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1439 1440 if (unlikely(valign)) { 1441 bool palign = (pte_pfn(pte) & contmask) == contmask; 1442 1443 if (unlikely(palign && 1444 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1445 __contpte_try_fold(mm, addr, ptep, pte); 1446 } 1447 } 1448 1449 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1450 unsigned long addr, pte_t *ptep, pte_t pte) 1451 { 1452 if (unlikely(pte_valid_cont(pte))) 1453 __contpte_try_unfold(mm, addr, ptep, pte); 1454 } 1455 1456 #define pte_batch_hint pte_batch_hint 1457 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1458 { 1459 if (!pte_valid_cont(pte)) 1460 return 1; 1461 1462 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1463 } 1464 1465 /* 1466 * The below functions constitute the public API that arm64 presents to the 1467 * core-mm to manipulate PTE entries within their page tables (or at least this 1468 * is the subset of the API that arm64 needs to implement). These public 1469 * versions will automatically and transparently apply the contiguous bit where 1470 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1471 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1472 * private versions, which are prefixed with double underscore. All of these 1473 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1474 * held. Although the contiguous bit is considered private to the 1475 * implementation, it is deliberately allowed to leak through the getters (e.g. 1476 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1477 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1478 * its possible a pte will be passed to a setter with the contiguous bit set, so 1479 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1480 * setting it in the pgtable. 1481 */ 1482 1483 #define ptep_get ptep_get 1484 static inline pte_t ptep_get(pte_t *ptep) 1485 { 1486 pte_t pte = __ptep_get(ptep); 1487 1488 if (likely(!pte_valid_cont(pte))) 1489 return pte; 1490 1491 return contpte_ptep_get(ptep, pte); 1492 } 1493 1494 #define ptep_get_lockless ptep_get_lockless 1495 static inline pte_t ptep_get_lockless(pte_t *ptep) 1496 { 1497 pte_t pte = __ptep_get(ptep); 1498 1499 if (likely(!pte_valid_cont(pte))) 1500 return pte; 1501 1502 return contpte_ptep_get_lockless(ptep); 1503 } 1504 1505 static inline void set_pte(pte_t *ptep, pte_t pte) 1506 { 1507 /* 1508 * We don't have the mm or vaddr so cannot unfold contig entries (since 1509 * it requires tlb maintenance). set_pte() is not used in core code, so 1510 * this should never even be called. Regardless do our best to service 1511 * any call and emit a warning if there is any attempt to set a pte on 1512 * top of an existing contig range. 1513 */ 1514 pte_t orig_pte = __ptep_get(ptep); 1515 1516 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1517 __set_pte(ptep, pte_mknoncont(pte)); 1518 } 1519 1520 #define set_ptes set_ptes 1521 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1522 pte_t *ptep, pte_t pte, unsigned int nr) 1523 { 1524 pte = pte_mknoncont(pte); 1525 1526 if (likely(nr == 1)) { 1527 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1528 __set_ptes(mm, addr, ptep, pte, 1); 1529 contpte_try_fold(mm, addr, ptep, pte); 1530 } else { 1531 contpte_set_ptes(mm, addr, ptep, pte, nr); 1532 } 1533 } 1534 1535 static inline void pte_clear(struct mm_struct *mm, 1536 unsigned long addr, pte_t *ptep) 1537 { 1538 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1539 __pte_clear(mm, addr, ptep); 1540 } 1541 1542 #define clear_full_ptes clear_full_ptes 1543 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1544 pte_t *ptep, unsigned int nr, int full) 1545 { 1546 if (likely(nr == 1)) { 1547 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1548 __clear_full_ptes(mm, addr, ptep, nr, full); 1549 } else { 1550 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1551 } 1552 } 1553 1554 #define get_and_clear_full_ptes get_and_clear_full_ptes 1555 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1556 unsigned long addr, pte_t *ptep, 1557 unsigned int nr, int full) 1558 { 1559 pte_t pte; 1560 1561 if (likely(nr == 1)) { 1562 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1563 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1564 } else { 1565 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1566 } 1567 1568 return pte; 1569 } 1570 1571 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1572 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1573 unsigned long addr, pte_t *ptep) 1574 { 1575 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1576 return __ptep_get_and_clear(mm, addr, ptep); 1577 } 1578 1579 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1580 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1581 unsigned long addr, pte_t *ptep) 1582 { 1583 pte_t orig_pte = __ptep_get(ptep); 1584 1585 if (likely(!pte_valid_cont(orig_pte))) 1586 return __ptep_test_and_clear_young(vma, addr, ptep); 1587 1588 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1589 } 1590 1591 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1592 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1593 unsigned long addr, pte_t *ptep) 1594 { 1595 pte_t orig_pte = __ptep_get(ptep); 1596 1597 if (likely(!pte_valid_cont(orig_pte))) 1598 return __ptep_clear_flush_young(vma, addr, ptep); 1599 1600 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1601 } 1602 1603 #define wrprotect_ptes wrprotect_ptes 1604 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1605 unsigned long addr, pte_t *ptep, unsigned int nr) 1606 { 1607 if (likely(nr == 1)) { 1608 /* 1609 * Optimization: wrprotect_ptes() can only be called for present 1610 * ptes so we only need to check contig bit as condition for 1611 * unfold, and we can remove the contig bit from the pte we read 1612 * to avoid re-reading. This speeds up fork() which is sensitive 1613 * for order-0 folios. Equivalent to contpte_try_unfold(). 1614 */ 1615 pte_t orig_pte = __ptep_get(ptep); 1616 1617 if (unlikely(pte_cont(orig_pte))) { 1618 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1619 orig_pte = pte_mknoncont(orig_pte); 1620 } 1621 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1622 } else { 1623 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1624 } 1625 } 1626 1627 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1628 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1629 unsigned long addr, pte_t *ptep) 1630 { 1631 wrprotect_ptes(mm, addr, ptep, 1); 1632 } 1633 1634 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1635 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1636 unsigned long addr, pte_t *ptep, 1637 pte_t entry, int dirty) 1638 { 1639 pte_t orig_pte = __ptep_get(ptep); 1640 1641 entry = pte_mknoncont(entry); 1642 1643 if (likely(!pte_valid_cont(orig_pte))) 1644 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1645 1646 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1647 } 1648 1649 #define clear_young_dirty_ptes clear_young_dirty_ptes 1650 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1651 unsigned long addr, pte_t *ptep, 1652 unsigned int nr, cydp_t flags) 1653 { 1654 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1655 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1656 else 1657 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1658 } 1659 1660 #else /* CONFIG_ARM64_CONTPTE */ 1661 1662 #define ptep_get __ptep_get 1663 #define set_pte __set_pte 1664 #define set_ptes __set_ptes 1665 #define pte_clear __pte_clear 1666 #define clear_full_ptes __clear_full_ptes 1667 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1668 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1669 #define ptep_get_and_clear __ptep_get_and_clear 1670 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1671 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1672 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1673 #define ptep_clear_flush_young __ptep_clear_flush_young 1674 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1675 #define ptep_set_wrprotect __ptep_set_wrprotect 1676 #define wrprotect_ptes __wrprotect_ptes 1677 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1678 #define ptep_set_access_flags __ptep_set_access_flags 1679 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1680 1681 #endif /* CONFIG_ARM64_CONTPTE */ 1682 1683 #endif /* !__ASSEMBLY__ */ 1684 1685 #endif /* __ASM_PGTABLE_H */ 1686