1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * Outside of a few very special situations (e.g. hibernation), we always 55 * use broadcast TLB invalidation instructions, therefore a spurious page 56 * fault on one CPU which has been handled concurrently by another CPU 57 * does not need to perform additional invalidation. 58 */ 59 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 60 61 /* 62 * ZERO_PAGE is a global shared page that is always zero: used 63 * for zero-mapped memory areas etc.. 64 */ 65 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 66 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 70 71 #ifdef CONFIG_ARM64_PA_BITS_52 72 static inline phys_addr_t __pte_to_phys(pte_t pte) 73 { 74 pte_val(pte) &= ~PTE_MAYBE_SHARED; 75 return (pte_val(pte) & PTE_ADDR_LOW) | 76 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 77 } 78 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 79 { 80 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 81 } 82 #else 83 static inline phys_addr_t __pte_to_phys(pte_t pte) 84 { 85 return pte_val(pte) & PTE_ADDR_LOW; 86 } 87 88 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 89 { 90 return phys; 91 } 92 #endif 93 94 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 95 #define pfn_pte(pfn,prot) \ 96 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 97 98 #define pte_none(pte) (!pte_val(pte)) 99 #define __pte_clear(mm, addr, ptep) \ 100 __set_pte(ptep, __pte(0)) 101 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 102 103 /* 104 * The following only work if pte_present(). Undefined behaviour otherwise. 105 */ 106 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 107 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 108 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 109 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 110 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 111 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 112 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 113 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 114 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 115 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 116 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 117 118 #define pte_cont_addr_end(addr, end) \ 119 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 121 }) 122 123 #define pmd_cont_addr_end(addr, end) \ 124 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 125 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 126 }) 127 128 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 129 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 130 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 131 132 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 133 #define pte_present_invalid(pte) \ 134 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 135 /* 136 * Execute-only user mappings do not have the PTE_USER bit set. All valid 137 * kernel mappings have the PTE_UXN bit set. 138 */ 139 #define pte_valid_not_user(pte) \ 140 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 141 /* 142 * Returns true if the pte is valid and has the contiguous bit set. 143 */ 144 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 145 /* 146 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 147 * so that we don't erroneously return false for pages that have been 148 * remapped as PROT_NONE but are yet to be flushed from the TLB. 149 * Note that we can't make any assumptions based on the state of the access 150 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 151 * TLB. 152 */ 153 #define pte_accessible(mm, pte) \ 154 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 155 156 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 157 { 158 u64 por; 159 160 if (!system_supports_poe()) 161 return true; 162 163 por = read_sysreg_s(SYS_POR_EL0); 164 165 if (write) 166 return por_elx_allows_write(por, pkey); 167 168 if (execute) 169 return por_elx_allows_exec(por, pkey); 170 171 return por_elx_allows_read(por, pkey); 172 } 173 174 /* 175 * p??_access_permitted() is true for valid user mappings (PTE_USER 176 * bit set, subject to the write permission check). For execute-only 177 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 178 * not set) must return false. PROT_NONE mappings do not have the 179 * PTE_VALID bit set. 180 */ 181 #define pte_access_permitted_no_overlay(pte, write) \ 182 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 183 #define pte_access_permitted(pte, write) \ 184 (pte_access_permitted_no_overlay(pte, write) && \ 185 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 186 #define pmd_access_permitted(pmd, write) \ 187 (pte_access_permitted(pmd_pte(pmd), (write))) 188 #define pud_access_permitted(pud, write) \ 189 (pte_access_permitted(pud_pte(pud), (write))) 190 191 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 192 { 193 pte_val(pte) &= ~pgprot_val(prot); 194 return pte; 195 } 196 197 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 198 { 199 pte_val(pte) |= pgprot_val(prot); 200 return pte; 201 } 202 203 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 204 { 205 pmd_val(pmd) &= ~pgprot_val(prot); 206 return pmd; 207 } 208 209 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 210 { 211 pmd_val(pmd) |= pgprot_val(prot); 212 return pmd; 213 } 214 215 static inline pte_t pte_mkwrite_novma(pte_t pte) 216 { 217 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 218 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 219 return pte; 220 } 221 222 static inline pte_t pte_mkclean(pte_t pte) 223 { 224 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 225 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 226 227 return pte; 228 } 229 230 static inline pte_t pte_mkdirty(pte_t pte) 231 { 232 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 233 234 if (pte_write(pte)) 235 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 236 237 return pte; 238 } 239 240 static inline pte_t pte_wrprotect(pte_t pte) 241 { 242 /* 243 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 244 * clear), set the PTE_DIRTY bit. 245 */ 246 if (pte_hw_dirty(pte)) 247 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 248 249 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 250 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 251 return pte; 252 } 253 254 static inline pte_t pte_mkold(pte_t pte) 255 { 256 return clear_pte_bit(pte, __pgprot(PTE_AF)); 257 } 258 259 static inline pte_t pte_mkyoung(pte_t pte) 260 { 261 return set_pte_bit(pte, __pgprot(PTE_AF)); 262 } 263 264 static inline pte_t pte_mkspecial(pte_t pte) 265 { 266 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 267 } 268 269 static inline pte_t pte_mkcont(pte_t pte) 270 { 271 return set_pte_bit(pte, __pgprot(PTE_CONT)); 272 } 273 274 static inline pte_t pte_mknoncont(pte_t pte) 275 { 276 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 277 } 278 279 static inline pte_t pte_mkvalid(pte_t pte) 280 { 281 return set_pte_bit(pte, __pgprot(PTE_VALID)); 282 } 283 284 static inline pte_t pte_mkinvalid(pte_t pte) 285 { 286 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 287 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 288 return pte; 289 } 290 291 static inline pmd_t pmd_mkcont(pmd_t pmd) 292 { 293 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 294 } 295 296 static inline pte_t pte_mkdevmap(pte_t pte) 297 { 298 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 299 } 300 301 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 302 static inline int pte_uffd_wp(pte_t pte) 303 { 304 return !!(pte_val(pte) & PTE_UFFD_WP); 305 } 306 307 static inline pte_t pte_mkuffd_wp(pte_t pte) 308 { 309 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 310 } 311 312 static inline pte_t pte_clear_uffd_wp(pte_t pte) 313 { 314 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 315 } 316 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 317 318 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 319 { 320 WRITE_ONCE(*ptep, pte); 321 } 322 323 static inline void __set_pte(pte_t *ptep, pte_t pte) 324 { 325 __set_pte_nosync(ptep, pte); 326 327 /* 328 * Only if the new pte is valid and kernel, otherwise TLB maintenance 329 * or update_mmu_cache() have the necessary barriers. 330 */ 331 if (pte_valid_not_user(pte)) { 332 dsb(ishst); 333 isb(); 334 } 335 } 336 337 static inline pte_t __ptep_get(pte_t *ptep) 338 { 339 return READ_ONCE(*ptep); 340 } 341 342 extern void __sync_icache_dcache(pte_t pteval); 343 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 344 345 /* 346 * PTE bits configuration in the presence of hardware Dirty Bit Management 347 * (PTE_WRITE == PTE_DBM): 348 * 349 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 350 * 0 0 | 1 0 0 351 * 0 1 | 1 1 0 352 * 1 0 | 1 0 1 353 * 1 1 | 0 1 x 354 * 355 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 356 * the page fault mechanism. Checking the dirty status of a pte becomes: 357 * 358 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 359 */ 360 361 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 362 pte_t pte) 363 { 364 pte_t old_pte; 365 366 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 367 return; 368 369 old_pte = __ptep_get(ptep); 370 371 if (!pte_valid(old_pte) || !pte_valid(pte)) 372 return; 373 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 374 return; 375 376 /* 377 * Check for potential race with hardware updates of the pte 378 * (__ptep_set_access_flags safely changes valid ptes without going 379 * through an invalid entry). 380 */ 381 VM_WARN_ONCE(!pte_young(pte), 382 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 383 __func__, pte_val(old_pte), pte_val(pte)); 384 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 385 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 386 __func__, pte_val(old_pte), pte_val(pte)); 387 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 388 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 389 __func__, pte_val(old_pte), pte_val(pte)); 390 } 391 392 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 393 { 394 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 395 __sync_icache_dcache(pte); 396 397 /* 398 * If the PTE would provide user space access to the tags associated 399 * with it then ensure that the MTE tags are synchronised. Although 400 * pte_access_permitted_no_overlay() returns false for exec only 401 * mappings, they don't expose tags (instruction fetches don't check 402 * tags). 403 */ 404 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 405 !pte_special(pte) && pte_tagged(pte)) 406 mte_sync_tags(pte, nr_pages); 407 } 408 409 /* 410 * Select all bits except the pfn 411 */ 412 #define pte_pgprot pte_pgprot 413 static inline pgprot_t pte_pgprot(pte_t pte) 414 { 415 unsigned long pfn = pte_pfn(pte); 416 417 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 418 } 419 420 #define pte_advance_pfn pte_advance_pfn 421 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 422 { 423 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 424 } 425 426 static inline void __set_ptes(struct mm_struct *mm, 427 unsigned long __always_unused addr, 428 pte_t *ptep, pte_t pte, unsigned int nr) 429 { 430 page_table_check_ptes_set(mm, ptep, pte, nr); 431 __sync_cache_and_tags(pte, nr); 432 433 for (;;) { 434 __check_safe_pte_update(mm, ptep, pte); 435 __set_pte(ptep, pte); 436 if (--nr == 0) 437 break; 438 ptep++; 439 pte = pte_advance_pfn(pte, 1); 440 } 441 } 442 443 /* 444 * Hugetlb definitions. 445 */ 446 #define HUGE_MAX_HSTATE 4 447 #define HPAGE_SHIFT PMD_SHIFT 448 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 449 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 450 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 451 452 static inline pte_t pgd_pte(pgd_t pgd) 453 { 454 return __pte(pgd_val(pgd)); 455 } 456 457 static inline pte_t p4d_pte(p4d_t p4d) 458 { 459 return __pte(p4d_val(p4d)); 460 } 461 462 static inline pte_t pud_pte(pud_t pud) 463 { 464 return __pte(pud_val(pud)); 465 } 466 467 static inline pud_t pte_pud(pte_t pte) 468 { 469 return __pud(pte_val(pte)); 470 } 471 472 static inline pmd_t pud_pmd(pud_t pud) 473 { 474 return __pmd(pud_val(pud)); 475 } 476 477 static inline pte_t pmd_pte(pmd_t pmd) 478 { 479 return __pte(pmd_val(pmd)); 480 } 481 482 static inline pmd_t pte_pmd(pte_t pte) 483 { 484 return __pmd(pte_val(pte)); 485 } 486 487 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 488 { 489 return __pgprot((pgprot_val(prot) & ~PUD_TYPE_MASK) | PUD_TYPE_SECT); 490 } 491 492 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 493 { 494 return __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); 495 } 496 497 static inline pte_t pte_swp_mkexclusive(pte_t pte) 498 { 499 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 500 } 501 502 static inline int pte_swp_exclusive(pte_t pte) 503 { 504 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 505 } 506 507 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 508 { 509 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 510 } 511 512 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 513 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 514 { 515 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 516 } 517 518 static inline int pte_swp_uffd_wp(pte_t pte) 519 { 520 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 521 } 522 523 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 524 { 525 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 526 } 527 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 528 529 #ifdef CONFIG_NUMA_BALANCING 530 /* 531 * See the comment in include/linux/pgtable.h 532 */ 533 static inline int pte_protnone(pte_t pte) 534 { 535 /* 536 * pte_present_invalid() tells us that the pte is invalid from HW 537 * perspective but present from SW perspective, so the fields are to be 538 * interpretted as per the HW layout. The second 2 checks are the unique 539 * encoding that we use for PROT_NONE. It is insufficient to only use 540 * the first check because we share the same encoding scheme with pmds 541 * which support pmd_mkinvalid(), so can be present-invalid without 542 * being PROT_NONE. 543 */ 544 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 545 } 546 547 static inline int pmd_protnone(pmd_t pmd) 548 { 549 return pte_protnone(pmd_pte(pmd)); 550 } 551 #endif 552 553 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 554 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 555 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 556 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 557 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 558 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 559 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 560 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 561 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 562 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 563 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 564 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 565 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 566 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 567 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 568 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 569 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 570 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 571 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 572 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 573 #define pmd_swp_clear_uffd_wp(pmd) \ 574 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 575 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 576 577 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 578 579 static inline pmd_t pmd_mkhuge(pmd_t pmd) 580 { 581 /* 582 * It's possible that the pmd is present-invalid on entry 583 * and in that case it needs to remain present-invalid on 584 * exit. So ensure the VALID bit does not get modified. 585 */ 586 pmdval_t mask = PMD_TYPE_MASK & ~PTE_VALID; 587 pmdval_t val = PMD_TYPE_SECT & ~PTE_VALID; 588 589 return __pmd((pmd_val(pmd) & ~mask) | val); 590 } 591 592 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 593 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 594 #endif 595 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 596 { 597 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 598 } 599 600 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 601 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 602 static inline pmd_t pmd_mkspecial(pmd_t pmd) 603 { 604 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 605 } 606 #endif 607 608 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 609 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 610 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 611 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 612 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 613 614 #define pud_young(pud) pte_young(pud_pte(pud)) 615 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 616 #define pud_write(pud) pte_write(pud_pte(pud)) 617 618 static inline pud_t pud_mkhuge(pud_t pud) 619 { 620 /* 621 * It's possible that the pud is present-invalid on entry 622 * and in that case it needs to remain present-invalid on 623 * exit. So ensure the VALID bit does not get modified. 624 */ 625 pudval_t mask = PUD_TYPE_MASK & ~PTE_VALID; 626 pudval_t val = PUD_TYPE_SECT & ~PTE_VALID; 627 628 return __pud((pud_val(pud) & ~mask) | val); 629 } 630 631 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 632 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 633 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 634 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 635 636 #define pmd_pgprot pmd_pgprot 637 static inline pgprot_t pmd_pgprot(pmd_t pmd) 638 { 639 unsigned long pfn = pmd_pfn(pmd); 640 641 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 642 } 643 644 #define pud_pgprot pud_pgprot 645 static inline pgprot_t pud_pgprot(pud_t pud) 646 { 647 unsigned long pfn = pud_pfn(pud); 648 649 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 650 } 651 652 static inline void __set_pte_at(struct mm_struct *mm, 653 unsigned long __always_unused addr, 654 pte_t *ptep, pte_t pte, unsigned int nr) 655 { 656 __sync_cache_and_tags(pte, nr); 657 __check_safe_pte_update(mm, ptep, pte); 658 __set_pte(ptep, pte); 659 } 660 661 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 662 pmd_t *pmdp, pmd_t pmd) 663 { 664 page_table_check_pmd_set(mm, pmdp, pmd); 665 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 666 PMD_SIZE >> PAGE_SHIFT); 667 } 668 669 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 670 pud_t *pudp, pud_t pud) 671 { 672 page_table_check_pud_set(mm, pudp, pud); 673 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 674 PUD_SIZE >> PAGE_SHIFT); 675 } 676 677 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 678 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 679 680 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 681 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 682 683 #define __pgprot_modify(prot,mask,bits) \ 684 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 685 686 #define pgprot_nx(prot) \ 687 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 688 689 #define pgprot_decrypted(prot) \ 690 __pgprot_modify(prot, PROT_NS_SHARED, PROT_NS_SHARED) 691 #define pgprot_encrypted(prot) \ 692 __pgprot_modify(prot, PROT_NS_SHARED, 0) 693 694 /* 695 * Mark the prot value as uncacheable and unbufferable. 696 */ 697 #define pgprot_noncached(prot) \ 698 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 699 #define pgprot_writecombine(prot) \ 700 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 701 #define pgprot_device(prot) \ 702 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 703 #define pgprot_tagged(prot) \ 704 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 705 #define pgprot_mhp pgprot_tagged 706 /* 707 * DMA allocations for non-coherent devices use what the Arm architecture calls 708 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 709 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 710 * is intended for MMIO and thus forbids speculation, preserves access size, 711 * requires strict alignment and can also force write responses to come from the 712 * endpoint. 713 */ 714 #define pgprot_dmacoherent(prot) \ 715 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 716 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 717 718 #define __HAVE_PHYS_MEM_ACCESS_PROT 719 struct file; 720 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 721 unsigned long size, pgprot_t vma_prot); 722 723 #define pmd_none(pmd) (!pmd_val(pmd)) 724 725 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 726 PMD_TYPE_TABLE) 727 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 728 PMD_TYPE_SECT) 729 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 730 #define pmd_bad(pmd) (!pmd_table(pmd)) 731 732 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 733 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 734 735 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 736 static inline int pmd_trans_huge(pmd_t pmd) 737 { 738 /* 739 * If pmd is present-invalid, pmd_table() won't detect it 740 * as a table, so force the valid bit for the comparison. 741 */ 742 return pmd_val(pmd) && pmd_present(pmd) && 743 !pmd_table(__pmd(pmd_val(pmd) | PTE_VALID)); 744 } 745 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 746 747 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 748 static inline bool pud_sect(pud_t pud) { return false; } 749 static inline bool pud_table(pud_t pud) { return true; } 750 #else 751 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 752 PUD_TYPE_SECT) 753 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 754 PUD_TYPE_TABLE) 755 #endif 756 757 extern pgd_t init_pg_dir[]; 758 extern pgd_t init_pg_end[]; 759 extern pgd_t swapper_pg_dir[]; 760 extern pgd_t idmap_pg_dir[]; 761 extern pgd_t tramp_pg_dir[]; 762 extern pgd_t reserved_pg_dir[]; 763 764 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 765 766 static inline bool in_swapper_pgdir(void *addr) 767 { 768 return ((unsigned long)addr & PAGE_MASK) == 769 ((unsigned long)swapper_pg_dir & PAGE_MASK); 770 } 771 772 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 773 { 774 #ifdef __PAGETABLE_PMD_FOLDED 775 if (in_swapper_pgdir(pmdp)) { 776 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 777 return; 778 } 779 #endif /* __PAGETABLE_PMD_FOLDED */ 780 781 WRITE_ONCE(*pmdp, pmd); 782 783 if (pmd_valid(pmd)) { 784 dsb(ishst); 785 isb(); 786 } 787 } 788 789 static inline void pmd_clear(pmd_t *pmdp) 790 { 791 set_pmd(pmdp, __pmd(0)); 792 } 793 794 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 795 { 796 return __pmd_to_phys(pmd); 797 } 798 799 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 800 { 801 return (unsigned long)__va(pmd_page_paddr(pmd)); 802 } 803 804 /* Find an entry in the third-level page table. */ 805 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 806 807 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 808 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 809 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 810 811 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 812 813 /* use ONLY for statically allocated translation tables */ 814 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 815 816 /* 817 * Conversion functions: convert a page and protection to a page entry, 818 * and a page entry and page directory to the page they refer to. 819 */ 820 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 821 822 #if CONFIG_PGTABLE_LEVELS > 2 823 824 #define pmd_ERROR(e) \ 825 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 826 827 #define pud_none(pud) (!pud_val(pud)) 828 #define pud_bad(pud) ((pud_val(pud) & PUD_TYPE_MASK) != \ 829 PUD_TYPE_TABLE) 830 #define pud_present(pud) pte_present(pud_pte(pud)) 831 #ifndef __PAGETABLE_PMD_FOLDED 832 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 833 #else 834 #define pud_leaf(pud) false 835 #endif 836 #define pud_valid(pud) pte_valid(pud_pte(pud)) 837 #define pud_user(pud) pte_user(pud_pte(pud)) 838 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 839 840 static inline bool pgtable_l4_enabled(void); 841 842 static inline void set_pud(pud_t *pudp, pud_t pud) 843 { 844 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 845 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 846 return; 847 } 848 849 WRITE_ONCE(*pudp, pud); 850 851 if (pud_valid(pud)) { 852 dsb(ishst); 853 isb(); 854 } 855 } 856 857 static inline void pud_clear(pud_t *pudp) 858 { 859 set_pud(pudp, __pud(0)); 860 } 861 862 static inline phys_addr_t pud_page_paddr(pud_t pud) 863 { 864 return __pud_to_phys(pud); 865 } 866 867 static inline pmd_t *pud_pgtable(pud_t pud) 868 { 869 return (pmd_t *)__va(pud_page_paddr(pud)); 870 } 871 872 /* Find an entry in the second-level page table. */ 873 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 874 875 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 876 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 877 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 878 879 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 880 881 /* use ONLY for statically allocated translation tables */ 882 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 883 884 #else 885 886 #define pud_valid(pud) false 887 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 888 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 889 890 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 891 #define pmd_set_fixmap(addr) NULL 892 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 893 #define pmd_clear_fixmap() 894 895 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 896 897 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 898 899 #if CONFIG_PGTABLE_LEVELS > 3 900 901 static __always_inline bool pgtable_l4_enabled(void) 902 { 903 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 904 return true; 905 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 906 return vabits_actual == VA_BITS; 907 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 908 } 909 910 static inline bool mm_pud_folded(const struct mm_struct *mm) 911 { 912 return !pgtable_l4_enabled(); 913 } 914 #define mm_pud_folded mm_pud_folded 915 916 #define pud_ERROR(e) \ 917 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 918 919 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 920 #define p4d_bad(p4d) (pgtable_l4_enabled() && \ 921 ((p4d_val(p4d) & P4D_TYPE_MASK) != \ 922 P4D_TYPE_TABLE)) 923 #define p4d_present(p4d) (!p4d_none(p4d)) 924 925 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 926 { 927 if (in_swapper_pgdir(p4dp)) { 928 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 929 return; 930 } 931 932 WRITE_ONCE(*p4dp, p4d); 933 dsb(ishst); 934 isb(); 935 } 936 937 static inline void p4d_clear(p4d_t *p4dp) 938 { 939 if (pgtable_l4_enabled()) 940 set_p4d(p4dp, __p4d(0)); 941 } 942 943 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 944 { 945 return __p4d_to_phys(p4d); 946 } 947 948 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 949 950 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 951 { 952 /* Ensure that 'p4dp' indexes a page table according to 'addr' */ 953 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D); 954 955 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 956 } 957 958 static inline pud_t *p4d_pgtable(p4d_t p4d) 959 { 960 return (pud_t *)__va(p4d_page_paddr(p4d)); 961 } 962 963 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 964 { 965 BUG_ON(!pgtable_l4_enabled()); 966 967 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 968 } 969 970 static inline 971 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 972 { 973 if (!pgtable_l4_enabled()) 974 return p4d_to_folded_pud(p4dp, addr); 975 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 976 } 977 #define pud_offset_lockless pud_offset_lockless 978 979 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 980 { 981 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 982 } 983 #define pud_offset pud_offset 984 985 static inline pud_t *pud_set_fixmap(unsigned long addr) 986 { 987 if (!pgtable_l4_enabled()) 988 return NULL; 989 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 990 } 991 992 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 993 { 994 if (!pgtable_l4_enabled()) 995 return p4d_to_folded_pud(p4dp, addr); 996 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 997 } 998 999 static inline void pud_clear_fixmap(void) 1000 { 1001 if (pgtable_l4_enabled()) 1002 clear_fixmap(FIX_PUD); 1003 } 1004 1005 /* use ONLY for statically allocated translation tables */ 1006 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 1007 { 1008 if (!pgtable_l4_enabled()) 1009 return p4d_to_folded_pud(p4dp, addr); 1010 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 1011 } 1012 1013 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 1014 1015 #else 1016 1017 static inline bool pgtable_l4_enabled(void) { return false; } 1018 1019 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 1020 1021 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 1022 #define pud_set_fixmap(addr) NULL 1023 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 1024 #define pud_clear_fixmap() 1025 1026 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 1027 1028 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1029 1030 #if CONFIG_PGTABLE_LEVELS > 4 1031 1032 static __always_inline bool pgtable_l5_enabled(void) 1033 { 1034 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1035 return vabits_actual == VA_BITS; 1036 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1037 } 1038 1039 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1040 { 1041 return !pgtable_l5_enabled(); 1042 } 1043 #define mm_p4d_folded mm_p4d_folded 1044 1045 #define p4d_ERROR(e) \ 1046 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1047 1048 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1049 #define pgd_bad(pgd) (pgtable_l5_enabled() && \ 1050 ((pgd_val(pgd) & PGD_TYPE_MASK) != \ 1051 PGD_TYPE_TABLE)) 1052 #define pgd_present(pgd) (!pgd_none(pgd)) 1053 1054 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1055 { 1056 if (in_swapper_pgdir(pgdp)) { 1057 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1058 return; 1059 } 1060 1061 WRITE_ONCE(*pgdp, pgd); 1062 dsb(ishst); 1063 isb(); 1064 } 1065 1066 static inline void pgd_clear(pgd_t *pgdp) 1067 { 1068 if (pgtable_l5_enabled()) 1069 set_pgd(pgdp, __pgd(0)); 1070 } 1071 1072 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1073 { 1074 return __pgd_to_phys(pgd); 1075 } 1076 1077 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1078 1079 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1080 { 1081 /* Ensure that 'pgdp' indexes a page table according to 'addr' */ 1082 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD); 1083 1084 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1085 } 1086 1087 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1088 { 1089 BUG_ON(!pgtable_l5_enabled()); 1090 1091 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1092 } 1093 1094 static inline 1095 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1096 { 1097 if (!pgtable_l5_enabled()) 1098 return pgd_to_folded_p4d(pgdp, addr); 1099 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1100 } 1101 #define p4d_offset_lockless p4d_offset_lockless 1102 1103 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1104 { 1105 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1106 } 1107 1108 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1109 { 1110 if (!pgtable_l5_enabled()) 1111 return NULL; 1112 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1113 } 1114 1115 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1116 { 1117 if (!pgtable_l5_enabled()) 1118 return pgd_to_folded_p4d(pgdp, addr); 1119 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1120 } 1121 1122 static inline void p4d_clear_fixmap(void) 1123 { 1124 if (pgtable_l5_enabled()) 1125 clear_fixmap(FIX_P4D); 1126 } 1127 1128 /* use ONLY for statically allocated translation tables */ 1129 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1130 { 1131 if (!pgtable_l5_enabled()) 1132 return pgd_to_folded_p4d(pgdp, addr); 1133 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1134 } 1135 1136 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1137 1138 #else 1139 1140 static inline bool pgtable_l5_enabled(void) { return false; } 1141 1142 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1143 1144 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1145 #define p4d_set_fixmap(addr) NULL 1146 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1147 #define p4d_clear_fixmap() 1148 1149 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1150 1151 static inline 1152 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1153 { 1154 /* 1155 * With runtime folding of the pud, pud_offset_lockless() passes 1156 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1157 * will offset the pointer assuming that it points into 1158 * a page-table page. However, the fast GUP path passes us a 1159 * pgd_t allocated on the stack and so we must use the original 1160 * pointer in 'pgdp' to construct the p4d pointer instead of 1161 * using the generic p4d_offset_lockless() implementation. 1162 * 1163 * Note: reusing the original pointer means that we may 1164 * dereference the same (live) page-table entry multiple times. 1165 * This is safe because it is still only loaded once in the 1166 * context of each level and the CPU guarantees same-address 1167 * read-after-read ordering. 1168 */ 1169 return p4d_offset(pgdp, addr); 1170 } 1171 #define p4d_offset_lockless p4d_offset_lockless_folded 1172 1173 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1174 1175 #define pgd_ERROR(e) \ 1176 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1177 1178 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1179 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1180 1181 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1182 { 1183 /* 1184 * Normal and Normal-Tagged are two different memory types and indices 1185 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1186 */ 1187 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1188 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1189 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1190 1191 /* preserve the hardware dirty information */ 1192 if (pte_hw_dirty(pte)) 1193 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1194 1195 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1196 /* 1197 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1198 * dirtiness again. 1199 */ 1200 if (pte_sw_dirty(pte)) 1201 pte = pte_mkdirty(pte); 1202 return pte; 1203 } 1204 1205 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1206 { 1207 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1208 } 1209 1210 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1211 unsigned long address, pte_t *ptep, 1212 pte_t entry, int dirty); 1213 1214 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1215 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1216 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1217 unsigned long address, pmd_t *pmdp, 1218 pmd_t entry, int dirty) 1219 { 1220 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1221 pmd_pte(entry), dirty); 1222 } 1223 1224 static inline int pud_devmap(pud_t pud) 1225 { 1226 return 0; 1227 } 1228 1229 static inline int pgd_devmap(pgd_t pgd) 1230 { 1231 return 0; 1232 } 1233 #endif 1234 1235 #ifdef CONFIG_PAGE_TABLE_CHECK 1236 static inline bool pte_user_accessible_page(pte_t pte) 1237 { 1238 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1239 } 1240 1241 static inline bool pmd_user_accessible_page(pmd_t pmd) 1242 { 1243 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1244 } 1245 1246 static inline bool pud_user_accessible_page(pud_t pud) 1247 { 1248 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1249 } 1250 #endif 1251 1252 /* 1253 * Atomic pte/pmd modifications. 1254 */ 1255 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1256 unsigned long address, 1257 pte_t *ptep) 1258 { 1259 pte_t old_pte, pte; 1260 1261 pte = __ptep_get(ptep); 1262 do { 1263 old_pte = pte; 1264 pte = pte_mkold(pte); 1265 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1266 pte_val(old_pte), pte_val(pte)); 1267 } while (pte_val(pte) != pte_val(old_pte)); 1268 1269 return pte_young(pte); 1270 } 1271 1272 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1273 unsigned long address, pte_t *ptep) 1274 { 1275 int young = __ptep_test_and_clear_young(vma, address, ptep); 1276 1277 if (young) { 1278 /* 1279 * We can elide the trailing DSB here since the worst that can 1280 * happen is that a CPU continues to use the young entry in its 1281 * TLB and we mistakenly reclaim the associated page. The 1282 * window for such an event is bounded by the next 1283 * context-switch, which provides a DSB to complete the TLB 1284 * invalidation. 1285 */ 1286 flush_tlb_page_nosync(vma, address); 1287 } 1288 1289 return young; 1290 } 1291 1292 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 1293 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1294 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1295 unsigned long address, 1296 pmd_t *pmdp) 1297 { 1298 /* Operation applies to PMD table entry only if FEAT_HAFT is enabled */ 1299 VM_WARN_ON(pmd_table(READ_ONCE(*pmdp)) && !system_supports_haft()); 1300 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1301 } 1302 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 1303 1304 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1305 unsigned long address, pte_t *ptep) 1306 { 1307 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1308 1309 page_table_check_pte_clear(mm, pte); 1310 1311 return pte; 1312 } 1313 1314 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1315 pte_t *ptep, unsigned int nr, int full) 1316 { 1317 for (;;) { 1318 __ptep_get_and_clear(mm, addr, ptep); 1319 if (--nr == 0) 1320 break; 1321 ptep++; 1322 addr += PAGE_SIZE; 1323 } 1324 } 1325 1326 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1327 unsigned long addr, pte_t *ptep, 1328 unsigned int nr, int full) 1329 { 1330 pte_t pte, tmp_pte; 1331 1332 pte = __ptep_get_and_clear(mm, addr, ptep); 1333 while (--nr) { 1334 ptep++; 1335 addr += PAGE_SIZE; 1336 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1337 if (pte_dirty(tmp_pte)) 1338 pte = pte_mkdirty(pte); 1339 if (pte_young(tmp_pte)) 1340 pte = pte_mkyoung(pte); 1341 } 1342 return pte; 1343 } 1344 1345 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1346 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1347 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1348 unsigned long address, pmd_t *pmdp) 1349 { 1350 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1351 1352 page_table_check_pmd_clear(mm, pmd); 1353 1354 return pmd; 1355 } 1356 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1357 1358 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1359 unsigned long address, pte_t *ptep, 1360 pte_t pte) 1361 { 1362 pte_t old_pte; 1363 1364 do { 1365 old_pte = pte; 1366 pte = pte_wrprotect(pte); 1367 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1368 pte_val(old_pte), pte_val(pte)); 1369 } while (pte_val(pte) != pte_val(old_pte)); 1370 } 1371 1372 /* 1373 * __ptep_set_wrprotect - mark read-only while transferring potential hardware 1374 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1375 */ 1376 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1377 unsigned long address, pte_t *ptep) 1378 { 1379 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1380 } 1381 1382 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1383 pte_t *ptep, unsigned int nr) 1384 { 1385 unsigned int i; 1386 1387 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1388 __ptep_set_wrprotect(mm, address, ptep); 1389 } 1390 1391 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1392 unsigned long addr, pte_t *ptep, 1393 pte_t pte, cydp_t flags) 1394 { 1395 pte_t old_pte; 1396 1397 do { 1398 old_pte = pte; 1399 1400 if (flags & CYDP_CLEAR_YOUNG) 1401 pte = pte_mkold(pte); 1402 if (flags & CYDP_CLEAR_DIRTY) 1403 pte = pte_mkclean(pte); 1404 1405 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1406 pte_val(old_pte), pte_val(pte)); 1407 } while (pte_val(pte) != pte_val(old_pte)); 1408 } 1409 1410 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1411 unsigned long addr, pte_t *ptep, 1412 unsigned int nr, cydp_t flags) 1413 { 1414 pte_t pte; 1415 1416 for (;;) { 1417 pte = __ptep_get(ptep); 1418 1419 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1420 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1421 else 1422 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1423 1424 if (--nr == 0) 1425 break; 1426 ptep++; 1427 addr += PAGE_SIZE; 1428 } 1429 } 1430 1431 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1432 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1433 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1434 unsigned long address, pmd_t *pmdp) 1435 { 1436 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1437 } 1438 1439 #define pmdp_establish pmdp_establish 1440 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1441 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1442 { 1443 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1444 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1445 } 1446 #endif 1447 1448 /* 1449 * Encode and decode a swap entry: 1450 * bits 0-1: present (must be zero) 1451 * bits 2: remember PG_anon_exclusive 1452 * bit 3: remember uffd-wp state 1453 * bits 6-10: swap type 1454 * bit 11: PTE_PRESENT_INVALID (must be zero) 1455 * bits 12-61: swap offset 1456 */ 1457 #define __SWP_TYPE_SHIFT 6 1458 #define __SWP_TYPE_BITS 5 1459 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1460 #define __SWP_OFFSET_SHIFT 12 1461 #define __SWP_OFFSET_BITS 50 1462 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1463 1464 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1465 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1466 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1467 1468 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1469 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1470 1471 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1472 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1473 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1474 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1475 1476 /* 1477 * Ensure that there are not more swap files than can be encoded in the kernel 1478 * PTEs. 1479 */ 1480 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1481 1482 #ifdef CONFIG_ARM64_MTE 1483 1484 #define __HAVE_ARCH_PREPARE_TO_SWAP 1485 extern int arch_prepare_to_swap(struct folio *folio); 1486 1487 #define __HAVE_ARCH_SWAP_INVALIDATE 1488 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1489 { 1490 if (system_supports_mte()) 1491 mte_invalidate_tags(type, offset); 1492 } 1493 1494 static inline void arch_swap_invalidate_area(int type) 1495 { 1496 if (system_supports_mte()) 1497 mte_invalidate_tags_area(type); 1498 } 1499 1500 #define __HAVE_ARCH_SWAP_RESTORE 1501 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1502 1503 #endif /* CONFIG_ARM64_MTE */ 1504 1505 /* 1506 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1507 */ 1508 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1509 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1510 unsigned int nr) 1511 { 1512 /* 1513 * We don't do anything here, so there's a very small chance of 1514 * us retaking a user fault which we just fixed up. The alternative 1515 * is doing a dsb(ishst), but that penalises the fastpath. 1516 */ 1517 } 1518 1519 #define update_mmu_cache(vma, addr, ptep) \ 1520 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1521 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1522 1523 #ifdef CONFIG_ARM64_PA_BITS_52 1524 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1525 #else 1526 #define phys_to_ttbr(addr) (addr) 1527 #endif 1528 1529 /* 1530 * On arm64 without hardware Access Flag, copying from user will fail because 1531 * the pte is old and cannot be marked young. So we always end up with zeroed 1532 * page after fork() + CoW for pfn mappings. We don't always have a 1533 * hardware-managed access flag on arm64. 1534 */ 1535 #define arch_has_hw_pte_young cpu_has_hw_af 1536 1537 #ifdef CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG 1538 #define arch_has_hw_nonleaf_pmd_young system_supports_haft 1539 #endif 1540 1541 /* 1542 * Experimentally, it's cheap to set the access flag in hardware and we 1543 * benefit from prefaulting mappings as 'old' to start with. 1544 */ 1545 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1546 1547 static inline bool pud_sect_supported(void) 1548 { 1549 return PAGE_SIZE == SZ_4K; 1550 } 1551 1552 1553 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1554 #define ptep_modify_prot_start ptep_modify_prot_start 1555 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1556 unsigned long addr, pte_t *ptep); 1557 1558 #define ptep_modify_prot_commit ptep_modify_prot_commit 1559 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1560 unsigned long addr, pte_t *ptep, 1561 pte_t old_pte, pte_t new_pte); 1562 1563 #ifdef CONFIG_ARM64_CONTPTE 1564 1565 /* 1566 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1567 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1568 * a private implementation detail of the public ptep API (see below). 1569 */ 1570 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1571 pte_t *ptep, pte_t pte); 1572 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1573 pte_t *ptep, pte_t pte); 1574 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1575 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1576 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1577 pte_t *ptep, pte_t pte, unsigned int nr); 1578 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1579 pte_t *ptep, unsigned int nr, int full); 1580 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1581 unsigned long addr, pte_t *ptep, 1582 unsigned int nr, int full); 1583 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1584 unsigned long addr, pte_t *ptep); 1585 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1586 unsigned long addr, pte_t *ptep); 1587 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1588 pte_t *ptep, unsigned int nr); 1589 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1590 unsigned long addr, pte_t *ptep, 1591 pte_t entry, int dirty); 1592 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1593 unsigned long addr, pte_t *ptep, 1594 unsigned int nr, cydp_t flags); 1595 1596 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1597 unsigned long addr, pte_t *ptep, pte_t pte) 1598 { 1599 /* 1600 * Only bother trying if both the virtual and physical addresses are 1601 * aligned and correspond to the last entry in a contig range. The core 1602 * code mostly modifies ranges from low to high, so this is the likely 1603 * the last modification in the contig range, so a good time to fold. 1604 * We can't fold special mappings, because there is no associated folio. 1605 */ 1606 1607 const unsigned long contmask = CONT_PTES - 1; 1608 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1609 1610 if (unlikely(valign)) { 1611 bool palign = (pte_pfn(pte) & contmask) == contmask; 1612 1613 if (unlikely(palign && 1614 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1615 __contpte_try_fold(mm, addr, ptep, pte); 1616 } 1617 } 1618 1619 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1620 unsigned long addr, pte_t *ptep, pte_t pte) 1621 { 1622 if (unlikely(pte_valid_cont(pte))) 1623 __contpte_try_unfold(mm, addr, ptep, pte); 1624 } 1625 1626 #define pte_batch_hint pte_batch_hint 1627 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1628 { 1629 if (!pte_valid_cont(pte)) 1630 return 1; 1631 1632 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1633 } 1634 1635 /* 1636 * The below functions constitute the public API that arm64 presents to the 1637 * core-mm to manipulate PTE entries within their page tables (or at least this 1638 * is the subset of the API that arm64 needs to implement). These public 1639 * versions will automatically and transparently apply the contiguous bit where 1640 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1641 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1642 * private versions, which are prefixed with double underscore. All of these 1643 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1644 * held. Although the contiguous bit is considered private to the 1645 * implementation, it is deliberately allowed to leak through the getters (e.g. 1646 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1647 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1648 * its possible a pte will be passed to a setter with the contiguous bit set, so 1649 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1650 * setting it in the pgtable. 1651 */ 1652 1653 #define ptep_get ptep_get 1654 static inline pte_t ptep_get(pte_t *ptep) 1655 { 1656 pte_t pte = __ptep_get(ptep); 1657 1658 if (likely(!pte_valid_cont(pte))) 1659 return pte; 1660 1661 return contpte_ptep_get(ptep, pte); 1662 } 1663 1664 #define ptep_get_lockless ptep_get_lockless 1665 static inline pte_t ptep_get_lockless(pte_t *ptep) 1666 { 1667 pte_t pte = __ptep_get(ptep); 1668 1669 if (likely(!pte_valid_cont(pte))) 1670 return pte; 1671 1672 return contpte_ptep_get_lockless(ptep); 1673 } 1674 1675 static inline void set_pte(pte_t *ptep, pte_t pte) 1676 { 1677 /* 1678 * We don't have the mm or vaddr so cannot unfold contig entries (since 1679 * it requires tlb maintenance). set_pte() is not used in core code, so 1680 * this should never even be called. Regardless do our best to service 1681 * any call and emit a warning if there is any attempt to set a pte on 1682 * top of an existing contig range. 1683 */ 1684 pte_t orig_pte = __ptep_get(ptep); 1685 1686 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1687 __set_pte(ptep, pte_mknoncont(pte)); 1688 } 1689 1690 #define set_ptes set_ptes 1691 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1692 pte_t *ptep, pte_t pte, unsigned int nr) 1693 { 1694 pte = pte_mknoncont(pte); 1695 1696 if (likely(nr == 1)) { 1697 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1698 __set_ptes(mm, addr, ptep, pte, 1); 1699 contpte_try_fold(mm, addr, ptep, pte); 1700 } else { 1701 contpte_set_ptes(mm, addr, ptep, pte, nr); 1702 } 1703 } 1704 1705 static inline void pte_clear(struct mm_struct *mm, 1706 unsigned long addr, pte_t *ptep) 1707 { 1708 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1709 __pte_clear(mm, addr, ptep); 1710 } 1711 1712 #define clear_full_ptes clear_full_ptes 1713 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1714 pte_t *ptep, unsigned int nr, int full) 1715 { 1716 if (likely(nr == 1)) { 1717 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1718 __clear_full_ptes(mm, addr, ptep, nr, full); 1719 } else { 1720 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1721 } 1722 } 1723 1724 #define get_and_clear_full_ptes get_and_clear_full_ptes 1725 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1726 unsigned long addr, pte_t *ptep, 1727 unsigned int nr, int full) 1728 { 1729 pte_t pte; 1730 1731 if (likely(nr == 1)) { 1732 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1733 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1734 } else { 1735 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1736 } 1737 1738 return pte; 1739 } 1740 1741 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1742 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1743 unsigned long addr, pte_t *ptep) 1744 { 1745 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1746 return __ptep_get_and_clear(mm, addr, ptep); 1747 } 1748 1749 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1750 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1751 unsigned long addr, pte_t *ptep) 1752 { 1753 pte_t orig_pte = __ptep_get(ptep); 1754 1755 if (likely(!pte_valid_cont(orig_pte))) 1756 return __ptep_test_and_clear_young(vma, addr, ptep); 1757 1758 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1759 } 1760 1761 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1762 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1763 unsigned long addr, pte_t *ptep) 1764 { 1765 pte_t orig_pte = __ptep_get(ptep); 1766 1767 if (likely(!pte_valid_cont(orig_pte))) 1768 return __ptep_clear_flush_young(vma, addr, ptep); 1769 1770 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1771 } 1772 1773 #define wrprotect_ptes wrprotect_ptes 1774 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1775 unsigned long addr, pte_t *ptep, unsigned int nr) 1776 { 1777 if (likely(nr == 1)) { 1778 /* 1779 * Optimization: wrprotect_ptes() can only be called for present 1780 * ptes so we only need to check contig bit as condition for 1781 * unfold, and we can remove the contig bit from the pte we read 1782 * to avoid re-reading. This speeds up fork() which is sensitive 1783 * for order-0 folios. Equivalent to contpte_try_unfold(). 1784 */ 1785 pte_t orig_pte = __ptep_get(ptep); 1786 1787 if (unlikely(pte_cont(orig_pte))) { 1788 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1789 orig_pte = pte_mknoncont(orig_pte); 1790 } 1791 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1792 } else { 1793 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1794 } 1795 } 1796 1797 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1798 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1799 unsigned long addr, pte_t *ptep) 1800 { 1801 wrprotect_ptes(mm, addr, ptep, 1); 1802 } 1803 1804 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1805 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1806 unsigned long addr, pte_t *ptep, 1807 pte_t entry, int dirty) 1808 { 1809 pte_t orig_pte = __ptep_get(ptep); 1810 1811 entry = pte_mknoncont(entry); 1812 1813 if (likely(!pte_valid_cont(orig_pte))) 1814 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1815 1816 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1817 } 1818 1819 #define clear_young_dirty_ptes clear_young_dirty_ptes 1820 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1821 unsigned long addr, pte_t *ptep, 1822 unsigned int nr, cydp_t flags) 1823 { 1824 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1825 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1826 else 1827 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1828 } 1829 1830 #else /* CONFIG_ARM64_CONTPTE */ 1831 1832 #define ptep_get __ptep_get 1833 #define set_pte __set_pte 1834 #define set_ptes __set_ptes 1835 #define pte_clear __pte_clear 1836 #define clear_full_ptes __clear_full_ptes 1837 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1838 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1839 #define ptep_get_and_clear __ptep_get_and_clear 1840 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1841 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1842 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1843 #define ptep_clear_flush_young __ptep_clear_flush_young 1844 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1845 #define ptep_set_wrprotect __ptep_set_wrprotect 1846 #define wrprotect_ptes __wrprotect_ptes 1847 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1848 #define ptep_set_access_flags __ptep_set_access_flags 1849 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1850 1851 #endif /* CONFIG_ARM64_CONTPTE */ 1852 1853 #endif /* !__ASSEMBLY__ */ 1854 1855 #endif /* __ASM_PGTABLE_H */ 1856