1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLER__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 static inline void emit_pte_barriers(void) 44 { 45 /* 46 * These barriers are emitted under certain conditions after a pte entry 47 * was modified (see e.g. __set_pte_complete()). The dsb makes the store 48 * visible to the table walker. The isb ensures that any previous 49 * speculative "invalid translation" marker that is in the CPU's 50 * pipeline gets cleared, so that any access to that address after 51 * setting the pte to valid won't cause a spurious fault. If the thread 52 * gets preempted after storing to the pgtable but before emitting these 53 * barriers, __switch_to() emits a dsb which ensure the walker gets to 54 * see the store. There is no guarantee of an isb being issued though. 55 * This is safe because it will still get issued (albeit on a 56 * potentially different CPU) when the thread starts running again, 57 * before any access to the address. 58 */ 59 dsb(ishst); 60 isb(); 61 } 62 63 static inline void queue_pte_barriers(void) 64 { 65 if (is_lazy_mmu_mode_active()) { 66 /* Avoid the atomic op if already set. */ 67 if (!test_thread_flag(TIF_LAZY_MMU_PENDING)) 68 set_thread_flag(TIF_LAZY_MMU_PENDING); 69 } else { 70 emit_pte_barriers(); 71 } 72 } 73 74 static inline void arch_enter_lazy_mmu_mode(void) {} 75 76 static inline void arch_flush_lazy_mmu_mode(void) 77 { 78 if (test_and_clear_thread_flag(TIF_LAZY_MMU_PENDING)) 79 emit_pte_barriers(); 80 } 81 82 static inline void arch_leave_lazy_mmu_mode(void) 83 { 84 arch_flush_lazy_mmu_mode(); 85 } 86 87 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 88 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 89 90 /* Set stride and tlb_level in flush_*_tlb_range */ 91 #define flush_pmd_tlb_range(vma, addr, end) \ 92 __flush_tlb_range(vma, addr, end, PMD_SIZE, 2, TLBF_NONE) 93 #define flush_pud_tlb_range(vma, addr, end) \ 94 __flush_tlb_range(vma, addr, end, PUD_SIZE, 1, TLBF_NONE) 95 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 96 97 /* 98 * We use local TLB invalidation instruction when reusing page in 99 * write protection fault handler to avoid TLBI broadcast in the hot 100 * path. This will cause spurious page faults if stale read-only TLB 101 * entries exist. 102 */ 103 #define flush_tlb_fix_spurious_fault(vma, address, ptep) \ 104 __flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY) 105 106 #define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp) \ 107 __flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2, \ 108 TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE) 109 110 #define pte_ERROR(e) \ 111 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 112 113 #ifdef CONFIG_ARM64_PA_BITS_52 114 static inline phys_addr_t __pte_to_phys(pte_t pte) 115 { 116 pte_val(pte) &= ~PTE_MAYBE_SHARED; 117 return (pte_val(pte) & PTE_ADDR_LOW) | 118 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 119 } 120 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 121 { 122 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 123 } 124 #else 125 static inline phys_addr_t __pte_to_phys(pte_t pte) 126 { 127 return pte_val(pte) & PTE_ADDR_LOW; 128 } 129 130 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 131 { 132 return phys; 133 } 134 #endif 135 136 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 137 #define pfn_pte(pfn,prot) \ 138 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 139 140 #define pte_none(pte) (!pte_val(pte)) 141 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 142 143 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 144 #define pte_present_invalid(pte) \ 145 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 146 147 /* 148 * The following only work if pte_present(). Undefined behaviour otherwise. 149 */ 150 static __always_inline bool pte_present(pte_t pte) 151 { 152 return pte_valid(pte) || pte_present_invalid(pte); 153 } 154 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 155 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 156 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 157 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 158 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 159 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 160 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 161 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 162 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 163 164 #define pte_cont_addr_end(addr, end) \ 165 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 166 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 167 }) 168 169 #define pmd_cont_addr_end(addr, end) \ 170 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 171 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 172 }) 173 174 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 175 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 176 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 177 178 /* 179 * Execute-only user mappings do not have the PTE_USER bit set. All valid 180 * kernel mappings have the PTE_UXN bit set. 181 */ 182 #define pte_valid_not_user(pte) \ 183 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 184 /* 185 * Returns true if the pte is valid and has the contiguous bit set. 186 */ 187 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 188 /* 189 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 190 * so that we don't erroneously return false for pages that have been 191 * remapped as PROT_NONE but are yet to be flushed from the TLB. 192 * Note that we can't make any assumptions based on the state of the access 193 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 194 * TLB. 195 */ 196 #define pte_accessible(mm, pte) \ 197 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 198 199 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 200 { 201 u64 por; 202 203 if (!system_supports_poe()) 204 return true; 205 206 por = read_sysreg_s(SYS_POR_EL0); 207 208 if (write) 209 return por_elx_allows_write(por, pkey); 210 211 if (execute) 212 return por_elx_allows_exec(por, pkey); 213 214 return por_elx_allows_read(por, pkey); 215 } 216 217 /* 218 * p??_access_permitted() is true for valid user mappings (PTE_USER 219 * bit set, subject to the write permission check). For execute-only 220 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 221 * not set) must return false. PROT_NONE mappings do not have the 222 * PTE_VALID bit set. 223 */ 224 #define pte_access_permitted_no_overlay(pte, write) \ 225 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 226 #define pte_access_permitted(pte, write) \ 227 (pte_access_permitted_no_overlay(pte, write) && \ 228 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 229 #define pmd_access_permitted(pmd, write) \ 230 (pte_access_permitted(pmd_pte(pmd), (write))) 231 #define pud_access_permitted(pud, write) \ 232 (pte_access_permitted(pud_pte(pud), (write))) 233 234 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 235 { 236 pte_val(pte) &= ~pgprot_val(prot); 237 return pte; 238 } 239 240 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 241 { 242 pte_val(pte) |= pgprot_val(prot); 243 return pte; 244 } 245 246 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 247 { 248 pmd_val(pmd) &= ~pgprot_val(prot); 249 return pmd; 250 } 251 252 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 253 { 254 pmd_val(pmd) |= pgprot_val(prot); 255 return pmd; 256 } 257 258 static inline pte_t pte_mkwrite_novma(pte_t pte) 259 { 260 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 261 if (pte_sw_dirty(pte)) 262 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 263 return pte; 264 } 265 266 static inline pte_t pte_mkclean(pte_t pte) 267 { 268 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 269 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 270 271 return pte; 272 } 273 274 static inline pte_t pte_mkdirty(pte_t pte) 275 { 276 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 277 278 if (pte_write(pte)) 279 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 280 281 return pte; 282 } 283 284 static inline pte_t pte_wrprotect(pte_t pte) 285 { 286 /* 287 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 288 * clear), set the PTE_DIRTY bit. 289 */ 290 if (pte_hw_dirty(pte)) 291 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 292 293 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 294 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 295 return pte; 296 } 297 298 static inline pte_t pte_mkold(pte_t pte) 299 { 300 return clear_pte_bit(pte, __pgprot(PTE_AF)); 301 } 302 303 static inline pte_t pte_mkyoung(pte_t pte) 304 { 305 return set_pte_bit(pte, __pgprot(PTE_AF)); 306 } 307 308 static inline pte_t pte_mkspecial(pte_t pte) 309 { 310 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 311 } 312 313 static inline pte_t pte_mkcont(pte_t pte) 314 { 315 return set_pte_bit(pte, __pgprot(PTE_CONT)); 316 } 317 318 static inline pte_t pte_mknoncont(pte_t pte) 319 { 320 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 321 } 322 323 static inline pte_t pte_mkvalid_k(pte_t pte) 324 { 325 pte = clear_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 326 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_VALID_KERNEL)); 327 return pte; 328 } 329 330 static inline pte_t pte_mkinvalid(pte_t pte) 331 { 332 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 333 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 334 return pte; 335 } 336 337 static inline pmd_t pmd_mkcont(pmd_t pmd) 338 { 339 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 340 } 341 342 static inline pmd_t pmd_mknoncont(pmd_t pmd) 343 { 344 return __pmd(pmd_val(pmd) & ~PMD_SECT_CONT); 345 } 346 347 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 348 static inline int pte_uffd_wp(pte_t pte) 349 { 350 return !!(pte_val(pte) & PTE_UFFD_WP); 351 } 352 353 static inline pte_t pte_mkuffd_wp(pte_t pte) 354 { 355 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 356 } 357 358 static inline pte_t pte_clear_uffd_wp(pte_t pte) 359 { 360 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 361 } 362 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 363 364 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 365 { 366 WRITE_ONCE(*ptep, pte); 367 } 368 369 static inline void __set_pte_complete(pte_t pte) 370 { 371 /* 372 * Only if the new pte is valid and kernel, otherwise TLB maintenance 373 * has the necessary barriers. 374 */ 375 if (pte_valid_not_user(pte)) 376 queue_pte_barriers(); 377 } 378 379 static inline void __set_pte(pte_t *ptep, pte_t pte) 380 { 381 __set_pte_nosync(ptep, pte); 382 __set_pte_complete(pte); 383 } 384 385 static inline pte_t __ptep_get(pte_t *ptep) 386 { 387 return READ_ONCE(*ptep); 388 } 389 390 extern void __sync_icache_dcache(pte_t pteval); 391 bool pgattr_change_is_safe(pteval_t old, pteval_t new); 392 393 /* 394 * PTE bits configuration in the presence of hardware Dirty Bit Management 395 * (PTE_WRITE == PTE_DBM): 396 * 397 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 398 * 0 0 | 1 0 0 399 * 0 1 | 1 1 0 400 * 1 0 | 1 0 1 401 * 1 1 | 0 1 x 402 * 403 * When hardware DBM is not present, the software PTE_DIRTY bit is updated via 404 * the page fault mechanism. Checking the dirty status of a pte becomes: 405 * 406 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 407 */ 408 409 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 410 pte_t pte) 411 { 412 pte_t old_pte; 413 414 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 415 return; 416 417 old_pte = __ptep_get(ptep); 418 419 if (!pte_valid(old_pte) || !pte_valid(pte)) 420 return; 421 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 422 return; 423 424 /* 425 * Check for potential race with hardware updates of the pte 426 * (__ptep_set_access_flags safely changes valid ptes without going 427 * through an invalid entry). 428 */ 429 VM_WARN_ONCE(!pte_young(pte), 430 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 431 __func__, pte_val(old_pte), pte_val(pte)); 432 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 433 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 434 __func__, pte_val(old_pte), pte_val(pte)); 435 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 436 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 437 __func__, pte_val(old_pte), pte_val(pte)); 438 } 439 440 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 441 { 442 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 443 __sync_icache_dcache(pte); 444 445 /* 446 * If the PTE would provide user space access to the tags associated 447 * with it then ensure that the MTE tags are synchronised. Although 448 * pte_access_permitted_no_overlay() returns false for exec only 449 * mappings, they don't expose tags (instruction fetches don't check 450 * tags). 451 */ 452 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 453 !pte_special(pte) && pte_tagged(pte)) 454 mte_sync_tags(pte, nr_pages); 455 } 456 457 /* 458 * Select all bits except the pfn 459 */ 460 #define pte_pgprot pte_pgprot 461 static inline pgprot_t pte_pgprot(pte_t pte) 462 { 463 unsigned long pfn = pte_pfn(pte); 464 465 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 466 } 467 468 #define pte_advance_pfn pte_advance_pfn 469 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 470 { 471 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 472 } 473 474 /* 475 * Hugetlb definitions. 476 */ 477 #define HUGE_MAX_HSTATE 4 478 #define HPAGE_SHIFT PMD_SHIFT 479 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 480 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 481 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 482 483 static inline pte_t pgd_pte(pgd_t pgd) 484 { 485 return __pte(pgd_val(pgd)); 486 } 487 488 static inline pte_t p4d_pte(p4d_t p4d) 489 { 490 return __pte(p4d_val(p4d)); 491 } 492 493 static inline pte_t pud_pte(pud_t pud) 494 { 495 return __pte(pud_val(pud)); 496 } 497 498 static inline pud_t pte_pud(pte_t pte) 499 { 500 return __pud(pte_val(pte)); 501 } 502 503 static inline pmd_t pud_pmd(pud_t pud) 504 { 505 return __pmd(pud_val(pud)); 506 } 507 508 static inline pte_t pmd_pte(pmd_t pmd) 509 { 510 return __pte(pmd_val(pmd)); 511 } 512 513 static inline pmd_t pte_pmd(pte_t pte) 514 { 515 return __pmd(pte_val(pte)); 516 } 517 518 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 519 { 520 return __pgprot((pgprot_val(prot) & ~PUD_TYPE_MASK) | PUD_TYPE_SECT); 521 } 522 523 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 524 { 525 return __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT); 526 } 527 528 static inline pte_t pte_swp_mkexclusive(pte_t pte) 529 { 530 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 531 } 532 533 static inline bool pte_swp_exclusive(pte_t pte) 534 { 535 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 536 } 537 538 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 539 { 540 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 541 } 542 543 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 544 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 545 { 546 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 547 } 548 549 static inline int pte_swp_uffd_wp(pte_t pte) 550 { 551 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 552 } 553 554 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 555 { 556 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 557 } 558 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 559 560 #ifdef CONFIG_NUMA_BALANCING 561 /* 562 * See the comment in include/linux/pgtable.h 563 */ 564 static inline int pte_protnone(pte_t pte) 565 { 566 /* 567 * pte_present_invalid() tells us that the pte is invalid from HW 568 * perspective but present from SW perspective, so the fields are to be 569 * interpreted as per the HW layout. The second 2 checks are the unique 570 * encoding that we use for PROT_NONE. It is insufficient to only use 571 * the first check because we share the same encoding scheme with pmds 572 * which support pmd_mkinvalid(), so can be present-invalid without 573 * being PROT_NONE. 574 */ 575 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 576 } 577 578 static inline int pmd_protnone(pmd_t pmd) 579 { 580 return pte_protnone(pmd_pte(pmd)); 581 } 582 #endif 583 584 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 585 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 586 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 587 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 588 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 589 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 590 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 591 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 592 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 593 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 594 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 595 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 596 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 597 #define pmd_mkvalid_k(pmd) pte_pmd(pte_mkvalid_k(pmd_pte(pmd))) 598 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 599 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 600 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 601 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 602 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 603 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 604 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 605 #define pmd_swp_clear_uffd_wp(pmd) \ 606 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 607 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 608 609 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 610 611 static inline pmd_t pmd_mkhuge(pmd_t pmd) 612 { 613 /* 614 * It's possible that the pmd is present-invalid on entry 615 * and in that case it needs to remain present-invalid on 616 * exit. So ensure the VALID bit does not get modified. 617 */ 618 pmdval_t mask = PMD_TYPE_MASK & ~PTE_VALID; 619 pmdval_t val = PMD_TYPE_SECT & ~PTE_VALID; 620 621 return __pmd((pmd_val(pmd) & ~mask) | val); 622 } 623 624 #ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP 625 #define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL))) 626 static inline pmd_t pmd_mkspecial(pmd_t pmd) 627 { 628 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL)); 629 } 630 #endif 631 632 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 633 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 634 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 635 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 636 637 #define pud_young(pud) pte_young(pud_pte(pud)) 638 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 639 #define pud_mkwrite_novma(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) 640 #define pud_mkvalid_k(pud) pte_pud(pte_mkvalid_k(pud_pte(pud))) 641 #define pud_write(pud) pte_write(pud_pte(pud)) 642 643 static inline pud_t pud_mkhuge(pud_t pud) 644 { 645 /* 646 * It's possible that the pud is present-invalid on entry 647 * and in that case it needs to remain present-invalid on 648 * exit. So ensure the VALID bit does not get modified. 649 */ 650 pudval_t mask = PUD_TYPE_MASK & ~PTE_VALID; 651 pudval_t val = PUD_TYPE_SECT & ~PTE_VALID; 652 653 return __pud((pud_val(pud) & ~mask) | val); 654 } 655 656 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 657 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 658 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 659 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 660 661 #define pmd_pgprot pmd_pgprot 662 static inline pgprot_t pmd_pgprot(pmd_t pmd) 663 { 664 unsigned long pfn = pmd_pfn(pmd); 665 666 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd)); 667 } 668 669 #define pud_pgprot pud_pgprot 670 static inline pgprot_t pud_pgprot(pud_t pud) 671 { 672 unsigned long pfn = pud_pfn(pud); 673 674 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud)); 675 } 676 677 static inline void __set_ptes_anysz(struct mm_struct *mm, unsigned long addr, 678 pte_t *ptep, pte_t pte, unsigned int nr, 679 unsigned long pgsize) 680 { 681 unsigned long stride = pgsize >> PAGE_SHIFT; 682 683 switch (pgsize) { 684 case PAGE_SIZE: 685 page_table_check_ptes_set(mm, addr, ptep, pte, nr); 686 break; 687 case PMD_SIZE: 688 page_table_check_pmds_set(mm, addr, (pmd_t *)ptep, 689 pte_pmd(pte), nr); 690 break; 691 #ifndef __PAGETABLE_PMD_FOLDED 692 case PUD_SIZE: 693 page_table_check_puds_set(mm, addr, (pud_t *)ptep, 694 pte_pud(pte), nr); 695 break; 696 #endif 697 default: 698 VM_WARN_ON(1); 699 } 700 701 __sync_cache_and_tags(pte, nr * stride); 702 703 for (;;) { 704 __check_safe_pte_update(mm, ptep, pte); 705 __set_pte_nosync(ptep, pte); 706 if (--nr == 0) 707 break; 708 ptep++; 709 pte = pte_advance_pfn(pte, stride); 710 } 711 712 __set_pte_complete(pte); 713 } 714 715 static inline void __set_ptes(struct mm_struct *mm, unsigned long addr, 716 pte_t *ptep, pte_t pte, unsigned int nr) 717 { 718 __set_ptes_anysz(mm, addr, ptep, pte, nr, PAGE_SIZE); 719 } 720 721 static inline void __set_pmds(struct mm_struct *mm, unsigned long addr, 722 pmd_t *pmdp, pmd_t pmd, unsigned int nr) 723 { 724 __set_ptes_anysz(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), nr, PMD_SIZE); 725 } 726 #define set_pmd_at(mm, addr, pmdp, pmd) __set_pmds(mm, addr, pmdp, pmd, 1) 727 728 static inline void __set_puds(struct mm_struct *mm, unsigned long addr, 729 pud_t *pudp, pud_t pud, unsigned int nr) 730 { 731 __set_ptes_anysz(mm, addr, (pte_t *)pudp, pud_pte(pud), nr, PUD_SIZE); 732 } 733 #define set_pud_at(mm, addr, pudp, pud) __set_puds(mm, addr, pudp, pud, 1) 734 735 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 736 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 737 738 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 739 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 740 741 #define __pgprot_modify(prot,mask,bits) \ 742 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 743 744 #define pgprot_nx(prot) \ 745 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 746 747 #define pgprot_decrypted(prot) \ 748 __pgprot_modify(prot, PROT_NS_SHARED, PROT_NS_SHARED) 749 #define pgprot_encrypted(prot) \ 750 __pgprot_modify(prot, PROT_NS_SHARED, 0) 751 752 /* 753 * Mark the prot value as uncacheable and unbufferable. 754 */ 755 #define pgprot_noncached(prot) \ 756 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 757 #define pgprot_writecombine(prot) \ 758 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 759 #define pgprot_device(prot) \ 760 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 761 #define pgprot_tagged(prot) \ 762 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 763 #define pgprot_mhp pgprot_tagged 764 /* 765 * DMA allocations for non-coherent devices use what the Arm architecture calls 766 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 767 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 768 * is intended for MMIO and thus forbids speculation, preserves access size, 769 * requires strict alignment and can also force write responses to come from the 770 * endpoint. 771 */ 772 #define pgprot_dmacoherent(prot) \ 773 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 774 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 775 776 #define __HAVE_PHYS_MEM_ACCESS_PROT 777 struct file; 778 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 779 unsigned long size, pgprot_t vma_prot); 780 781 #define pmd_none(pmd) (!pmd_val(pmd)) 782 783 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 784 PMD_TYPE_TABLE) 785 786 #define pmd_leaf pmd_leaf 787 static inline bool pmd_leaf(pmd_t pmd) 788 { 789 return pmd_present(pmd) && !pmd_table(pmd); 790 } 791 792 #define pmd_bad(pmd) (!pmd_table(pmd)) 793 794 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 795 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 796 797 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 798 static inline int pmd_trans_huge(pmd_t pmd) 799 { 800 /* 801 * If pmd is present-invalid, pmd_table() won't detect it 802 * as a table, so force the valid bit for the comparison. 803 */ 804 return pmd_present(pmd) && !pmd_table(__pmd(pmd_val(pmd) | PTE_VALID)); 805 } 806 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 807 808 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 809 static inline bool pud_table(pud_t pud) { return true; } 810 #else 811 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 812 PUD_TYPE_TABLE) 813 #endif 814 815 extern pgd_t swapper_pg_dir[]; 816 extern pgd_t idmap_pg_dir[]; 817 extern pgd_t tramp_pg_dir[]; 818 extern pgd_t reserved_pg_dir[]; 819 820 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 821 822 static inline bool in_swapper_pgdir(void *addr) 823 { 824 return ((unsigned long)addr & PAGE_MASK) == 825 ((unsigned long)swapper_pg_dir & PAGE_MASK); 826 } 827 828 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 829 { 830 #ifdef __PAGETABLE_PMD_FOLDED 831 if (in_swapper_pgdir(pmdp)) { 832 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 833 return; 834 } 835 #endif /* __PAGETABLE_PMD_FOLDED */ 836 837 WRITE_ONCE(*pmdp, pmd); 838 839 if (pmd_valid(pmd)) 840 queue_pte_barriers(); 841 } 842 843 static inline void pmd_clear(pmd_t *pmdp) 844 { 845 set_pmd(pmdp, __pmd(0)); 846 } 847 848 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 849 { 850 return __pmd_to_phys(pmd); 851 } 852 853 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 854 { 855 return (unsigned long)__va(pmd_page_paddr(pmd)); 856 } 857 858 /* Find an entry in the third-level page table. */ 859 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 860 861 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 862 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 863 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 864 865 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 866 867 /* use ONLY for statically allocated translation tables */ 868 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 869 870 #if CONFIG_PGTABLE_LEVELS > 2 871 872 #define pmd_ERROR(e) \ 873 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 874 875 #define pud_none(pud) (!pud_val(pud)) 876 #define pud_bad(pud) ((pud_val(pud) & PUD_TYPE_MASK) != \ 877 PUD_TYPE_TABLE) 878 #define pud_present(pud) pte_present(pud_pte(pud)) 879 #ifndef __PAGETABLE_PMD_FOLDED 880 #define pud_leaf pud_leaf 881 static inline bool pud_leaf(pud_t pud) 882 { 883 return pud_present(pud) && !pud_table(pud); 884 } 885 #else 886 #define pud_leaf(pud) false 887 #endif 888 #define pud_valid(pud) pte_valid(pud_pte(pud)) 889 #define pud_user(pud) pte_user(pud_pte(pud)) 890 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 891 892 static inline bool pgtable_l4_enabled(void); 893 894 static inline void set_pud(pud_t *pudp, pud_t pud) 895 { 896 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 897 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 898 return; 899 } 900 901 WRITE_ONCE(*pudp, pud); 902 903 if (pud_valid(pud)) 904 queue_pte_barriers(); 905 } 906 907 static inline void pud_clear(pud_t *pudp) 908 { 909 set_pud(pudp, __pud(0)); 910 } 911 912 static inline phys_addr_t pud_page_paddr(pud_t pud) 913 { 914 return __pud_to_phys(pud); 915 } 916 917 static inline pmd_t *pud_pgtable(pud_t pud) 918 { 919 return (pmd_t *)__va(pud_page_paddr(pud)); 920 } 921 922 /* Find an entry in the second-level page table. */ 923 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 924 925 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 926 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 927 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 928 929 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 930 931 /* use ONLY for statically allocated translation tables */ 932 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 933 934 #else 935 936 #define pud_valid(pud) false 937 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 938 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 939 940 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 941 #define pmd_set_fixmap(addr) NULL 942 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 943 #define pmd_clear_fixmap() 944 945 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 946 947 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 948 949 #if CONFIG_PGTABLE_LEVELS > 3 950 951 static __always_inline bool pgtable_l4_enabled(void) 952 { 953 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 954 return true; 955 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 956 return vabits_actual == VA_BITS; 957 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 958 } 959 960 static inline bool mm_pud_folded(const struct mm_struct *mm) 961 { 962 return !pgtable_l4_enabled(); 963 } 964 #define mm_pud_folded mm_pud_folded 965 966 #define pud_ERROR(e) \ 967 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 968 969 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 970 #define p4d_bad(p4d) (pgtable_l4_enabled() && \ 971 ((p4d_val(p4d) & P4D_TYPE_MASK) != \ 972 P4D_TYPE_TABLE)) 973 #define p4d_present(p4d) (!p4d_none(p4d)) 974 975 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 976 { 977 if (in_swapper_pgdir(p4dp)) { 978 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 979 return; 980 } 981 982 WRITE_ONCE(*p4dp, p4d); 983 queue_pte_barriers(); 984 } 985 986 static inline void p4d_clear(p4d_t *p4dp) 987 { 988 if (pgtable_l4_enabled()) 989 set_p4d(p4dp, __p4d(0)); 990 } 991 992 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 993 { 994 return __p4d_to_phys(p4d); 995 } 996 997 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 998 999 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 1000 { 1001 /* Ensure that 'p4dp' indexes a page table according to 'addr' */ 1002 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D); 1003 1004 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 1005 } 1006 1007 static inline pud_t *p4d_pgtable(p4d_t p4d) 1008 { 1009 return (pud_t *)__va(p4d_page_paddr(p4d)); 1010 } 1011 1012 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 1013 { 1014 VM_WARN_ON_ONCE(!pgtable_l4_enabled()); 1015 1016 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 1017 } 1018 1019 static inline 1020 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 1021 { 1022 if (!pgtable_l4_enabled()) 1023 return p4d_to_folded_pud(p4dp, addr); 1024 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 1025 } 1026 #define pud_offset_lockless pud_offset_lockless 1027 1028 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 1029 { 1030 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 1031 } 1032 #define pud_offset pud_offset 1033 1034 static inline pud_t *pud_set_fixmap(unsigned long addr) 1035 { 1036 if (!pgtable_l4_enabled()) 1037 return NULL; 1038 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 1039 } 1040 1041 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 1042 { 1043 if (!pgtable_l4_enabled()) 1044 return p4d_to_folded_pud(p4dp, addr); 1045 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 1046 } 1047 1048 static inline void pud_clear_fixmap(void) 1049 { 1050 if (pgtable_l4_enabled()) 1051 clear_fixmap(FIX_PUD); 1052 } 1053 1054 /* use ONLY for statically allocated translation tables */ 1055 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 1056 { 1057 if (!pgtable_l4_enabled()) 1058 return p4d_to_folded_pud(p4dp, addr); 1059 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 1060 } 1061 1062 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 1063 1064 #else 1065 1066 static inline bool pgtable_l4_enabled(void) { return false; } 1067 1068 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 1069 1070 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 1071 #define pud_set_fixmap(addr) NULL 1072 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 1073 #define pud_clear_fixmap() 1074 1075 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 1076 1077 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 1078 1079 #if CONFIG_PGTABLE_LEVELS > 4 1080 1081 static __always_inline bool pgtable_l5_enabled(void) 1082 { 1083 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 1084 return vabits_actual == VA_BITS; 1085 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 1086 } 1087 1088 static inline bool mm_p4d_folded(const struct mm_struct *mm) 1089 { 1090 return !pgtable_l5_enabled(); 1091 } 1092 #define mm_p4d_folded mm_p4d_folded 1093 1094 #define p4d_ERROR(e) \ 1095 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 1096 1097 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 1098 #define pgd_bad(pgd) (pgtable_l5_enabled() && \ 1099 ((pgd_val(pgd) & PGD_TYPE_MASK) != \ 1100 PGD_TYPE_TABLE)) 1101 #define pgd_present(pgd) (!pgd_none(pgd)) 1102 1103 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 1104 { 1105 if (in_swapper_pgdir(pgdp)) { 1106 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1107 return; 1108 } 1109 1110 WRITE_ONCE(*pgdp, pgd); 1111 queue_pte_barriers(); 1112 } 1113 1114 static inline void pgd_clear(pgd_t *pgdp) 1115 { 1116 if (pgtable_l5_enabled()) 1117 set_pgd(pgdp, __pgd(0)); 1118 } 1119 1120 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1121 { 1122 return __pgd_to_phys(pgd); 1123 } 1124 1125 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1126 1127 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1128 { 1129 /* Ensure that 'pgdp' indexes a page table according to 'addr' */ 1130 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD); 1131 1132 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1133 } 1134 1135 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1136 { 1137 VM_WARN_ON_ONCE(!pgtable_l5_enabled()); 1138 1139 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1140 } 1141 1142 static inline 1143 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1144 { 1145 if (!pgtable_l5_enabled()) 1146 return pgd_to_folded_p4d(pgdp, addr); 1147 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1148 } 1149 #define p4d_offset_lockless p4d_offset_lockless 1150 1151 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1152 { 1153 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1154 } 1155 1156 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1157 { 1158 if (!pgtable_l5_enabled()) 1159 return NULL; 1160 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1161 } 1162 1163 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1164 { 1165 if (!pgtable_l5_enabled()) 1166 return pgd_to_folded_p4d(pgdp, addr); 1167 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1168 } 1169 1170 static inline void p4d_clear_fixmap(void) 1171 { 1172 if (pgtable_l5_enabled()) 1173 clear_fixmap(FIX_P4D); 1174 } 1175 1176 /* use ONLY for statically allocated translation tables */ 1177 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1178 { 1179 if (!pgtable_l5_enabled()) 1180 return pgd_to_folded_p4d(pgdp, addr); 1181 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1182 } 1183 1184 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1185 1186 #else 1187 1188 static inline bool pgtable_l5_enabled(void) { return false; } 1189 1190 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1191 1192 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1193 #define p4d_set_fixmap(addr) NULL 1194 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1195 #define p4d_clear_fixmap() 1196 1197 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1198 1199 static inline 1200 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1201 { 1202 /* 1203 * With runtime folding of the pud, pud_offset_lockless() passes 1204 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1205 * will offset the pointer assuming that it points into 1206 * a page-table page. However, the fast GUP path passes us a 1207 * pgd_t allocated on the stack and so we must use the original 1208 * pointer in 'pgdp' to construct the p4d pointer instead of 1209 * using the generic p4d_offset_lockless() implementation. 1210 * 1211 * Note: reusing the original pointer means that we may 1212 * dereference the same (live) page-table entry multiple times. 1213 * This is safe because it is still only loaded once in the 1214 * context of each level and the CPU guarantees same-address 1215 * read-after-read ordering. 1216 */ 1217 return p4d_offset(pgdp, addr); 1218 } 1219 #define p4d_offset_lockless p4d_offset_lockless_folded 1220 1221 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1222 1223 #define pgd_ERROR(e) \ 1224 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1225 1226 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1227 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1228 1229 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1230 { 1231 /* 1232 * Normal and Normal-Tagged are two different memory types and indices 1233 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1234 */ 1235 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1236 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1237 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1238 1239 /* preserve the hardware dirty information */ 1240 if (pte_hw_dirty(pte)) 1241 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1242 1243 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1244 /* 1245 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1246 * dirtiness again. 1247 */ 1248 if (pte_sw_dirty(pte)) 1249 pte = pte_mkdirty(pte); 1250 return pte; 1251 } 1252 1253 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1254 { 1255 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1256 } 1257 1258 extern int __ptep_set_access_flags_anysz(struct vm_area_struct *vma, 1259 unsigned long address, pte_t *ptep, 1260 pte_t entry, int dirty, 1261 unsigned long pgsize); 1262 1263 static inline int __ptep_set_access_flags(struct vm_area_struct *vma, 1264 unsigned long address, pte_t *ptep, 1265 pte_t entry, int dirty) 1266 { 1267 return __ptep_set_access_flags_anysz(vma, address, ptep, entry, dirty, 1268 PAGE_SIZE); 1269 } 1270 1271 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1272 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1273 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1274 unsigned long address, pmd_t *pmdp, 1275 pmd_t entry, int dirty) 1276 { 1277 return __ptep_set_access_flags_anysz(vma, address, (pte_t *)pmdp, 1278 pmd_pte(entry), dirty, PMD_SIZE); 1279 } 1280 #endif 1281 1282 #ifdef CONFIG_PAGE_TABLE_CHECK 1283 static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte) 1284 { 1285 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1286 } 1287 1288 static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd) 1289 { 1290 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1291 } 1292 1293 static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud) 1294 { 1295 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1296 } 1297 #endif 1298 1299 /* 1300 * Atomic pte/pmd modifications. 1301 */ 1302 1303 static inline void __pte_clear(struct mm_struct *mm, 1304 unsigned long addr, pte_t *ptep) 1305 { 1306 __set_pte(ptep, __pte(0)); 1307 } 1308 1309 static inline bool __ptep_test_and_clear_young(struct vm_area_struct *vma, 1310 unsigned long address, pte_t *ptep) 1311 { 1312 pte_t old_pte, pte; 1313 1314 pte = __ptep_get(ptep); 1315 do { 1316 old_pte = pte; 1317 pte = pte_mkold(pte); 1318 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1319 pte_val(old_pte), pte_val(pte)); 1320 } while (pte_val(pte) != pte_val(old_pte)); 1321 1322 return pte_young(pte); 1323 } 1324 1325 static inline bool __ptep_clear_flush_young(struct vm_area_struct *vma, 1326 unsigned long address, pte_t *ptep) 1327 { 1328 bool young = __ptep_test_and_clear_young(vma, address, ptep); 1329 1330 if (young) { 1331 /* 1332 * We can elide the trailing DSB here since the worst that can 1333 * happen is that a CPU continues to use the young entry in its 1334 * TLB and we mistakenly reclaim the associated page. The 1335 * window for such an event is bounded by the next 1336 * context-switch, which provides a DSB to complete the TLB 1337 * invalidation. 1338 */ 1339 __flush_tlb_page(vma, address, TLBF_NOSYNC); 1340 } 1341 1342 return young; 1343 } 1344 1345 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG) 1346 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1347 static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma, 1348 unsigned long address, pmd_t *pmdp) 1349 { 1350 /* Operation applies to PMD table entry only if FEAT_HAFT is enabled */ 1351 VM_WARN_ON(pmd_table(READ_ONCE(*pmdp)) && !system_supports_haft()); 1352 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1353 } 1354 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */ 1355 1356 static inline pte_t __ptep_get_and_clear_anysz(struct mm_struct *mm, 1357 unsigned long address, 1358 pte_t *ptep, 1359 unsigned long pgsize) 1360 { 1361 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1362 1363 switch (pgsize) { 1364 case PAGE_SIZE: 1365 page_table_check_pte_clear(mm, address, pte); 1366 break; 1367 case PMD_SIZE: 1368 page_table_check_pmd_clear(mm, address, pte_pmd(pte)); 1369 break; 1370 #ifndef __PAGETABLE_PMD_FOLDED 1371 case PUD_SIZE: 1372 page_table_check_pud_clear(mm, address, pte_pud(pte)); 1373 break; 1374 #endif 1375 default: 1376 VM_WARN_ON(1); 1377 } 1378 1379 return pte; 1380 } 1381 1382 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1383 unsigned long address, pte_t *ptep) 1384 { 1385 return __ptep_get_and_clear_anysz(mm, address, ptep, PAGE_SIZE); 1386 } 1387 1388 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1389 pte_t *ptep, unsigned int nr, int full) 1390 { 1391 for (;;) { 1392 __ptep_get_and_clear(mm, addr, ptep); 1393 if (--nr == 0) 1394 break; 1395 ptep++; 1396 addr += PAGE_SIZE; 1397 } 1398 } 1399 1400 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1401 unsigned long addr, pte_t *ptep, 1402 unsigned int nr, int full) 1403 { 1404 pte_t pte, tmp_pte; 1405 1406 pte = __ptep_get_and_clear(mm, addr, ptep); 1407 while (--nr) { 1408 ptep++; 1409 addr += PAGE_SIZE; 1410 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1411 if (pte_dirty(tmp_pte)) 1412 pte = pte_mkdirty(pte); 1413 if (pte_young(tmp_pte)) 1414 pte = pte_mkyoung(pte); 1415 } 1416 return pte; 1417 } 1418 1419 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1420 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1421 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1422 unsigned long address, pmd_t *pmdp) 1423 { 1424 return pte_pmd(__ptep_get_and_clear_anysz(mm, address, (pte_t *)pmdp, PMD_SIZE)); 1425 } 1426 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1427 1428 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1429 unsigned long address, pte_t *ptep, 1430 pte_t pte) 1431 { 1432 pte_t old_pte; 1433 1434 do { 1435 old_pte = pte; 1436 pte = pte_wrprotect(pte); 1437 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1438 pte_val(old_pte), pte_val(pte)); 1439 } while (pte_val(pte) != pte_val(old_pte)); 1440 } 1441 1442 /* 1443 * __ptep_set_wrprotect - mark read-only while transferring potential hardware 1444 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1445 */ 1446 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1447 unsigned long address, pte_t *ptep) 1448 { 1449 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1450 } 1451 1452 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1453 pte_t *ptep, unsigned int nr) 1454 { 1455 unsigned int i; 1456 1457 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1458 __ptep_set_wrprotect(mm, address, ptep); 1459 } 1460 1461 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1462 unsigned long addr, pte_t *ptep, 1463 pte_t pte, cydp_t flags) 1464 { 1465 pte_t old_pte; 1466 1467 do { 1468 old_pte = pte; 1469 1470 if (flags & CYDP_CLEAR_YOUNG) 1471 pte = pte_mkold(pte); 1472 if (flags & CYDP_CLEAR_DIRTY) 1473 pte = pte_mkclean(pte); 1474 1475 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1476 pte_val(old_pte), pte_val(pte)); 1477 } while (pte_val(pte) != pte_val(old_pte)); 1478 } 1479 1480 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1481 unsigned long addr, pte_t *ptep, 1482 unsigned int nr, cydp_t flags) 1483 { 1484 pte_t pte; 1485 1486 for (;;) { 1487 pte = __ptep_get(ptep); 1488 1489 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1490 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1491 else 1492 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1493 1494 if (--nr == 0) 1495 break; 1496 ptep++; 1497 addr += PAGE_SIZE; 1498 } 1499 } 1500 1501 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1502 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1503 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1504 unsigned long address, pmd_t *pmdp) 1505 { 1506 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1507 } 1508 1509 #define pmdp_establish pmdp_establish 1510 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1511 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1512 { 1513 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd); 1514 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1515 } 1516 #endif 1517 1518 /* 1519 * Encode and decode a swap entry: 1520 * bits 0-1: present (must be zero) 1521 * bits 2: remember PG_anon_exclusive 1522 * bit 3: remember uffd-wp state 1523 * bits 6-10: swap type 1524 * bit 11: PTE_PRESENT_INVALID (must be zero) 1525 * bits 12-61: swap offset 1526 */ 1527 #define __SWP_TYPE_SHIFT 6 1528 #define __SWP_TYPE_BITS 5 1529 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1530 #define __SWP_OFFSET_SHIFT 12 1531 #define __SWP_OFFSET_BITS 50 1532 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1533 1534 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1535 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1536 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1537 1538 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1539 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1540 1541 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1542 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1543 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1544 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1545 1546 /* 1547 * Ensure that there are not more swap files than can be encoded in the kernel 1548 * PTEs. 1549 */ 1550 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1551 1552 #ifdef CONFIG_ARM64_MTE 1553 1554 #define __HAVE_ARCH_PREPARE_TO_SWAP 1555 extern int arch_prepare_to_swap(struct folio *folio); 1556 1557 #define __HAVE_ARCH_SWAP_INVALIDATE 1558 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1559 { 1560 if (system_supports_mte()) 1561 mte_invalidate_tags(type, offset); 1562 } 1563 1564 static inline void arch_swap_invalidate_area(int type) 1565 { 1566 if (system_supports_mte()) 1567 mte_invalidate_tags_area(type); 1568 } 1569 1570 #define __HAVE_ARCH_SWAP_RESTORE 1571 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1572 1573 #endif /* CONFIG_ARM64_MTE */ 1574 1575 /* 1576 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1577 */ 1578 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1579 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1580 unsigned int nr) 1581 { 1582 /* 1583 * We don't do anything here, so there's a very small chance of 1584 * us retaking a user fault which we just fixed up. The alternative 1585 * is doing a dsb(ishst), but that penalises the fastpath. 1586 */ 1587 } 1588 1589 #define update_mmu_cache(vma, addr, ptep) \ 1590 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1591 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1592 1593 #ifdef CONFIG_ARM64_PA_BITS_52 1594 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1595 #else 1596 #define phys_to_ttbr(addr) (addr) 1597 #endif 1598 1599 /* 1600 * On arm64 without hardware Access Flag, copying from user will fail because 1601 * the pte is old and cannot be marked young. So we always end up with zeroed 1602 * page after fork() + CoW for pfn mappings. We don't always have a 1603 * hardware-managed access flag on arm64. 1604 */ 1605 #define arch_has_hw_pte_young cpu_has_hw_af 1606 1607 #ifdef CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG 1608 #define arch_has_hw_nonleaf_pmd_young system_supports_haft 1609 #endif 1610 1611 /* 1612 * Experimentally, it's cheap to set the access flag in hardware and we 1613 * benefit from prefaulting mappings as 'old' to start with. 1614 */ 1615 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1616 1617 /* 1618 * Request exec memory is read into pagecache in at least 64K folios. This size 1619 * can be contpte-mapped when 4K base pages are in use (16 pages into 1 iTLB 1620 * entry), and HPA can coalesce it (4 pages into 1 TLB entry) when 16K base 1621 * pages are in use. 1622 */ 1623 #define exec_folio_order() ilog2(SZ_64K >> PAGE_SHIFT) 1624 1625 static inline bool pud_sect_supported(void) 1626 { 1627 return PAGE_SIZE == SZ_4K; 1628 } 1629 1630 1631 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1632 #define ptep_modify_prot_start ptep_modify_prot_start 1633 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1634 unsigned long addr, pte_t *ptep); 1635 1636 #define ptep_modify_prot_commit ptep_modify_prot_commit 1637 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1638 unsigned long addr, pte_t *ptep, 1639 pte_t old_pte, pte_t new_pte); 1640 1641 #define modify_prot_start_ptes modify_prot_start_ptes 1642 extern pte_t modify_prot_start_ptes(struct vm_area_struct *vma, 1643 unsigned long addr, pte_t *ptep, 1644 unsigned int nr); 1645 1646 #define modify_prot_commit_ptes modify_prot_commit_ptes 1647 extern void modify_prot_commit_ptes(struct vm_area_struct *vma, unsigned long addr, 1648 pte_t *ptep, pte_t old_pte, pte_t pte, 1649 unsigned int nr); 1650 1651 #ifdef CONFIG_ARM64_CONTPTE 1652 1653 /* 1654 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1655 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1656 * a private implementation detail of the public ptep API (see below). 1657 */ 1658 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1659 pte_t *ptep, pte_t pte); 1660 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1661 pte_t *ptep, pte_t pte); 1662 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1663 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1664 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1665 pte_t *ptep, pte_t pte, unsigned int nr); 1666 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1667 pte_t *ptep, unsigned int nr, int full); 1668 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1669 unsigned long addr, pte_t *ptep, 1670 unsigned int nr, int full); 1671 bool contpte_test_and_clear_young_ptes(struct vm_area_struct *vma, 1672 unsigned long addr, pte_t *ptep, unsigned int nr); 1673 bool contpte_clear_flush_young_ptes(struct vm_area_struct *vma, 1674 unsigned long addr, pte_t *ptep, unsigned int nr); 1675 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1676 pte_t *ptep, unsigned int nr); 1677 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1678 unsigned long addr, pte_t *ptep, 1679 pte_t entry, int dirty); 1680 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1681 unsigned long addr, pte_t *ptep, 1682 unsigned int nr, cydp_t flags); 1683 1684 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1685 unsigned long addr, pte_t *ptep, pte_t pte) 1686 { 1687 /* 1688 * Only bother trying if both the virtual and physical addresses are 1689 * aligned and correspond to the last entry in a contig range. The core 1690 * code mostly modifies ranges from low to high, so this is the likely 1691 * the last modification in the contig range, so a good time to fold. 1692 * We can't fold special mappings, because there is no associated folio. 1693 */ 1694 1695 const unsigned long contmask = CONT_PTES - 1; 1696 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1697 1698 if (unlikely(valign)) { 1699 bool palign = (pte_pfn(pte) & contmask) == contmask; 1700 1701 if (unlikely(palign && 1702 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1703 __contpte_try_fold(mm, addr, ptep, pte); 1704 } 1705 } 1706 1707 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1708 unsigned long addr, pte_t *ptep, pte_t pte) 1709 { 1710 if (unlikely(pte_valid_cont(pte))) 1711 __contpte_try_unfold(mm, addr, ptep, pte); 1712 } 1713 1714 #define pte_batch_hint pte_batch_hint 1715 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1716 { 1717 if (!pte_valid_cont(pte)) 1718 return 1; 1719 1720 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1721 } 1722 1723 /* 1724 * The below functions constitute the public API that arm64 presents to the 1725 * core-mm to manipulate PTE entries within their page tables (or at least this 1726 * is the subset of the API that arm64 needs to implement). These public 1727 * versions will automatically and transparently apply the contiguous bit where 1728 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1729 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1730 * private versions, which are prefixed with double underscore. All of these 1731 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1732 * held. Although the contiguous bit is considered private to the 1733 * implementation, it is deliberately allowed to leak through the getters (e.g. 1734 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1735 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1736 * its possible a pte will be passed to a setter with the contiguous bit set, so 1737 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1738 * setting it in the pgtable. 1739 */ 1740 1741 #define ptep_get ptep_get 1742 static inline pte_t ptep_get(pte_t *ptep) 1743 { 1744 pte_t pte = __ptep_get(ptep); 1745 1746 if (likely(!pte_valid_cont(pte))) 1747 return pte; 1748 1749 return contpte_ptep_get(ptep, pte); 1750 } 1751 1752 #define ptep_get_lockless ptep_get_lockless 1753 static inline pte_t ptep_get_lockless(pte_t *ptep) 1754 { 1755 pte_t pte = __ptep_get(ptep); 1756 1757 if (likely(!pte_valid_cont(pte))) 1758 return pte; 1759 1760 return contpte_ptep_get_lockless(ptep); 1761 } 1762 1763 static inline void set_pte(pte_t *ptep, pte_t pte) 1764 { 1765 /* 1766 * We don't have the mm or vaddr so cannot unfold contig entries (since 1767 * it requires tlb maintenance). set_pte() is not used in core code, so 1768 * this should never even be called. Regardless do our best to service 1769 * any call and emit a warning if there is any attempt to set a pte on 1770 * top of an existing contig range. 1771 */ 1772 pte_t orig_pte = __ptep_get(ptep); 1773 1774 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1775 __set_pte(ptep, pte_mknoncont(pte)); 1776 } 1777 1778 #define set_ptes set_ptes 1779 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1780 pte_t *ptep, pte_t pte, unsigned int nr) 1781 { 1782 pte = pte_mknoncont(pte); 1783 1784 if (likely(nr == 1)) { 1785 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1786 __set_ptes(mm, addr, ptep, pte, 1); 1787 contpte_try_fold(mm, addr, ptep, pte); 1788 } else { 1789 contpte_set_ptes(mm, addr, ptep, pte, nr); 1790 } 1791 } 1792 1793 static inline void pte_clear(struct mm_struct *mm, 1794 unsigned long addr, pte_t *ptep) 1795 { 1796 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1797 __pte_clear(mm, addr, ptep); 1798 } 1799 1800 #define clear_full_ptes clear_full_ptes 1801 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1802 pte_t *ptep, unsigned int nr, int full) 1803 { 1804 if (likely(nr == 1)) { 1805 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1806 __clear_full_ptes(mm, addr, ptep, nr, full); 1807 } else { 1808 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1809 } 1810 } 1811 1812 #define get_and_clear_full_ptes get_and_clear_full_ptes 1813 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1814 unsigned long addr, pte_t *ptep, 1815 unsigned int nr, int full) 1816 { 1817 pte_t pte; 1818 1819 if (likely(nr == 1)) { 1820 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1821 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1822 } else { 1823 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1824 } 1825 1826 return pte; 1827 } 1828 1829 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1830 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1831 unsigned long addr, pte_t *ptep) 1832 { 1833 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1834 return __ptep_get_and_clear(mm, addr, ptep); 1835 } 1836 1837 static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte) 1838 { 1839 pteval_t old = 0; 1840 1841 if (!try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte))) 1842 return false; 1843 1844 /* 1845 * The store must be complete by the time this returns, but the caller 1846 * may be in lazy MMU mode, where __set_pte_complete() would defer the 1847 * barriers. Issue them directly. 1848 */ 1849 emit_pte_barriers(); 1850 return true; 1851 } 1852 #define ptep_try_set ptep_try_set 1853 1854 /* 1855 * arm64 mandates break-before-make: a cleared kernel PTE must have its TLB 1856 * invalidated before a different page is installed in its place. The broadcast 1857 * TLBI is an instruction, not an IPI, so this is safe with interrupts disabled. 1858 */ 1859 static inline void flush_tlb_before_set(unsigned long addr) 1860 { 1861 flush_tlb_kernel_range(addr, addr + PAGE_SIZE); 1862 } 1863 #define flush_tlb_before_set flush_tlb_before_set 1864 1865 #define test_and_clear_young_ptes test_and_clear_young_ptes 1866 static inline bool test_and_clear_young_ptes(struct vm_area_struct *vma, 1867 unsigned long addr, pte_t *ptep, unsigned int nr) 1868 { 1869 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1870 return __ptep_test_and_clear_young(vma, addr, ptep); 1871 1872 return contpte_test_and_clear_young_ptes(vma, addr, ptep, nr); 1873 } 1874 1875 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1876 static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma, 1877 unsigned long addr, pte_t *ptep) 1878 { 1879 return test_and_clear_young_ptes(vma, addr, ptep, 1); 1880 } 1881 1882 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1883 static inline bool ptep_clear_flush_young(struct vm_area_struct *vma, 1884 unsigned long addr, pte_t *ptep) 1885 { 1886 pte_t orig_pte = __ptep_get(ptep); 1887 1888 if (likely(!pte_valid_cont(orig_pte))) 1889 return __ptep_clear_flush_young(vma, addr, ptep); 1890 1891 return contpte_clear_flush_young_ptes(vma, addr, ptep, 1); 1892 } 1893 1894 #define clear_flush_young_ptes clear_flush_young_ptes 1895 static inline bool clear_flush_young_ptes(struct vm_area_struct *vma, 1896 unsigned long addr, pte_t *ptep, unsigned int nr) 1897 { 1898 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1899 return __ptep_clear_flush_young(vma, addr, ptep); 1900 1901 return contpte_clear_flush_young_ptes(vma, addr, ptep, nr); 1902 } 1903 1904 #define wrprotect_ptes wrprotect_ptes 1905 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1906 unsigned long addr, pte_t *ptep, unsigned int nr) 1907 { 1908 if (likely(nr == 1)) { 1909 /* 1910 * Optimization: wrprotect_ptes() can only be called for present 1911 * ptes so we only need to check contig bit as condition for 1912 * unfold, and we can remove the contig bit from the pte we read 1913 * to avoid re-reading. This speeds up fork() which is sensitive 1914 * for order-0 folios. Equivalent to contpte_try_unfold(). 1915 */ 1916 pte_t orig_pte = __ptep_get(ptep); 1917 1918 if (unlikely(pte_cont(orig_pte))) { 1919 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1920 orig_pte = pte_mknoncont(orig_pte); 1921 } 1922 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1923 } else { 1924 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1925 } 1926 } 1927 1928 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1929 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1930 unsigned long addr, pte_t *ptep) 1931 { 1932 wrprotect_ptes(mm, addr, ptep, 1); 1933 } 1934 1935 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1936 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1937 unsigned long addr, pte_t *ptep, 1938 pte_t entry, int dirty) 1939 { 1940 pte_t orig_pte = __ptep_get(ptep); 1941 1942 entry = pte_mknoncont(entry); 1943 1944 if (likely(!pte_valid_cont(orig_pte))) 1945 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1946 1947 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1948 } 1949 1950 #define clear_young_dirty_ptes clear_young_dirty_ptes 1951 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1952 unsigned long addr, pte_t *ptep, 1953 unsigned int nr, cydp_t flags) 1954 { 1955 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1956 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1957 else 1958 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1959 } 1960 1961 #else /* CONFIG_ARM64_CONTPTE */ 1962 1963 #define ptep_get __ptep_get 1964 #define set_pte __set_pte 1965 #define set_ptes __set_ptes 1966 #define pte_clear __pte_clear 1967 #define clear_full_ptes __clear_full_ptes 1968 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1969 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1970 #define ptep_get_and_clear __ptep_get_and_clear 1971 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1972 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1973 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1974 #define ptep_clear_flush_young __ptep_clear_flush_young 1975 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1976 #define ptep_set_wrprotect __ptep_set_wrprotect 1977 #define wrprotect_ptes __wrprotect_ptes 1978 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1979 #define ptep_set_access_flags __ptep_set_access_flags 1980 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1981 1982 #endif /* CONFIG_ARM64_CONTPTE */ 1983 1984 #endif /* !__ASSEMBLER__ */ 1985 1986 #endif /* __ASM_PGTABLE_H */ 1987