1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 static inline bool arch_thp_swp_supported(void) 53 { 54 return !system_supports_mte(); 55 } 56 #define arch_thp_swp_supported arch_thp_swp_supported 57 58 /* 59 * Outside of a few very special situations (e.g. hibernation), we always 60 * use broadcast TLB invalidation instructions, therefore a spurious page 61 * fault on one CPU which has been handled concurrently by another CPU 62 * does not need to perform additional invalidation. 63 */ 64 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 65 66 /* 67 * ZERO_PAGE is a global shared page that is always zero: used 68 * for zero-mapped memory areas etc.. 69 */ 70 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 71 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 72 73 #define pte_ERROR(e) \ 74 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 75 76 /* 77 * Macros to convert between a physical address and its placement in a 78 * page table entry, taking care of 52-bit addresses. 79 */ 80 #ifdef CONFIG_ARM64_PA_BITS_52 81 static inline phys_addr_t __pte_to_phys(pte_t pte) 82 { 83 pte_val(pte) &= ~PTE_MAYBE_SHARED; 84 return (pte_val(pte) & PTE_ADDR_LOW) | 85 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 86 } 87 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 88 { 89 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 90 } 91 #else 92 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 93 #define __phys_to_pte_val(phys) (phys) 94 #endif 95 96 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 97 #define pfn_pte(pfn,prot) \ 98 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 99 100 #define pte_none(pte) (!pte_val(pte)) 101 #define __pte_clear(mm, addr, ptep) \ 102 __set_pte(ptep, __pte(0)) 103 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 104 105 /* 106 * The following only work if pte_present(). Undefined behaviour otherwise. 107 */ 108 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 109 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 110 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 111 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 112 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 113 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 114 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 115 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 116 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 117 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 118 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 119 120 #define pte_cont_addr_end(addr, end) \ 121 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 122 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123 }) 124 125 #define pmd_cont_addr_end(addr, end) \ 126 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 127 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 128 }) 129 130 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 131 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 132 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 133 134 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 135 /* 136 * Execute-only user mappings do not have the PTE_USER bit set. All valid 137 * kernel mappings have the PTE_UXN bit set. 138 */ 139 #define pte_valid_not_user(pte) \ 140 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 141 /* 142 * Returns true if the pte is valid and has the contiguous bit set. 143 */ 144 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 145 /* 146 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 147 * so that we don't erroneously return false for pages that have been 148 * remapped as PROT_NONE but are yet to be flushed from the TLB. 149 * Note that we can't make any assumptions based on the state of the access 150 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 151 * TLB. 152 */ 153 #define pte_accessible(mm, pte) \ 154 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 155 156 /* 157 * p??_access_permitted() is true for valid user mappings (PTE_USER 158 * bit set, subject to the write permission check). For execute-only 159 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 160 * not set) must return false. PROT_NONE mappings do not have the 161 * PTE_VALID bit set. 162 */ 163 #define pte_access_permitted(pte, write) \ 164 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 165 #define pmd_access_permitted(pmd, write) \ 166 (pte_access_permitted(pmd_pte(pmd), (write))) 167 #define pud_access_permitted(pud, write) \ 168 (pte_access_permitted(pud_pte(pud), (write))) 169 170 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 171 { 172 pte_val(pte) &= ~pgprot_val(prot); 173 return pte; 174 } 175 176 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 177 { 178 pte_val(pte) |= pgprot_val(prot); 179 return pte; 180 } 181 182 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 183 { 184 pmd_val(pmd) &= ~pgprot_val(prot); 185 return pmd; 186 } 187 188 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 189 { 190 pmd_val(pmd) |= pgprot_val(prot); 191 return pmd; 192 } 193 194 static inline pte_t pte_mkwrite_novma(pte_t pte) 195 { 196 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 197 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 198 return pte; 199 } 200 201 static inline pte_t pte_mkclean(pte_t pte) 202 { 203 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 204 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 205 206 return pte; 207 } 208 209 static inline pte_t pte_mkdirty(pte_t pte) 210 { 211 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 212 213 if (pte_write(pte)) 214 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 215 216 return pte; 217 } 218 219 static inline pte_t pte_wrprotect(pte_t pte) 220 { 221 /* 222 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 223 * clear), set the PTE_DIRTY bit. 224 */ 225 if (pte_hw_dirty(pte)) 226 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 227 228 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 229 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 230 return pte; 231 } 232 233 static inline pte_t pte_mkold(pte_t pte) 234 { 235 return clear_pte_bit(pte, __pgprot(PTE_AF)); 236 } 237 238 static inline pte_t pte_mkyoung(pte_t pte) 239 { 240 return set_pte_bit(pte, __pgprot(PTE_AF)); 241 } 242 243 static inline pte_t pte_mkspecial(pte_t pte) 244 { 245 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 246 } 247 248 static inline pte_t pte_mkcont(pte_t pte) 249 { 250 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 251 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 252 } 253 254 static inline pte_t pte_mknoncont(pte_t pte) 255 { 256 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 257 } 258 259 static inline pte_t pte_mkpresent(pte_t pte) 260 { 261 return set_pte_bit(pte, __pgprot(PTE_VALID)); 262 } 263 264 static inline pmd_t pmd_mkcont(pmd_t pmd) 265 { 266 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 267 } 268 269 static inline pte_t pte_mkdevmap(pte_t pte) 270 { 271 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 272 } 273 274 static inline void __set_pte(pte_t *ptep, pte_t pte) 275 { 276 WRITE_ONCE(*ptep, pte); 277 278 /* 279 * Only if the new pte is valid and kernel, otherwise TLB maintenance 280 * or update_mmu_cache() have the necessary barriers. 281 */ 282 if (pte_valid_not_user(pte)) { 283 dsb(ishst); 284 isb(); 285 } 286 } 287 288 static inline pte_t __ptep_get(pte_t *ptep) 289 { 290 return READ_ONCE(*ptep); 291 } 292 293 extern void __sync_icache_dcache(pte_t pteval); 294 bool pgattr_change_is_safe(u64 old, u64 new); 295 296 /* 297 * PTE bits configuration in the presence of hardware Dirty Bit Management 298 * (PTE_WRITE == PTE_DBM): 299 * 300 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 301 * 0 0 | 1 0 0 302 * 0 1 | 1 1 0 303 * 1 0 | 1 0 1 304 * 1 1 | 0 1 x 305 * 306 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 307 * the page fault mechanism. Checking the dirty status of a pte becomes: 308 * 309 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 310 */ 311 312 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 313 pte_t pte) 314 { 315 pte_t old_pte; 316 317 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 318 return; 319 320 old_pte = __ptep_get(ptep); 321 322 if (!pte_valid(old_pte) || !pte_valid(pte)) 323 return; 324 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 325 return; 326 327 /* 328 * Check for potential race with hardware updates of the pte 329 * (__ptep_set_access_flags safely changes valid ptes without going 330 * through an invalid entry). 331 */ 332 VM_WARN_ONCE(!pte_young(pte), 333 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 334 __func__, pte_val(old_pte), pte_val(pte)); 335 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 336 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 337 __func__, pte_val(old_pte), pte_val(pte)); 338 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 339 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 340 __func__, pte_val(old_pte), pte_val(pte)); 341 } 342 343 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 344 { 345 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 346 __sync_icache_dcache(pte); 347 348 /* 349 * If the PTE would provide user space access to the tags associated 350 * with it then ensure that the MTE tags are synchronised. Although 351 * pte_access_permitted() returns false for exec only mappings, they 352 * don't expose tags (instruction fetches don't check tags). 353 */ 354 if (system_supports_mte() && pte_access_permitted(pte, false) && 355 !pte_special(pte) && pte_tagged(pte)) 356 mte_sync_tags(pte, nr_pages); 357 } 358 359 /* 360 * Select all bits except the pfn 361 */ 362 static inline pgprot_t pte_pgprot(pte_t pte) 363 { 364 unsigned long pfn = pte_pfn(pte); 365 366 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 367 } 368 369 #define pte_advance_pfn pte_advance_pfn 370 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 371 { 372 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 373 } 374 375 static inline void __set_ptes(struct mm_struct *mm, 376 unsigned long __always_unused addr, 377 pte_t *ptep, pte_t pte, unsigned int nr) 378 { 379 page_table_check_ptes_set(mm, ptep, pte, nr); 380 __sync_cache_and_tags(pte, nr); 381 382 for (;;) { 383 __check_safe_pte_update(mm, ptep, pte); 384 __set_pte(ptep, pte); 385 if (--nr == 0) 386 break; 387 ptep++; 388 pte = pte_advance_pfn(pte, 1); 389 } 390 } 391 392 /* 393 * Huge pte definitions. 394 */ 395 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 396 397 /* 398 * Hugetlb definitions. 399 */ 400 #define HUGE_MAX_HSTATE 4 401 #define HPAGE_SHIFT PMD_SHIFT 402 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 403 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 404 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 405 406 static inline pte_t pgd_pte(pgd_t pgd) 407 { 408 return __pte(pgd_val(pgd)); 409 } 410 411 static inline pte_t p4d_pte(p4d_t p4d) 412 { 413 return __pte(p4d_val(p4d)); 414 } 415 416 static inline pte_t pud_pte(pud_t pud) 417 { 418 return __pte(pud_val(pud)); 419 } 420 421 static inline pud_t pte_pud(pte_t pte) 422 { 423 return __pud(pte_val(pte)); 424 } 425 426 static inline pmd_t pud_pmd(pud_t pud) 427 { 428 return __pmd(pud_val(pud)); 429 } 430 431 static inline pte_t pmd_pte(pmd_t pmd) 432 { 433 return __pte(pmd_val(pmd)); 434 } 435 436 static inline pmd_t pte_pmd(pte_t pte) 437 { 438 return __pmd(pte_val(pte)); 439 } 440 441 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 442 { 443 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 444 } 445 446 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 447 { 448 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 449 } 450 451 static inline pte_t pte_swp_mkexclusive(pte_t pte) 452 { 453 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 454 } 455 456 static inline int pte_swp_exclusive(pte_t pte) 457 { 458 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 459 } 460 461 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 462 { 463 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 464 } 465 466 #ifdef CONFIG_NUMA_BALANCING 467 /* 468 * See the comment in include/linux/pgtable.h 469 */ 470 static inline int pte_protnone(pte_t pte) 471 { 472 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 473 } 474 475 static inline int pmd_protnone(pmd_t pmd) 476 { 477 return pte_protnone(pmd_pte(pmd)); 478 } 479 #endif 480 481 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 482 483 static inline int pmd_present(pmd_t pmd) 484 { 485 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 486 } 487 488 /* 489 * THP definitions. 490 */ 491 492 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 493 static inline int pmd_trans_huge(pmd_t pmd) 494 { 495 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 496 } 497 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 498 499 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 500 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 501 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 502 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 503 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 504 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 505 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 506 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 507 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 508 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 509 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 510 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 511 512 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 513 { 514 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 515 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 516 517 return pmd; 518 } 519 520 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 521 522 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 523 524 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 525 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 526 #endif 527 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 528 { 529 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 530 } 531 532 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 533 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 534 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 535 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 536 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 537 538 #define pud_young(pud) pte_young(pud_pte(pud)) 539 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 540 #define pud_write(pud) pte_write(pud_pte(pud)) 541 542 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 543 544 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 545 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 546 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 547 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 548 549 static inline void __set_pte_at(struct mm_struct *mm, 550 unsigned long __always_unused addr, 551 pte_t *ptep, pte_t pte, unsigned int nr) 552 { 553 __sync_cache_and_tags(pte, nr); 554 __check_safe_pte_update(mm, ptep, pte); 555 __set_pte(ptep, pte); 556 } 557 558 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 559 pmd_t *pmdp, pmd_t pmd) 560 { 561 page_table_check_pmd_set(mm, pmdp, pmd); 562 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 563 PMD_SIZE >> PAGE_SHIFT); 564 } 565 566 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 567 pud_t *pudp, pud_t pud) 568 { 569 page_table_check_pud_set(mm, pudp, pud); 570 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 571 PUD_SIZE >> PAGE_SHIFT); 572 } 573 574 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 575 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 576 577 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 578 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 579 580 #define __pgprot_modify(prot,mask,bits) \ 581 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 582 583 #define pgprot_nx(prot) \ 584 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 585 586 /* 587 * Mark the prot value as uncacheable and unbufferable. 588 */ 589 #define pgprot_noncached(prot) \ 590 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 591 #define pgprot_writecombine(prot) \ 592 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 593 #define pgprot_device(prot) \ 594 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 595 #define pgprot_tagged(prot) \ 596 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 597 #define pgprot_mhp pgprot_tagged 598 /* 599 * DMA allocations for non-coherent devices use what the Arm architecture calls 600 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 601 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 602 * is intended for MMIO and thus forbids speculation, preserves access size, 603 * requires strict alignment and can also force write responses to come from the 604 * endpoint. 605 */ 606 #define pgprot_dmacoherent(prot) \ 607 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 608 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 609 610 #define __HAVE_PHYS_MEM_ACCESS_PROT 611 struct file; 612 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 613 unsigned long size, pgprot_t vma_prot); 614 615 #define pmd_none(pmd) (!pmd_val(pmd)) 616 617 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 618 PMD_TYPE_TABLE) 619 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 620 PMD_TYPE_SECT) 621 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 622 #define pmd_bad(pmd) (!pmd_table(pmd)) 623 624 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 625 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 626 627 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 628 static inline bool pud_sect(pud_t pud) { return false; } 629 static inline bool pud_table(pud_t pud) { return true; } 630 #else 631 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 632 PUD_TYPE_SECT) 633 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 634 PUD_TYPE_TABLE) 635 #endif 636 637 extern pgd_t init_pg_dir[]; 638 extern pgd_t init_pg_end[]; 639 extern pgd_t swapper_pg_dir[]; 640 extern pgd_t idmap_pg_dir[]; 641 extern pgd_t tramp_pg_dir[]; 642 extern pgd_t reserved_pg_dir[]; 643 644 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 645 646 static inline bool in_swapper_pgdir(void *addr) 647 { 648 return ((unsigned long)addr & PAGE_MASK) == 649 ((unsigned long)swapper_pg_dir & PAGE_MASK); 650 } 651 652 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 653 { 654 #ifdef __PAGETABLE_PMD_FOLDED 655 if (in_swapper_pgdir(pmdp)) { 656 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 657 return; 658 } 659 #endif /* __PAGETABLE_PMD_FOLDED */ 660 661 WRITE_ONCE(*pmdp, pmd); 662 663 if (pmd_valid(pmd)) { 664 dsb(ishst); 665 isb(); 666 } 667 } 668 669 static inline void pmd_clear(pmd_t *pmdp) 670 { 671 set_pmd(pmdp, __pmd(0)); 672 } 673 674 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 675 { 676 return __pmd_to_phys(pmd); 677 } 678 679 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 680 { 681 return (unsigned long)__va(pmd_page_paddr(pmd)); 682 } 683 684 /* Find an entry in the third-level page table. */ 685 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 686 687 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 688 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 689 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 690 691 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 692 693 /* use ONLY for statically allocated translation tables */ 694 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 695 696 /* 697 * Conversion functions: convert a page and protection to a page entry, 698 * and a page entry and page directory to the page they refer to. 699 */ 700 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 701 702 #if CONFIG_PGTABLE_LEVELS > 2 703 704 #define pmd_ERROR(e) \ 705 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 706 707 #define pud_none(pud) (!pud_val(pud)) 708 #define pud_bad(pud) (!pud_table(pud)) 709 #define pud_present(pud) pte_present(pud_pte(pud)) 710 #ifndef __PAGETABLE_PMD_FOLDED 711 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 712 #else 713 #define pud_leaf(pud) false 714 #endif 715 #define pud_valid(pud) pte_valid(pud_pte(pud)) 716 #define pud_user(pud) pte_user(pud_pte(pud)) 717 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 718 719 static inline bool pgtable_l4_enabled(void); 720 721 static inline void set_pud(pud_t *pudp, pud_t pud) 722 { 723 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 724 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 725 return; 726 } 727 728 WRITE_ONCE(*pudp, pud); 729 730 if (pud_valid(pud)) { 731 dsb(ishst); 732 isb(); 733 } 734 } 735 736 static inline void pud_clear(pud_t *pudp) 737 { 738 set_pud(pudp, __pud(0)); 739 } 740 741 static inline phys_addr_t pud_page_paddr(pud_t pud) 742 { 743 return __pud_to_phys(pud); 744 } 745 746 static inline pmd_t *pud_pgtable(pud_t pud) 747 { 748 return (pmd_t *)__va(pud_page_paddr(pud)); 749 } 750 751 /* Find an entry in the second-level page table. */ 752 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 753 754 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 755 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 756 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 757 758 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 759 760 /* use ONLY for statically allocated translation tables */ 761 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 762 763 #else 764 765 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 766 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 767 768 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 769 #define pmd_set_fixmap(addr) NULL 770 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 771 #define pmd_clear_fixmap() 772 773 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 774 775 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 776 777 #if CONFIG_PGTABLE_LEVELS > 3 778 779 static __always_inline bool pgtable_l4_enabled(void) 780 { 781 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 782 return true; 783 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 784 return vabits_actual == VA_BITS; 785 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 786 } 787 788 static inline bool mm_pud_folded(const struct mm_struct *mm) 789 { 790 return !pgtable_l4_enabled(); 791 } 792 #define mm_pud_folded mm_pud_folded 793 794 #define pud_ERROR(e) \ 795 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 796 797 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 798 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 799 #define p4d_present(p4d) (!p4d_none(p4d)) 800 801 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 802 { 803 if (in_swapper_pgdir(p4dp)) { 804 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 805 return; 806 } 807 808 WRITE_ONCE(*p4dp, p4d); 809 dsb(ishst); 810 isb(); 811 } 812 813 static inline void p4d_clear(p4d_t *p4dp) 814 { 815 if (pgtable_l4_enabled()) 816 set_p4d(p4dp, __p4d(0)); 817 } 818 819 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 820 { 821 return __p4d_to_phys(p4d); 822 } 823 824 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 825 826 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 827 { 828 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 829 } 830 831 static inline pud_t *p4d_pgtable(p4d_t p4d) 832 { 833 return (pud_t *)__va(p4d_page_paddr(p4d)); 834 } 835 836 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 837 { 838 BUG_ON(!pgtable_l4_enabled()); 839 840 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 841 } 842 843 static inline 844 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 845 { 846 if (!pgtable_l4_enabled()) 847 return p4d_to_folded_pud(p4dp, addr); 848 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 849 } 850 #define pud_offset_lockless pud_offset_lockless 851 852 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 853 { 854 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 855 } 856 #define pud_offset pud_offset 857 858 static inline pud_t *pud_set_fixmap(unsigned long addr) 859 { 860 if (!pgtable_l4_enabled()) 861 return NULL; 862 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 863 } 864 865 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 866 { 867 if (!pgtable_l4_enabled()) 868 return p4d_to_folded_pud(p4dp, addr); 869 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 870 } 871 872 static inline void pud_clear_fixmap(void) 873 { 874 if (pgtable_l4_enabled()) 875 clear_fixmap(FIX_PUD); 876 } 877 878 /* use ONLY for statically allocated translation tables */ 879 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 880 { 881 if (!pgtable_l4_enabled()) 882 return p4d_to_folded_pud(p4dp, addr); 883 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 884 } 885 886 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 887 888 #else 889 890 static inline bool pgtable_l4_enabled(void) { return false; } 891 892 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 893 894 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 895 #define pud_set_fixmap(addr) NULL 896 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 897 #define pud_clear_fixmap() 898 899 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 900 901 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 902 903 #if CONFIG_PGTABLE_LEVELS > 4 904 905 static __always_inline bool pgtable_l5_enabled(void) 906 { 907 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 908 return vabits_actual == VA_BITS; 909 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 910 } 911 912 static inline bool mm_p4d_folded(const struct mm_struct *mm) 913 { 914 return !pgtable_l5_enabled(); 915 } 916 #define mm_p4d_folded mm_p4d_folded 917 918 #define p4d_ERROR(e) \ 919 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 920 921 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 922 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 923 #define pgd_present(pgd) (!pgd_none(pgd)) 924 925 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 926 { 927 if (in_swapper_pgdir(pgdp)) { 928 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 929 return; 930 } 931 932 WRITE_ONCE(*pgdp, pgd); 933 dsb(ishst); 934 isb(); 935 } 936 937 static inline void pgd_clear(pgd_t *pgdp) 938 { 939 if (pgtable_l5_enabled()) 940 set_pgd(pgdp, __pgd(0)); 941 } 942 943 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 944 { 945 return __pgd_to_phys(pgd); 946 } 947 948 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 949 950 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 951 { 952 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 953 } 954 955 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 956 { 957 BUG_ON(!pgtable_l5_enabled()); 958 959 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 960 } 961 962 static inline 963 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 964 { 965 if (!pgtable_l5_enabled()) 966 return pgd_to_folded_p4d(pgdp, addr); 967 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 968 } 969 #define p4d_offset_lockless p4d_offset_lockless 970 971 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 972 { 973 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 974 } 975 976 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 977 { 978 if (!pgtable_l5_enabled()) 979 return NULL; 980 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 981 } 982 983 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 984 { 985 if (!pgtable_l5_enabled()) 986 return pgd_to_folded_p4d(pgdp, addr); 987 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 988 } 989 990 static inline void p4d_clear_fixmap(void) 991 { 992 if (pgtable_l5_enabled()) 993 clear_fixmap(FIX_P4D); 994 } 995 996 /* use ONLY for statically allocated translation tables */ 997 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 998 { 999 if (!pgtable_l5_enabled()) 1000 return pgd_to_folded_p4d(pgdp, addr); 1001 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1002 } 1003 1004 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1005 1006 #else 1007 1008 static inline bool pgtable_l5_enabled(void) { return false; } 1009 1010 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1011 #define p4d_set_fixmap(addr) NULL 1012 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1013 #define p4d_clear_fixmap() 1014 1015 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1016 1017 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1018 1019 #define pgd_ERROR(e) \ 1020 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1021 1022 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1023 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1024 1025 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1026 { 1027 /* 1028 * Normal and Normal-Tagged are two different memory types and indices 1029 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1030 */ 1031 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1032 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 1033 PTE_ATTRINDX_MASK; 1034 /* preserve the hardware dirty information */ 1035 if (pte_hw_dirty(pte)) 1036 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1037 1038 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1039 /* 1040 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1041 * dirtiness again. 1042 */ 1043 if (pte_sw_dirty(pte)) 1044 pte = pte_mkdirty(pte); 1045 return pte; 1046 } 1047 1048 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1049 { 1050 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1051 } 1052 1053 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1054 unsigned long address, pte_t *ptep, 1055 pte_t entry, int dirty); 1056 1057 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1058 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1059 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1060 unsigned long address, pmd_t *pmdp, 1061 pmd_t entry, int dirty) 1062 { 1063 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1064 pmd_pte(entry), dirty); 1065 } 1066 1067 static inline int pud_devmap(pud_t pud) 1068 { 1069 return 0; 1070 } 1071 1072 static inline int pgd_devmap(pgd_t pgd) 1073 { 1074 return 0; 1075 } 1076 #endif 1077 1078 #ifdef CONFIG_PAGE_TABLE_CHECK 1079 static inline bool pte_user_accessible_page(pte_t pte) 1080 { 1081 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 1082 } 1083 1084 static inline bool pmd_user_accessible_page(pmd_t pmd) 1085 { 1086 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1087 } 1088 1089 static inline bool pud_user_accessible_page(pud_t pud) 1090 { 1091 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 1092 } 1093 #endif 1094 1095 /* 1096 * Atomic pte/pmd modifications. 1097 */ 1098 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1099 unsigned long address, 1100 pte_t *ptep) 1101 { 1102 pte_t old_pte, pte; 1103 1104 pte = __ptep_get(ptep); 1105 do { 1106 old_pte = pte; 1107 pte = pte_mkold(pte); 1108 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1109 pte_val(old_pte), pte_val(pte)); 1110 } while (pte_val(pte) != pte_val(old_pte)); 1111 1112 return pte_young(pte); 1113 } 1114 1115 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1116 unsigned long address, pte_t *ptep) 1117 { 1118 int young = __ptep_test_and_clear_young(vma, address, ptep); 1119 1120 if (young) { 1121 /* 1122 * We can elide the trailing DSB here since the worst that can 1123 * happen is that a CPU continues to use the young entry in its 1124 * TLB and we mistakenly reclaim the associated page. The 1125 * window for such an event is bounded by the next 1126 * context-switch, which provides a DSB to complete the TLB 1127 * invalidation. 1128 */ 1129 flush_tlb_page_nosync(vma, address); 1130 } 1131 1132 return young; 1133 } 1134 1135 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1136 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1137 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1138 unsigned long address, 1139 pmd_t *pmdp) 1140 { 1141 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1142 } 1143 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1144 1145 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1146 unsigned long address, pte_t *ptep) 1147 { 1148 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1149 1150 page_table_check_pte_clear(mm, pte); 1151 1152 return pte; 1153 } 1154 1155 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1156 pte_t *ptep, unsigned int nr, int full) 1157 { 1158 for (;;) { 1159 __ptep_get_and_clear(mm, addr, ptep); 1160 if (--nr == 0) 1161 break; 1162 ptep++; 1163 addr += PAGE_SIZE; 1164 } 1165 } 1166 1167 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1168 unsigned long addr, pte_t *ptep, 1169 unsigned int nr, int full) 1170 { 1171 pte_t pte, tmp_pte; 1172 1173 pte = __ptep_get_and_clear(mm, addr, ptep); 1174 while (--nr) { 1175 ptep++; 1176 addr += PAGE_SIZE; 1177 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1178 if (pte_dirty(tmp_pte)) 1179 pte = pte_mkdirty(pte); 1180 if (pte_young(tmp_pte)) 1181 pte = pte_mkyoung(pte); 1182 } 1183 return pte; 1184 } 1185 1186 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1187 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1188 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1189 unsigned long address, pmd_t *pmdp) 1190 { 1191 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1192 1193 page_table_check_pmd_clear(mm, pmd); 1194 1195 return pmd; 1196 } 1197 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1198 1199 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1200 unsigned long address, pte_t *ptep, 1201 pte_t pte) 1202 { 1203 pte_t old_pte; 1204 1205 do { 1206 old_pte = pte; 1207 pte = pte_wrprotect(pte); 1208 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1209 pte_val(old_pte), pte_val(pte)); 1210 } while (pte_val(pte) != pte_val(old_pte)); 1211 } 1212 1213 /* 1214 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1215 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1216 */ 1217 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1218 unsigned long address, pte_t *ptep) 1219 { 1220 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1221 } 1222 1223 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1224 pte_t *ptep, unsigned int nr) 1225 { 1226 unsigned int i; 1227 1228 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1229 __ptep_set_wrprotect(mm, address, ptep); 1230 } 1231 1232 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1233 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1234 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1235 unsigned long address, pmd_t *pmdp) 1236 { 1237 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1238 } 1239 1240 #define pmdp_establish pmdp_establish 1241 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1242 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1243 { 1244 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1245 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1246 } 1247 #endif 1248 1249 /* 1250 * Encode and decode a swap entry: 1251 * bits 0-1: present (must be zero) 1252 * bits 2: remember PG_anon_exclusive 1253 * bits 3-7: swap type 1254 * bits 8-57: swap offset 1255 * bit 58: PTE_PROT_NONE (must be zero) 1256 */ 1257 #define __SWP_TYPE_SHIFT 3 1258 #define __SWP_TYPE_BITS 5 1259 #define __SWP_OFFSET_BITS 50 1260 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1261 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 1262 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1263 1264 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1265 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1266 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1267 1268 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1269 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1270 1271 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1272 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1273 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1274 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1275 1276 /* 1277 * Ensure that there are not more swap files than can be encoded in the kernel 1278 * PTEs. 1279 */ 1280 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1281 1282 #ifdef CONFIG_ARM64_MTE 1283 1284 #define __HAVE_ARCH_PREPARE_TO_SWAP 1285 static inline int arch_prepare_to_swap(struct page *page) 1286 { 1287 if (system_supports_mte()) 1288 return mte_save_tags(page); 1289 return 0; 1290 } 1291 1292 #define __HAVE_ARCH_SWAP_INVALIDATE 1293 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1294 { 1295 if (system_supports_mte()) 1296 mte_invalidate_tags(type, offset); 1297 } 1298 1299 static inline void arch_swap_invalidate_area(int type) 1300 { 1301 if (system_supports_mte()) 1302 mte_invalidate_tags_area(type); 1303 } 1304 1305 #define __HAVE_ARCH_SWAP_RESTORE 1306 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1307 { 1308 if (system_supports_mte()) 1309 mte_restore_tags(entry, &folio->page); 1310 } 1311 1312 #endif /* CONFIG_ARM64_MTE */ 1313 1314 /* 1315 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1316 */ 1317 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1318 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1319 unsigned int nr) 1320 { 1321 /* 1322 * We don't do anything here, so there's a very small chance of 1323 * us retaking a user fault which we just fixed up. The alternative 1324 * is doing a dsb(ishst), but that penalises the fastpath. 1325 */ 1326 } 1327 1328 #define update_mmu_cache(vma, addr, ptep) \ 1329 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1330 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1331 1332 #ifdef CONFIG_ARM64_PA_BITS_52 1333 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1334 #else 1335 #define phys_to_ttbr(addr) (addr) 1336 #endif 1337 1338 /* 1339 * On arm64 without hardware Access Flag, copying from user will fail because 1340 * the pte is old and cannot be marked young. So we always end up with zeroed 1341 * page after fork() + CoW for pfn mappings. We don't always have a 1342 * hardware-managed access flag on arm64. 1343 */ 1344 #define arch_has_hw_pte_young cpu_has_hw_af 1345 1346 /* 1347 * Experimentally, it's cheap to set the access flag in hardware and we 1348 * benefit from prefaulting mappings as 'old' to start with. 1349 */ 1350 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1351 1352 static inline bool pud_sect_supported(void) 1353 { 1354 return PAGE_SIZE == SZ_4K; 1355 } 1356 1357 1358 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1359 #define ptep_modify_prot_start ptep_modify_prot_start 1360 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1361 unsigned long addr, pte_t *ptep); 1362 1363 #define ptep_modify_prot_commit ptep_modify_prot_commit 1364 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1365 unsigned long addr, pte_t *ptep, 1366 pte_t old_pte, pte_t new_pte); 1367 1368 #ifdef CONFIG_ARM64_CONTPTE 1369 1370 /* 1371 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1372 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1373 * a private implementation detail of the public ptep API (see below). 1374 */ 1375 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1376 pte_t *ptep, pte_t pte); 1377 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1378 pte_t *ptep, pte_t pte); 1379 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1380 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1381 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1382 pte_t *ptep, pte_t pte, unsigned int nr); 1383 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1384 pte_t *ptep, unsigned int nr, int full); 1385 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1386 unsigned long addr, pte_t *ptep, 1387 unsigned int nr, int full); 1388 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1389 unsigned long addr, pte_t *ptep); 1390 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1391 unsigned long addr, pte_t *ptep); 1392 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1393 pte_t *ptep, unsigned int nr); 1394 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1395 unsigned long addr, pte_t *ptep, 1396 pte_t entry, int dirty); 1397 1398 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1399 unsigned long addr, pte_t *ptep, pte_t pte) 1400 { 1401 /* 1402 * Only bother trying if both the virtual and physical addresses are 1403 * aligned and correspond to the last entry in a contig range. The core 1404 * code mostly modifies ranges from low to high, so this is the likely 1405 * the last modification in the contig range, so a good time to fold. 1406 * We can't fold special mappings, because there is no associated folio. 1407 */ 1408 1409 const unsigned long contmask = CONT_PTES - 1; 1410 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1411 1412 if (unlikely(valign)) { 1413 bool palign = (pte_pfn(pte) & contmask) == contmask; 1414 1415 if (unlikely(palign && 1416 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1417 __contpte_try_fold(mm, addr, ptep, pte); 1418 } 1419 } 1420 1421 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1422 unsigned long addr, pte_t *ptep, pte_t pte) 1423 { 1424 if (unlikely(pte_valid_cont(pte))) 1425 __contpte_try_unfold(mm, addr, ptep, pte); 1426 } 1427 1428 #define pte_batch_hint pte_batch_hint 1429 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1430 { 1431 if (!pte_valid_cont(pte)) 1432 return 1; 1433 1434 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1435 } 1436 1437 /* 1438 * The below functions constitute the public API that arm64 presents to the 1439 * core-mm to manipulate PTE entries within their page tables (or at least this 1440 * is the subset of the API that arm64 needs to implement). These public 1441 * versions will automatically and transparently apply the contiguous bit where 1442 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1443 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1444 * private versions, which are prefixed with double underscore. All of these 1445 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1446 * held. Although the contiguous bit is considered private to the 1447 * implementation, it is deliberately allowed to leak through the getters (e.g. 1448 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1449 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1450 * its possible a pte will be passed to a setter with the contiguous bit set, so 1451 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1452 * setting it in the pgtable. 1453 */ 1454 1455 #define ptep_get ptep_get 1456 static inline pte_t ptep_get(pte_t *ptep) 1457 { 1458 pte_t pte = __ptep_get(ptep); 1459 1460 if (likely(!pte_valid_cont(pte))) 1461 return pte; 1462 1463 return contpte_ptep_get(ptep, pte); 1464 } 1465 1466 #define ptep_get_lockless ptep_get_lockless 1467 static inline pte_t ptep_get_lockless(pte_t *ptep) 1468 { 1469 pte_t pte = __ptep_get(ptep); 1470 1471 if (likely(!pte_valid_cont(pte))) 1472 return pte; 1473 1474 return contpte_ptep_get_lockless(ptep); 1475 } 1476 1477 static inline void set_pte(pte_t *ptep, pte_t pte) 1478 { 1479 /* 1480 * We don't have the mm or vaddr so cannot unfold contig entries (since 1481 * it requires tlb maintenance). set_pte() is not used in core code, so 1482 * this should never even be called. Regardless do our best to service 1483 * any call and emit a warning if there is any attempt to set a pte on 1484 * top of an existing contig range. 1485 */ 1486 pte_t orig_pte = __ptep_get(ptep); 1487 1488 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1489 __set_pte(ptep, pte_mknoncont(pte)); 1490 } 1491 1492 #define set_ptes set_ptes 1493 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1494 pte_t *ptep, pte_t pte, unsigned int nr) 1495 { 1496 pte = pte_mknoncont(pte); 1497 1498 if (likely(nr == 1)) { 1499 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1500 __set_ptes(mm, addr, ptep, pte, 1); 1501 contpte_try_fold(mm, addr, ptep, pte); 1502 } else { 1503 contpte_set_ptes(mm, addr, ptep, pte, nr); 1504 } 1505 } 1506 1507 static inline void pte_clear(struct mm_struct *mm, 1508 unsigned long addr, pte_t *ptep) 1509 { 1510 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1511 __pte_clear(mm, addr, ptep); 1512 } 1513 1514 #define clear_full_ptes clear_full_ptes 1515 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1516 pte_t *ptep, unsigned int nr, int full) 1517 { 1518 if (likely(nr == 1)) { 1519 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1520 __clear_full_ptes(mm, addr, ptep, nr, full); 1521 } else { 1522 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1523 } 1524 } 1525 1526 #define get_and_clear_full_ptes get_and_clear_full_ptes 1527 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1528 unsigned long addr, pte_t *ptep, 1529 unsigned int nr, int full) 1530 { 1531 pte_t pte; 1532 1533 if (likely(nr == 1)) { 1534 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1535 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1536 } else { 1537 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1538 } 1539 1540 return pte; 1541 } 1542 1543 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1544 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1545 unsigned long addr, pte_t *ptep) 1546 { 1547 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1548 return __ptep_get_and_clear(mm, addr, ptep); 1549 } 1550 1551 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1552 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1553 unsigned long addr, pte_t *ptep) 1554 { 1555 pte_t orig_pte = __ptep_get(ptep); 1556 1557 if (likely(!pte_valid_cont(orig_pte))) 1558 return __ptep_test_and_clear_young(vma, addr, ptep); 1559 1560 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1561 } 1562 1563 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1564 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1565 unsigned long addr, pte_t *ptep) 1566 { 1567 pte_t orig_pte = __ptep_get(ptep); 1568 1569 if (likely(!pte_valid_cont(orig_pte))) 1570 return __ptep_clear_flush_young(vma, addr, ptep); 1571 1572 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1573 } 1574 1575 #define wrprotect_ptes wrprotect_ptes 1576 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1577 unsigned long addr, pte_t *ptep, unsigned int nr) 1578 { 1579 if (likely(nr == 1)) { 1580 /* 1581 * Optimization: wrprotect_ptes() can only be called for present 1582 * ptes so we only need to check contig bit as condition for 1583 * unfold, and we can remove the contig bit from the pte we read 1584 * to avoid re-reading. This speeds up fork() which is sensitive 1585 * for order-0 folios. Equivalent to contpte_try_unfold(). 1586 */ 1587 pte_t orig_pte = __ptep_get(ptep); 1588 1589 if (unlikely(pte_cont(orig_pte))) { 1590 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1591 orig_pte = pte_mknoncont(orig_pte); 1592 } 1593 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1594 } else { 1595 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1596 } 1597 } 1598 1599 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1600 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1601 unsigned long addr, pte_t *ptep) 1602 { 1603 wrprotect_ptes(mm, addr, ptep, 1); 1604 } 1605 1606 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1607 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1608 unsigned long addr, pte_t *ptep, 1609 pte_t entry, int dirty) 1610 { 1611 pte_t orig_pte = __ptep_get(ptep); 1612 1613 entry = pte_mknoncont(entry); 1614 1615 if (likely(!pte_valid_cont(orig_pte))) 1616 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1617 1618 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1619 } 1620 1621 #else /* CONFIG_ARM64_CONTPTE */ 1622 1623 #define ptep_get __ptep_get 1624 #define set_pte __set_pte 1625 #define set_ptes __set_ptes 1626 #define pte_clear __pte_clear 1627 #define clear_full_ptes __clear_full_ptes 1628 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1629 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1630 #define ptep_get_and_clear __ptep_get_and_clear 1631 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1632 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1633 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1634 #define ptep_clear_flush_young __ptep_clear_flush_young 1635 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1636 #define ptep_set_wrprotect __ptep_set_wrprotect 1637 #define wrprotect_ptes __wrprotect_ptes 1638 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1639 #define ptep_set_access_flags __ptep_set_access_flags 1640 1641 #endif /* CONFIG_ARM64_CONTPTE */ 1642 1643 #endif /* !__ASSEMBLY__ */ 1644 1645 #endif /* __ASM_PGTABLE_H */ 1646