1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <asm/por.h> 38 #include <linux/mmdebug.h> 39 #include <linux/mm_types.h> 40 #include <linux/sched.h> 41 #include <linux/page_table_check.h> 42 43 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45 46 /* Set stride and tlb_level in flush_*_tlb_range */ 47 #define flush_pmd_tlb_range(vma, addr, end) \ 48 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49 #define flush_pud_tlb_range(vma, addr, end) \ 50 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52 53 /* 54 * Outside of a few very special situations (e.g. hibernation), we always 55 * use broadcast TLB invalidation instructions, therefore a spurious page 56 * fault on one CPU which has been handled concurrently by another CPU 57 * does not need to perform additional invalidation. 58 */ 59 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 60 61 /* 62 * ZERO_PAGE is a global shared page that is always zero: used 63 * for zero-mapped memory areas etc.. 64 */ 65 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 66 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 67 68 #define pte_ERROR(e) \ 69 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 70 71 /* 72 * Macros to convert between a physical address and its placement in a 73 * page table entry, taking care of 52-bit addresses. 74 */ 75 #ifdef CONFIG_ARM64_PA_BITS_52 76 static inline phys_addr_t __pte_to_phys(pte_t pte) 77 { 78 pte_val(pte) &= ~PTE_MAYBE_SHARED; 79 return (pte_val(pte) & PTE_ADDR_LOW) | 80 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81 } 82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83 { 84 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 85 } 86 #else 87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 88 #define __phys_to_pte_val(phys) (phys) 89 #endif 90 91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 92 #define pfn_pte(pfn,prot) \ 93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 94 95 #define pte_none(pte) (!pte_val(pte)) 96 #define __pte_clear(mm, addr, ptep) \ 97 __set_pte(ptep, __pte(0)) 98 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 99 100 /* 101 * The following only work if pte_present(). Undefined behaviour otherwise. 102 */ 103 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 104 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 105 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 106 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 107 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 108 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 109 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 110 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 111 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 112 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 113 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 114 115 #define pte_cont_addr_end(addr, end) \ 116 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 117 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 118 }) 119 120 #define pmd_cont_addr_end(addr, end) \ 121 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 122 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123 }) 124 125 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 126 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 127 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 128 129 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 130 #define pte_present_invalid(pte) \ 131 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 132 /* 133 * Execute-only user mappings do not have the PTE_USER bit set. All valid 134 * kernel mappings have the PTE_UXN bit set. 135 */ 136 #define pte_valid_not_user(pte) \ 137 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 138 /* 139 * Returns true if the pte is valid and has the contiguous bit set. 140 */ 141 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 142 /* 143 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 144 * so that we don't erroneously return false for pages that have been 145 * remapped as PROT_NONE but are yet to be flushed from the TLB. 146 * Note that we can't make any assumptions based on the state of the access 147 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 148 * TLB. 149 */ 150 #define pte_accessible(mm, pte) \ 151 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 152 153 static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute) 154 { 155 u64 por; 156 157 if (!system_supports_poe()) 158 return true; 159 160 por = read_sysreg_s(SYS_POR_EL0); 161 162 if (write) 163 return por_elx_allows_write(por, pkey); 164 165 if (execute) 166 return por_elx_allows_exec(por, pkey); 167 168 return por_elx_allows_read(por, pkey); 169 } 170 171 /* 172 * p??_access_permitted() is true for valid user mappings (PTE_USER 173 * bit set, subject to the write permission check). For execute-only 174 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 175 * not set) must return false. PROT_NONE mappings do not have the 176 * PTE_VALID bit set. 177 */ 178 #define pte_access_permitted_no_overlay(pte, write) \ 179 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 180 #define pte_access_permitted(pte, write) \ 181 (pte_access_permitted_no_overlay(pte, write) && \ 182 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false)) 183 #define pmd_access_permitted(pmd, write) \ 184 (pte_access_permitted(pmd_pte(pmd), (write))) 185 #define pud_access_permitted(pud, write) \ 186 (pte_access_permitted(pud_pte(pud), (write))) 187 188 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 189 { 190 pte_val(pte) &= ~pgprot_val(prot); 191 return pte; 192 } 193 194 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 195 { 196 pte_val(pte) |= pgprot_val(prot); 197 return pte; 198 } 199 200 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 201 { 202 pmd_val(pmd) &= ~pgprot_val(prot); 203 return pmd; 204 } 205 206 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 207 { 208 pmd_val(pmd) |= pgprot_val(prot); 209 return pmd; 210 } 211 212 static inline pte_t pte_mkwrite_novma(pte_t pte) 213 { 214 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 215 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 216 return pte; 217 } 218 219 static inline pte_t pte_mkclean(pte_t pte) 220 { 221 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 222 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 223 224 return pte; 225 } 226 227 static inline pte_t pte_mkdirty(pte_t pte) 228 { 229 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 230 231 if (pte_write(pte)) 232 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 233 234 return pte; 235 } 236 237 static inline pte_t pte_wrprotect(pte_t pte) 238 { 239 /* 240 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 241 * clear), set the PTE_DIRTY bit. 242 */ 243 if (pte_hw_dirty(pte)) 244 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 245 246 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 247 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 248 return pte; 249 } 250 251 static inline pte_t pte_mkold(pte_t pte) 252 { 253 return clear_pte_bit(pte, __pgprot(PTE_AF)); 254 } 255 256 static inline pte_t pte_mkyoung(pte_t pte) 257 { 258 return set_pte_bit(pte, __pgprot(PTE_AF)); 259 } 260 261 static inline pte_t pte_mkspecial(pte_t pte) 262 { 263 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 264 } 265 266 static inline pte_t pte_mkcont(pte_t pte) 267 { 268 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 269 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 270 } 271 272 static inline pte_t pte_mknoncont(pte_t pte) 273 { 274 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 275 } 276 277 static inline pte_t pte_mkpresent(pte_t pte) 278 { 279 return set_pte_bit(pte, __pgprot(PTE_VALID)); 280 } 281 282 static inline pte_t pte_mkinvalid(pte_t pte) 283 { 284 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 285 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 286 return pte; 287 } 288 289 static inline pmd_t pmd_mkcont(pmd_t pmd) 290 { 291 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 292 } 293 294 static inline pte_t pte_mkdevmap(pte_t pte) 295 { 296 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 297 } 298 299 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 300 static inline int pte_uffd_wp(pte_t pte) 301 { 302 return !!(pte_val(pte) & PTE_UFFD_WP); 303 } 304 305 static inline pte_t pte_mkuffd_wp(pte_t pte) 306 { 307 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 308 } 309 310 static inline pte_t pte_clear_uffd_wp(pte_t pte) 311 { 312 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 313 } 314 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 315 316 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 317 { 318 WRITE_ONCE(*ptep, pte); 319 } 320 321 static inline void __set_pte(pte_t *ptep, pte_t pte) 322 { 323 __set_pte_nosync(ptep, pte); 324 325 /* 326 * Only if the new pte is valid and kernel, otherwise TLB maintenance 327 * or update_mmu_cache() have the necessary barriers. 328 */ 329 if (pte_valid_not_user(pte)) { 330 dsb(ishst); 331 isb(); 332 } 333 } 334 335 static inline pte_t __ptep_get(pte_t *ptep) 336 { 337 return READ_ONCE(*ptep); 338 } 339 340 extern void __sync_icache_dcache(pte_t pteval); 341 bool pgattr_change_is_safe(u64 old, u64 new); 342 343 /* 344 * PTE bits configuration in the presence of hardware Dirty Bit Management 345 * (PTE_WRITE == PTE_DBM): 346 * 347 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 348 * 0 0 | 1 0 0 349 * 0 1 | 1 1 0 350 * 1 0 | 1 0 1 351 * 1 1 | 0 1 x 352 * 353 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 354 * the page fault mechanism. Checking the dirty status of a pte becomes: 355 * 356 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 357 */ 358 359 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 360 pte_t pte) 361 { 362 pte_t old_pte; 363 364 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 365 return; 366 367 old_pte = __ptep_get(ptep); 368 369 if (!pte_valid(old_pte) || !pte_valid(pte)) 370 return; 371 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 372 return; 373 374 /* 375 * Check for potential race with hardware updates of the pte 376 * (__ptep_set_access_flags safely changes valid ptes without going 377 * through an invalid entry). 378 */ 379 VM_WARN_ONCE(!pte_young(pte), 380 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 381 __func__, pte_val(old_pte), pte_val(pte)); 382 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 383 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 384 __func__, pte_val(old_pte), pte_val(pte)); 385 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 386 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 387 __func__, pte_val(old_pte), pte_val(pte)); 388 } 389 390 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 391 { 392 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 393 __sync_icache_dcache(pte); 394 395 /* 396 * If the PTE would provide user space access to the tags associated 397 * with it then ensure that the MTE tags are synchronised. Although 398 * pte_access_permitted_no_overlay() returns false for exec only 399 * mappings, they don't expose tags (instruction fetches don't check 400 * tags). 401 */ 402 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) && 403 !pte_special(pte) && pte_tagged(pte)) 404 mte_sync_tags(pte, nr_pages); 405 } 406 407 /* 408 * Select all bits except the pfn 409 */ 410 static inline pgprot_t pte_pgprot(pte_t pte) 411 { 412 unsigned long pfn = pte_pfn(pte); 413 414 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 415 } 416 417 #define pte_advance_pfn pte_advance_pfn 418 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 419 { 420 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 421 } 422 423 static inline void __set_ptes(struct mm_struct *mm, 424 unsigned long __always_unused addr, 425 pte_t *ptep, pte_t pte, unsigned int nr) 426 { 427 page_table_check_ptes_set(mm, ptep, pte, nr); 428 __sync_cache_and_tags(pte, nr); 429 430 for (;;) { 431 __check_safe_pte_update(mm, ptep, pte); 432 __set_pte(ptep, pte); 433 if (--nr == 0) 434 break; 435 ptep++; 436 pte = pte_advance_pfn(pte, 1); 437 } 438 } 439 440 /* 441 * Huge pte definitions. 442 */ 443 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 444 445 /* 446 * Hugetlb definitions. 447 */ 448 #define HUGE_MAX_HSTATE 4 449 #define HPAGE_SHIFT PMD_SHIFT 450 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 451 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 452 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 453 454 static inline pte_t pgd_pte(pgd_t pgd) 455 { 456 return __pte(pgd_val(pgd)); 457 } 458 459 static inline pte_t p4d_pte(p4d_t p4d) 460 { 461 return __pte(p4d_val(p4d)); 462 } 463 464 static inline pte_t pud_pte(pud_t pud) 465 { 466 return __pte(pud_val(pud)); 467 } 468 469 static inline pud_t pte_pud(pte_t pte) 470 { 471 return __pud(pte_val(pte)); 472 } 473 474 static inline pmd_t pud_pmd(pud_t pud) 475 { 476 return __pmd(pud_val(pud)); 477 } 478 479 static inline pte_t pmd_pte(pmd_t pmd) 480 { 481 return __pte(pmd_val(pmd)); 482 } 483 484 static inline pmd_t pte_pmd(pte_t pte) 485 { 486 return __pmd(pte_val(pte)); 487 } 488 489 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 490 { 491 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 492 } 493 494 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 495 { 496 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 497 } 498 499 static inline pte_t pte_swp_mkexclusive(pte_t pte) 500 { 501 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 502 } 503 504 static inline int pte_swp_exclusive(pte_t pte) 505 { 506 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 507 } 508 509 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 510 { 511 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 512 } 513 514 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 515 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 516 { 517 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 518 } 519 520 static inline int pte_swp_uffd_wp(pte_t pte) 521 { 522 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 523 } 524 525 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 526 { 527 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 528 } 529 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 530 531 #ifdef CONFIG_NUMA_BALANCING 532 /* 533 * See the comment in include/linux/pgtable.h 534 */ 535 static inline int pte_protnone(pte_t pte) 536 { 537 /* 538 * pte_present_invalid() tells us that the pte is invalid from HW 539 * perspective but present from SW perspective, so the fields are to be 540 * interpretted as per the HW layout. The second 2 checks are the unique 541 * encoding that we use for PROT_NONE. It is insufficient to only use 542 * the first check because we share the same encoding scheme with pmds 543 * which support pmd_mkinvalid(), so can be present-invalid without 544 * being PROT_NONE. 545 */ 546 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 547 } 548 549 static inline int pmd_protnone(pmd_t pmd) 550 { 551 return pte_protnone(pmd_pte(pmd)); 552 } 553 #endif 554 555 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 556 557 /* 558 * THP definitions. 559 */ 560 561 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 562 static inline int pmd_trans_huge(pmd_t pmd) 563 { 564 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 565 } 566 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 567 568 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 569 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 570 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 571 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 572 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 573 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 574 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 575 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 576 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 577 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 578 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 579 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 580 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 581 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 582 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 583 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 584 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 585 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 586 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 587 #define pmd_swp_clear_uffd_wp(pmd) \ 588 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 589 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 590 591 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 592 593 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 594 595 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 596 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 597 #endif 598 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 599 { 600 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 601 } 602 603 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 604 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 605 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 606 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 607 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 608 609 #define pud_young(pud) pte_young(pud_pte(pud)) 610 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 611 #define pud_write(pud) pte_write(pud_pte(pud)) 612 613 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 614 615 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 616 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 617 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 618 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 619 620 static inline void __set_pte_at(struct mm_struct *mm, 621 unsigned long __always_unused addr, 622 pte_t *ptep, pte_t pte, unsigned int nr) 623 { 624 __sync_cache_and_tags(pte, nr); 625 __check_safe_pte_update(mm, ptep, pte); 626 __set_pte(ptep, pte); 627 } 628 629 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 630 pmd_t *pmdp, pmd_t pmd) 631 { 632 page_table_check_pmd_set(mm, pmdp, pmd); 633 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 634 PMD_SIZE >> PAGE_SHIFT); 635 } 636 637 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 638 pud_t *pudp, pud_t pud) 639 { 640 page_table_check_pud_set(mm, pudp, pud); 641 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 642 PUD_SIZE >> PAGE_SHIFT); 643 } 644 645 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 646 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 647 648 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 649 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 650 651 #define __pgprot_modify(prot,mask,bits) \ 652 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 653 654 #define pgprot_nx(prot) \ 655 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 656 657 /* 658 * Mark the prot value as uncacheable and unbufferable. 659 */ 660 #define pgprot_noncached(prot) \ 661 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 662 #define pgprot_writecombine(prot) \ 663 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 664 #define pgprot_device(prot) \ 665 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 666 #define pgprot_tagged(prot) \ 667 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 668 #define pgprot_mhp pgprot_tagged 669 /* 670 * DMA allocations for non-coherent devices use what the Arm architecture calls 671 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 672 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 673 * is intended for MMIO and thus forbids speculation, preserves access size, 674 * requires strict alignment and can also force write responses to come from the 675 * endpoint. 676 */ 677 #define pgprot_dmacoherent(prot) \ 678 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 679 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 680 681 #define __HAVE_PHYS_MEM_ACCESS_PROT 682 struct file; 683 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 684 unsigned long size, pgprot_t vma_prot); 685 686 #define pmd_none(pmd) (!pmd_val(pmd)) 687 688 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 689 PMD_TYPE_TABLE) 690 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 691 PMD_TYPE_SECT) 692 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 693 #define pmd_bad(pmd) (!pmd_table(pmd)) 694 695 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 696 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 697 698 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 699 static inline bool pud_sect(pud_t pud) { return false; } 700 static inline bool pud_table(pud_t pud) { return true; } 701 #else 702 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 703 PUD_TYPE_SECT) 704 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 705 PUD_TYPE_TABLE) 706 #endif 707 708 extern pgd_t init_pg_dir[]; 709 extern pgd_t init_pg_end[]; 710 extern pgd_t swapper_pg_dir[]; 711 extern pgd_t idmap_pg_dir[]; 712 extern pgd_t tramp_pg_dir[]; 713 extern pgd_t reserved_pg_dir[]; 714 715 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 716 717 static inline bool in_swapper_pgdir(void *addr) 718 { 719 return ((unsigned long)addr & PAGE_MASK) == 720 ((unsigned long)swapper_pg_dir & PAGE_MASK); 721 } 722 723 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 724 { 725 #ifdef __PAGETABLE_PMD_FOLDED 726 if (in_swapper_pgdir(pmdp)) { 727 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 728 return; 729 } 730 #endif /* __PAGETABLE_PMD_FOLDED */ 731 732 WRITE_ONCE(*pmdp, pmd); 733 734 if (pmd_valid(pmd)) { 735 dsb(ishst); 736 isb(); 737 } 738 } 739 740 static inline void pmd_clear(pmd_t *pmdp) 741 { 742 set_pmd(pmdp, __pmd(0)); 743 } 744 745 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 746 { 747 return __pmd_to_phys(pmd); 748 } 749 750 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 751 { 752 return (unsigned long)__va(pmd_page_paddr(pmd)); 753 } 754 755 /* Find an entry in the third-level page table. */ 756 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 757 758 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 759 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 760 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 761 762 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 763 764 /* use ONLY for statically allocated translation tables */ 765 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 766 767 /* 768 * Conversion functions: convert a page and protection to a page entry, 769 * and a page entry and page directory to the page they refer to. 770 */ 771 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 772 773 #if CONFIG_PGTABLE_LEVELS > 2 774 775 #define pmd_ERROR(e) \ 776 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 777 778 #define pud_none(pud) (!pud_val(pud)) 779 #define pud_bad(pud) (!pud_table(pud)) 780 #define pud_present(pud) pte_present(pud_pte(pud)) 781 #ifndef __PAGETABLE_PMD_FOLDED 782 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 783 #else 784 #define pud_leaf(pud) false 785 #endif 786 #define pud_valid(pud) pte_valid(pud_pte(pud)) 787 #define pud_user(pud) pte_user(pud_pte(pud)) 788 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 789 790 static inline bool pgtable_l4_enabled(void); 791 792 static inline void set_pud(pud_t *pudp, pud_t pud) 793 { 794 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 795 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 796 return; 797 } 798 799 WRITE_ONCE(*pudp, pud); 800 801 if (pud_valid(pud)) { 802 dsb(ishst); 803 isb(); 804 } 805 } 806 807 static inline void pud_clear(pud_t *pudp) 808 { 809 set_pud(pudp, __pud(0)); 810 } 811 812 static inline phys_addr_t pud_page_paddr(pud_t pud) 813 { 814 return __pud_to_phys(pud); 815 } 816 817 static inline pmd_t *pud_pgtable(pud_t pud) 818 { 819 return (pmd_t *)__va(pud_page_paddr(pud)); 820 } 821 822 /* Find an entry in the second-level page table. */ 823 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 824 825 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 826 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 827 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 828 829 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 830 831 /* use ONLY for statically allocated translation tables */ 832 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 833 834 #else 835 836 #define pud_valid(pud) false 837 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 838 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 839 840 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 841 #define pmd_set_fixmap(addr) NULL 842 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 843 #define pmd_clear_fixmap() 844 845 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 846 847 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 848 849 #if CONFIG_PGTABLE_LEVELS > 3 850 851 static __always_inline bool pgtable_l4_enabled(void) 852 { 853 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 854 return true; 855 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 856 return vabits_actual == VA_BITS; 857 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 858 } 859 860 static inline bool mm_pud_folded(const struct mm_struct *mm) 861 { 862 return !pgtable_l4_enabled(); 863 } 864 #define mm_pud_folded mm_pud_folded 865 866 #define pud_ERROR(e) \ 867 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 868 869 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 870 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 871 #define p4d_present(p4d) (!p4d_none(p4d)) 872 873 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 874 { 875 if (in_swapper_pgdir(p4dp)) { 876 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 877 return; 878 } 879 880 WRITE_ONCE(*p4dp, p4d); 881 dsb(ishst); 882 isb(); 883 } 884 885 static inline void p4d_clear(p4d_t *p4dp) 886 { 887 if (pgtable_l4_enabled()) 888 set_p4d(p4dp, __p4d(0)); 889 } 890 891 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 892 { 893 return __p4d_to_phys(p4d); 894 } 895 896 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 897 898 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 899 { 900 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 901 } 902 903 static inline pud_t *p4d_pgtable(p4d_t p4d) 904 { 905 return (pud_t *)__va(p4d_page_paddr(p4d)); 906 } 907 908 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 909 { 910 BUG_ON(!pgtable_l4_enabled()); 911 912 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 913 } 914 915 static inline 916 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 917 { 918 if (!pgtable_l4_enabled()) 919 return p4d_to_folded_pud(p4dp, addr); 920 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 921 } 922 #define pud_offset_lockless pud_offset_lockless 923 924 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 925 { 926 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 927 } 928 #define pud_offset pud_offset 929 930 static inline pud_t *pud_set_fixmap(unsigned long addr) 931 { 932 if (!pgtable_l4_enabled()) 933 return NULL; 934 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 935 } 936 937 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 938 { 939 if (!pgtable_l4_enabled()) 940 return p4d_to_folded_pud(p4dp, addr); 941 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 942 } 943 944 static inline void pud_clear_fixmap(void) 945 { 946 if (pgtable_l4_enabled()) 947 clear_fixmap(FIX_PUD); 948 } 949 950 /* use ONLY for statically allocated translation tables */ 951 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 952 { 953 if (!pgtable_l4_enabled()) 954 return p4d_to_folded_pud(p4dp, addr); 955 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 956 } 957 958 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 959 960 #else 961 962 static inline bool pgtable_l4_enabled(void) { return false; } 963 964 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 965 966 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 967 #define pud_set_fixmap(addr) NULL 968 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 969 #define pud_clear_fixmap() 970 971 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 972 973 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 974 975 #if CONFIG_PGTABLE_LEVELS > 4 976 977 static __always_inline bool pgtable_l5_enabled(void) 978 { 979 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 980 return vabits_actual == VA_BITS; 981 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 982 } 983 984 static inline bool mm_p4d_folded(const struct mm_struct *mm) 985 { 986 return !pgtable_l5_enabled(); 987 } 988 #define mm_p4d_folded mm_p4d_folded 989 990 #define p4d_ERROR(e) \ 991 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 992 993 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 994 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 995 #define pgd_present(pgd) (!pgd_none(pgd)) 996 997 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 998 { 999 if (in_swapper_pgdir(pgdp)) { 1000 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 1001 return; 1002 } 1003 1004 WRITE_ONCE(*pgdp, pgd); 1005 dsb(ishst); 1006 isb(); 1007 } 1008 1009 static inline void pgd_clear(pgd_t *pgdp) 1010 { 1011 if (pgtable_l5_enabled()) 1012 set_pgd(pgdp, __pgd(0)); 1013 } 1014 1015 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 1016 { 1017 return __pgd_to_phys(pgd); 1018 } 1019 1020 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1021 1022 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1023 { 1024 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1025 } 1026 1027 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1028 { 1029 BUG_ON(!pgtable_l5_enabled()); 1030 1031 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1032 } 1033 1034 static inline 1035 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1036 { 1037 if (!pgtable_l5_enabled()) 1038 return pgd_to_folded_p4d(pgdp, addr); 1039 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1040 } 1041 #define p4d_offset_lockless p4d_offset_lockless 1042 1043 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1044 { 1045 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1046 } 1047 1048 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1049 { 1050 if (!pgtable_l5_enabled()) 1051 return NULL; 1052 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1053 } 1054 1055 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1056 { 1057 if (!pgtable_l5_enabled()) 1058 return pgd_to_folded_p4d(pgdp, addr); 1059 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1060 } 1061 1062 static inline void p4d_clear_fixmap(void) 1063 { 1064 if (pgtable_l5_enabled()) 1065 clear_fixmap(FIX_P4D); 1066 } 1067 1068 /* use ONLY for statically allocated translation tables */ 1069 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1070 { 1071 if (!pgtable_l5_enabled()) 1072 return pgd_to_folded_p4d(pgdp, addr); 1073 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1074 } 1075 1076 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1077 1078 #else 1079 1080 static inline bool pgtable_l5_enabled(void) { return false; } 1081 1082 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1083 1084 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1085 #define p4d_set_fixmap(addr) NULL 1086 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1087 #define p4d_clear_fixmap() 1088 1089 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1090 1091 static inline 1092 p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1093 { 1094 /* 1095 * With runtime folding of the pud, pud_offset_lockless() passes 1096 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which 1097 * will offset the pointer assuming that it points into 1098 * a page-table page. However, the fast GUP path passes us a 1099 * pgd_t allocated on the stack and so we must use the original 1100 * pointer in 'pgdp' to construct the p4d pointer instead of 1101 * using the generic p4d_offset_lockless() implementation. 1102 * 1103 * Note: reusing the original pointer means that we may 1104 * dereference the same (live) page-table entry multiple times. 1105 * This is safe because it is still only loaded once in the 1106 * context of each level and the CPU guarantees same-address 1107 * read-after-read ordering. 1108 */ 1109 return p4d_offset(pgdp, addr); 1110 } 1111 #define p4d_offset_lockless p4d_offset_lockless_folded 1112 1113 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1114 1115 #define pgd_ERROR(e) \ 1116 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1117 1118 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1119 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1120 1121 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1122 { 1123 /* 1124 * Normal and Normal-Tagged are two different memory types and indices 1125 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1126 */ 1127 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1128 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1129 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK; 1130 1131 /* preserve the hardware dirty information */ 1132 if (pte_hw_dirty(pte)) 1133 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1134 1135 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1136 /* 1137 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1138 * dirtiness again. 1139 */ 1140 if (pte_sw_dirty(pte)) 1141 pte = pte_mkdirty(pte); 1142 return pte; 1143 } 1144 1145 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1146 { 1147 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1148 } 1149 1150 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1151 unsigned long address, pte_t *ptep, 1152 pte_t entry, int dirty); 1153 1154 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1155 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1156 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1157 unsigned long address, pmd_t *pmdp, 1158 pmd_t entry, int dirty) 1159 { 1160 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1161 pmd_pte(entry), dirty); 1162 } 1163 1164 static inline int pud_devmap(pud_t pud) 1165 { 1166 return 0; 1167 } 1168 1169 static inline int pgd_devmap(pgd_t pgd) 1170 { 1171 return 0; 1172 } 1173 #endif 1174 1175 #ifdef CONFIG_PAGE_TABLE_CHECK 1176 static inline bool pte_user_accessible_page(pte_t pte) 1177 { 1178 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1179 } 1180 1181 static inline bool pmd_user_accessible_page(pmd_t pmd) 1182 { 1183 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1184 } 1185 1186 static inline bool pud_user_accessible_page(pud_t pud) 1187 { 1188 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1189 } 1190 #endif 1191 1192 /* 1193 * Atomic pte/pmd modifications. 1194 */ 1195 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1196 unsigned long address, 1197 pte_t *ptep) 1198 { 1199 pte_t old_pte, pte; 1200 1201 pte = __ptep_get(ptep); 1202 do { 1203 old_pte = pte; 1204 pte = pte_mkold(pte); 1205 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1206 pte_val(old_pte), pte_val(pte)); 1207 } while (pte_val(pte) != pte_val(old_pte)); 1208 1209 return pte_young(pte); 1210 } 1211 1212 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1213 unsigned long address, pte_t *ptep) 1214 { 1215 int young = __ptep_test_and_clear_young(vma, address, ptep); 1216 1217 if (young) { 1218 /* 1219 * We can elide the trailing DSB here since the worst that can 1220 * happen is that a CPU continues to use the young entry in its 1221 * TLB and we mistakenly reclaim the associated page. The 1222 * window for such an event is bounded by the next 1223 * context-switch, which provides a DSB to complete the TLB 1224 * invalidation. 1225 */ 1226 flush_tlb_page_nosync(vma, address); 1227 } 1228 1229 return young; 1230 } 1231 1232 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1233 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1234 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1235 unsigned long address, 1236 pmd_t *pmdp) 1237 { 1238 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1239 } 1240 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1241 1242 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1243 unsigned long address, pte_t *ptep) 1244 { 1245 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1246 1247 page_table_check_pte_clear(mm, pte); 1248 1249 return pte; 1250 } 1251 1252 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1253 pte_t *ptep, unsigned int nr, int full) 1254 { 1255 for (;;) { 1256 __ptep_get_and_clear(mm, addr, ptep); 1257 if (--nr == 0) 1258 break; 1259 ptep++; 1260 addr += PAGE_SIZE; 1261 } 1262 } 1263 1264 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1265 unsigned long addr, pte_t *ptep, 1266 unsigned int nr, int full) 1267 { 1268 pte_t pte, tmp_pte; 1269 1270 pte = __ptep_get_and_clear(mm, addr, ptep); 1271 while (--nr) { 1272 ptep++; 1273 addr += PAGE_SIZE; 1274 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1275 if (pte_dirty(tmp_pte)) 1276 pte = pte_mkdirty(pte); 1277 if (pte_young(tmp_pte)) 1278 pte = pte_mkyoung(pte); 1279 } 1280 return pte; 1281 } 1282 1283 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1284 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1285 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1286 unsigned long address, pmd_t *pmdp) 1287 { 1288 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1289 1290 page_table_check_pmd_clear(mm, pmd); 1291 1292 return pmd; 1293 } 1294 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1295 1296 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1297 unsigned long address, pte_t *ptep, 1298 pte_t pte) 1299 { 1300 pte_t old_pte; 1301 1302 do { 1303 old_pte = pte; 1304 pte = pte_wrprotect(pte); 1305 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1306 pte_val(old_pte), pte_val(pte)); 1307 } while (pte_val(pte) != pte_val(old_pte)); 1308 } 1309 1310 /* 1311 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1312 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1313 */ 1314 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1315 unsigned long address, pte_t *ptep) 1316 { 1317 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1318 } 1319 1320 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1321 pte_t *ptep, unsigned int nr) 1322 { 1323 unsigned int i; 1324 1325 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1326 __ptep_set_wrprotect(mm, address, ptep); 1327 } 1328 1329 static inline void __clear_young_dirty_pte(struct vm_area_struct *vma, 1330 unsigned long addr, pte_t *ptep, 1331 pte_t pte, cydp_t flags) 1332 { 1333 pte_t old_pte; 1334 1335 do { 1336 old_pte = pte; 1337 1338 if (flags & CYDP_CLEAR_YOUNG) 1339 pte = pte_mkold(pte); 1340 if (flags & CYDP_CLEAR_DIRTY) 1341 pte = pte_mkclean(pte); 1342 1343 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1344 pte_val(old_pte), pte_val(pte)); 1345 } while (pte_val(pte) != pte_val(old_pte)); 1346 } 1347 1348 static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma, 1349 unsigned long addr, pte_t *ptep, 1350 unsigned int nr, cydp_t flags) 1351 { 1352 pte_t pte; 1353 1354 for (;;) { 1355 pte = __ptep_get(ptep); 1356 1357 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY)) 1358 __set_pte(ptep, pte_mkclean(pte_mkold(pte))); 1359 else 1360 __clear_young_dirty_pte(vma, addr, ptep, pte, flags); 1361 1362 if (--nr == 0) 1363 break; 1364 ptep++; 1365 addr += PAGE_SIZE; 1366 } 1367 } 1368 1369 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1370 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1371 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1372 unsigned long address, pmd_t *pmdp) 1373 { 1374 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1375 } 1376 1377 #define pmdp_establish pmdp_establish 1378 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1379 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1380 { 1381 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1382 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1383 } 1384 #endif 1385 1386 /* 1387 * Encode and decode a swap entry: 1388 * bits 0-1: present (must be zero) 1389 * bits 2: remember PG_anon_exclusive 1390 * bit 3: remember uffd-wp state 1391 * bits 6-10: swap type 1392 * bit 11: PTE_PRESENT_INVALID (must be zero) 1393 * bits 12-61: swap offset 1394 */ 1395 #define __SWP_TYPE_SHIFT 6 1396 #define __SWP_TYPE_BITS 5 1397 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1398 #define __SWP_OFFSET_SHIFT 12 1399 #define __SWP_OFFSET_BITS 50 1400 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1401 1402 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1403 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1404 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1405 1406 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1407 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1408 1409 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1410 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1411 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1412 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1413 1414 /* 1415 * Ensure that there are not more swap files than can be encoded in the kernel 1416 * PTEs. 1417 */ 1418 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1419 1420 #ifdef CONFIG_ARM64_MTE 1421 1422 #define __HAVE_ARCH_PREPARE_TO_SWAP 1423 extern int arch_prepare_to_swap(struct folio *folio); 1424 1425 #define __HAVE_ARCH_SWAP_INVALIDATE 1426 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1427 { 1428 if (system_supports_mte()) 1429 mte_invalidate_tags(type, offset); 1430 } 1431 1432 static inline void arch_swap_invalidate_area(int type) 1433 { 1434 if (system_supports_mte()) 1435 mte_invalidate_tags_area(type); 1436 } 1437 1438 #define __HAVE_ARCH_SWAP_RESTORE 1439 extern void arch_swap_restore(swp_entry_t entry, struct folio *folio); 1440 1441 #endif /* CONFIG_ARM64_MTE */ 1442 1443 /* 1444 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1445 */ 1446 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1447 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1448 unsigned int nr) 1449 { 1450 /* 1451 * We don't do anything here, so there's a very small chance of 1452 * us retaking a user fault which we just fixed up. The alternative 1453 * is doing a dsb(ishst), but that penalises the fastpath. 1454 */ 1455 } 1456 1457 #define update_mmu_cache(vma, addr, ptep) \ 1458 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1459 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1460 1461 #ifdef CONFIG_ARM64_PA_BITS_52 1462 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1463 #else 1464 #define phys_to_ttbr(addr) (addr) 1465 #endif 1466 1467 /* 1468 * On arm64 without hardware Access Flag, copying from user will fail because 1469 * the pte is old and cannot be marked young. So we always end up with zeroed 1470 * page after fork() + CoW for pfn mappings. We don't always have a 1471 * hardware-managed access flag on arm64. 1472 */ 1473 #define arch_has_hw_pte_young cpu_has_hw_af 1474 1475 /* 1476 * Experimentally, it's cheap to set the access flag in hardware and we 1477 * benefit from prefaulting mappings as 'old' to start with. 1478 */ 1479 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1480 1481 static inline bool pud_sect_supported(void) 1482 { 1483 return PAGE_SIZE == SZ_4K; 1484 } 1485 1486 1487 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1488 #define ptep_modify_prot_start ptep_modify_prot_start 1489 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1490 unsigned long addr, pte_t *ptep); 1491 1492 #define ptep_modify_prot_commit ptep_modify_prot_commit 1493 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1494 unsigned long addr, pte_t *ptep, 1495 pte_t old_pte, pte_t new_pte); 1496 1497 #ifdef CONFIG_ARM64_CONTPTE 1498 1499 /* 1500 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1501 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1502 * a private implementation detail of the public ptep API (see below). 1503 */ 1504 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1505 pte_t *ptep, pte_t pte); 1506 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1507 pte_t *ptep, pte_t pte); 1508 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1509 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1510 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1511 pte_t *ptep, pte_t pte, unsigned int nr); 1512 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1513 pte_t *ptep, unsigned int nr, int full); 1514 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1515 unsigned long addr, pte_t *ptep, 1516 unsigned int nr, int full); 1517 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1518 unsigned long addr, pte_t *ptep); 1519 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1520 unsigned long addr, pte_t *ptep); 1521 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1522 pte_t *ptep, unsigned int nr); 1523 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1524 unsigned long addr, pte_t *ptep, 1525 pte_t entry, int dirty); 1526 extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma, 1527 unsigned long addr, pte_t *ptep, 1528 unsigned int nr, cydp_t flags); 1529 1530 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1531 unsigned long addr, pte_t *ptep, pte_t pte) 1532 { 1533 /* 1534 * Only bother trying if both the virtual and physical addresses are 1535 * aligned and correspond to the last entry in a contig range. The core 1536 * code mostly modifies ranges from low to high, so this is the likely 1537 * the last modification in the contig range, so a good time to fold. 1538 * We can't fold special mappings, because there is no associated folio. 1539 */ 1540 1541 const unsigned long contmask = CONT_PTES - 1; 1542 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1543 1544 if (unlikely(valign)) { 1545 bool palign = (pte_pfn(pte) & contmask) == contmask; 1546 1547 if (unlikely(palign && 1548 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1549 __contpte_try_fold(mm, addr, ptep, pte); 1550 } 1551 } 1552 1553 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1554 unsigned long addr, pte_t *ptep, pte_t pte) 1555 { 1556 if (unlikely(pte_valid_cont(pte))) 1557 __contpte_try_unfold(mm, addr, ptep, pte); 1558 } 1559 1560 #define pte_batch_hint pte_batch_hint 1561 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1562 { 1563 if (!pte_valid_cont(pte)) 1564 return 1; 1565 1566 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1567 } 1568 1569 /* 1570 * The below functions constitute the public API that arm64 presents to the 1571 * core-mm to manipulate PTE entries within their page tables (or at least this 1572 * is the subset of the API that arm64 needs to implement). These public 1573 * versions will automatically and transparently apply the contiguous bit where 1574 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1575 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1576 * private versions, which are prefixed with double underscore. All of these 1577 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1578 * held. Although the contiguous bit is considered private to the 1579 * implementation, it is deliberately allowed to leak through the getters (e.g. 1580 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1581 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1582 * its possible a pte will be passed to a setter with the contiguous bit set, so 1583 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1584 * setting it in the pgtable. 1585 */ 1586 1587 #define ptep_get ptep_get 1588 static inline pte_t ptep_get(pte_t *ptep) 1589 { 1590 pte_t pte = __ptep_get(ptep); 1591 1592 if (likely(!pte_valid_cont(pte))) 1593 return pte; 1594 1595 return contpte_ptep_get(ptep, pte); 1596 } 1597 1598 #define ptep_get_lockless ptep_get_lockless 1599 static inline pte_t ptep_get_lockless(pte_t *ptep) 1600 { 1601 pte_t pte = __ptep_get(ptep); 1602 1603 if (likely(!pte_valid_cont(pte))) 1604 return pte; 1605 1606 return contpte_ptep_get_lockless(ptep); 1607 } 1608 1609 static inline void set_pte(pte_t *ptep, pte_t pte) 1610 { 1611 /* 1612 * We don't have the mm or vaddr so cannot unfold contig entries (since 1613 * it requires tlb maintenance). set_pte() is not used in core code, so 1614 * this should never even be called. Regardless do our best to service 1615 * any call and emit a warning if there is any attempt to set a pte on 1616 * top of an existing contig range. 1617 */ 1618 pte_t orig_pte = __ptep_get(ptep); 1619 1620 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1621 __set_pte(ptep, pte_mknoncont(pte)); 1622 } 1623 1624 #define set_ptes set_ptes 1625 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1626 pte_t *ptep, pte_t pte, unsigned int nr) 1627 { 1628 pte = pte_mknoncont(pte); 1629 1630 if (likely(nr == 1)) { 1631 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1632 __set_ptes(mm, addr, ptep, pte, 1); 1633 contpte_try_fold(mm, addr, ptep, pte); 1634 } else { 1635 contpte_set_ptes(mm, addr, ptep, pte, nr); 1636 } 1637 } 1638 1639 static inline void pte_clear(struct mm_struct *mm, 1640 unsigned long addr, pte_t *ptep) 1641 { 1642 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1643 __pte_clear(mm, addr, ptep); 1644 } 1645 1646 #define clear_full_ptes clear_full_ptes 1647 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1648 pte_t *ptep, unsigned int nr, int full) 1649 { 1650 if (likely(nr == 1)) { 1651 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1652 __clear_full_ptes(mm, addr, ptep, nr, full); 1653 } else { 1654 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1655 } 1656 } 1657 1658 #define get_and_clear_full_ptes get_and_clear_full_ptes 1659 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1660 unsigned long addr, pte_t *ptep, 1661 unsigned int nr, int full) 1662 { 1663 pte_t pte; 1664 1665 if (likely(nr == 1)) { 1666 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1667 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1668 } else { 1669 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1670 } 1671 1672 return pte; 1673 } 1674 1675 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1676 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1677 unsigned long addr, pte_t *ptep) 1678 { 1679 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1680 return __ptep_get_and_clear(mm, addr, ptep); 1681 } 1682 1683 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1684 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1685 unsigned long addr, pte_t *ptep) 1686 { 1687 pte_t orig_pte = __ptep_get(ptep); 1688 1689 if (likely(!pte_valid_cont(orig_pte))) 1690 return __ptep_test_and_clear_young(vma, addr, ptep); 1691 1692 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1693 } 1694 1695 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1696 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1697 unsigned long addr, pte_t *ptep) 1698 { 1699 pte_t orig_pte = __ptep_get(ptep); 1700 1701 if (likely(!pte_valid_cont(orig_pte))) 1702 return __ptep_clear_flush_young(vma, addr, ptep); 1703 1704 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1705 } 1706 1707 #define wrprotect_ptes wrprotect_ptes 1708 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1709 unsigned long addr, pte_t *ptep, unsigned int nr) 1710 { 1711 if (likely(nr == 1)) { 1712 /* 1713 * Optimization: wrprotect_ptes() can only be called for present 1714 * ptes so we only need to check contig bit as condition for 1715 * unfold, and we can remove the contig bit from the pte we read 1716 * to avoid re-reading. This speeds up fork() which is sensitive 1717 * for order-0 folios. Equivalent to contpte_try_unfold(). 1718 */ 1719 pte_t orig_pte = __ptep_get(ptep); 1720 1721 if (unlikely(pte_cont(orig_pte))) { 1722 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1723 orig_pte = pte_mknoncont(orig_pte); 1724 } 1725 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1726 } else { 1727 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1728 } 1729 } 1730 1731 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1732 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1733 unsigned long addr, pte_t *ptep) 1734 { 1735 wrprotect_ptes(mm, addr, ptep, 1); 1736 } 1737 1738 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1739 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1740 unsigned long addr, pte_t *ptep, 1741 pte_t entry, int dirty) 1742 { 1743 pte_t orig_pte = __ptep_get(ptep); 1744 1745 entry = pte_mknoncont(entry); 1746 1747 if (likely(!pte_valid_cont(orig_pte))) 1748 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1749 1750 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1751 } 1752 1753 #define clear_young_dirty_ptes clear_young_dirty_ptes 1754 static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, 1755 unsigned long addr, pte_t *ptep, 1756 unsigned int nr, cydp_t flags) 1757 { 1758 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep)))) 1759 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1760 else 1761 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags); 1762 } 1763 1764 #else /* CONFIG_ARM64_CONTPTE */ 1765 1766 #define ptep_get __ptep_get 1767 #define set_pte __set_pte 1768 #define set_ptes __set_ptes 1769 #define pte_clear __pte_clear 1770 #define clear_full_ptes __clear_full_ptes 1771 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1772 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1773 #define ptep_get_and_clear __ptep_get_and_clear 1774 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1775 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1776 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1777 #define ptep_clear_flush_young __ptep_clear_flush_young 1778 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1779 #define ptep_set_wrprotect __ptep_set_wrprotect 1780 #define wrprotect_ptes __wrprotect_ptes 1781 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1782 #define ptep_set_access_flags __ptep_set_access_flags 1783 #define clear_young_dirty_ptes __clear_young_dirty_ptes 1784 1785 #endif /* CONFIG_ARM64_CONTPTE */ 1786 1787 #endif /* !__ASSEMBLY__ */ 1788 1789 #endif /* __ASM_PGTABLE_H */ 1790