1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_PGTABLE_H 6 #define __ASM_PGTABLE_H 7 8 #include <asm/bug.h> 9 #include <asm/proc-fns.h> 10 11 #include <asm/memory.h> 12 #include <asm/mte.h> 13 #include <asm/pgtable-hwdef.h> 14 #include <asm/pgtable-prot.h> 15 #include <asm/tlbflush.h> 16 17 /* 18 * VMALLOC range. 19 * 20 * VMALLOC_START: beginning of the kernel vmalloc space 21 * VMALLOC_END: extends to the available space below vmemmap 22 */ 23 #define VMALLOC_START (MODULES_END) 24 #if VA_BITS == VA_BITS_MIN 25 #define VMALLOC_END (VMEMMAP_START - SZ_8M) 26 #else 27 #define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT) 28 #define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M) 29 #endif 30 31 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 32 33 #ifndef __ASSEMBLY__ 34 35 #include <asm/cmpxchg.h> 36 #include <asm/fixmap.h> 37 #include <linux/mmdebug.h> 38 #include <linux/mm_types.h> 39 #include <linux/sched.h> 40 #include <linux/page_table_check.h> 41 42 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 43 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 44 45 /* Set stride and tlb_level in flush_*_tlb_range */ 46 #define flush_pmd_tlb_range(vma, addr, end) \ 47 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 48 #define flush_pud_tlb_range(vma, addr, end) \ 49 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 50 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 51 52 static inline bool arch_thp_swp_supported(void) 53 { 54 return !system_supports_mte(); 55 } 56 #define arch_thp_swp_supported arch_thp_swp_supported 57 58 /* 59 * Outside of a few very special situations (e.g. hibernation), we always 60 * use broadcast TLB invalidation instructions, therefore a spurious page 61 * fault on one CPU which has been handled concurrently by another CPU 62 * does not need to perform additional invalidation. 63 */ 64 #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 65 66 /* 67 * ZERO_PAGE is a global shared page that is always zero: used 68 * for zero-mapped memory areas etc.. 69 */ 70 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 71 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 72 73 #define pte_ERROR(e) \ 74 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 75 76 /* 77 * Macros to convert between a physical address and its placement in a 78 * page table entry, taking care of 52-bit addresses. 79 */ 80 #ifdef CONFIG_ARM64_PA_BITS_52 81 static inline phys_addr_t __pte_to_phys(pte_t pte) 82 { 83 pte_val(pte) &= ~PTE_MAYBE_SHARED; 84 return (pte_val(pte) & PTE_ADDR_LOW) | 85 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 86 } 87 static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 88 { 89 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK; 90 } 91 #else 92 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_LOW) 93 #define __phys_to_pte_val(phys) (phys) 94 #endif 95 96 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 97 #define pfn_pte(pfn,prot) \ 98 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 99 100 #define pte_none(pte) (!pte_val(pte)) 101 #define __pte_clear(mm, addr, ptep) \ 102 __set_pte(ptep, __pte(0)) 103 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 104 105 /* 106 * The following only work if pte_present(). Undefined behaviour otherwise. 107 */ 108 #define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte)) 109 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 110 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 111 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 112 #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 113 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 114 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 115 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 116 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 117 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 118 PTE_ATTRINDX(MT_NORMAL_TAGGED)) 119 120 #define pte_cont_addr_end(addr, end) \ 121 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 122 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 123 }) 124 125 #define pmd_cont_addr_end(addr, end) \ 126 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 127 (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 128 }) 129 130 #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 131 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 132 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 133 134 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 135 #define pte_present_invalid(pte) \ 136 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID) 137 /* 138 * Execute-only user mappings do not have the PTE_USER bit set. All valid 139 * kernel mappings have the PTE_UXN bit set. 140 */ 141 #define pte_valid_not_user(pte) \ 142 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 143 /* 144 * Returns true if the pte is valid and has the contiguous bit set. 145 */ 146 #define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte)) 147 /* 148 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 149 * so that we don't erroneously return false for pages that have been 150 * remapped as PROT_NONE but are yet to be flushed from the TLB. 151 * Note that we can't make any assumptions based on the state of the access 152 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the 153 * TLB. 154 */ 155 #define pte_accessible(mm, pte) \ 156 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 157 158 /* 159 * p??_access_permitted() is true for valid user mappings (PTE_USER 160 * bit set, subject to the write permission check). For execute-only 161 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 162 * not set) must return false. PROT_NONE mappings do not have the 163 * PTE_VALID bit set. 164 */ 165 #define pte_access_permitted(pte, write) \ 166 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 167 #define pmd_access_permitted(pmd, write) \ 168 (pte_access_permitted(pmd_pte(pmd), (write))) 169 #define pud_access_permitted(pud, write) \ 170 (pte_access_permitted(pud_pte(pud), (write))) 171 172 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 173 { 174 pte_val(pte) &= ~pgprot_val(prot); 175 return pte; 176 } 177 178 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 179 { 180 pte_val(pte) |= pgprot_val(prot); 181 return pte; 182 } 183 184 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 185 { 186 pmd_val(pmd) &= ~pgprot_val(prot); 187 return pmd; 188 } 189 190 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 191 { 192 pmd_val(pmd) |= pgprot_val(prot); 193 return pmd; 194 } 195 196 static inline pte_t pte_mkwrite_novma(pte_t pte) 197 { 198 pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 199 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 200 return pte; 201 } 202 203 static inline pte_t pte_mkclean(pte_t pte) 204 { 205 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 206 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 207 208 return pte; 209 } 210 211 static inline pte_t pte_mkdirty(pte_t pte) 212 { 213 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 214 215 if (pte_write(pte)) 216 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 217 218 return pte; 219 } 220 221 static inline pte_t pte_wrprotect(pte_t pte) 222 { 223 /* 224 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 225 * clear), set the PTE_DIRTY bit. 226 */ 227 if (pte_hw_dirty(pte)) 228 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 229 230 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 231 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 232 return pte; 233 } 234 235 static inline pte_t pte_mkold(pte_t pte) 236 { 237 return clear_pte_bit(pte, __pgprot(PTE_AF)); 238 } 239 240 static inline pte_t pte_mkyoung(pte_t pte) 241 { 242 return set_pte_bit(pte, __pgprot(PTE_AF)); 243 } 244 245 static inline pte_t pte_mkspecial(pte_t pte) 246 { 247 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 248 } 249 250 static inline pte_t pte_mkcont(pte_t pte) 251 { 252 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 253 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 254 } 255 256 static inline pte_t pte_mknoncont(pte_t pte) 257 { 258 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 259 } 260 261 static inline pte_t pte_mkpresent(pte_t pte) 262 { 263 return set_pte_bit(pte, __pgprot(PTE_VALID)); 264 } 265 266 static inline pte_t pte_mkinvalid(pte_t pte) 267 { 268 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID)); 269 pte = clear_pte_bit(pte, __pgprot(PTE_VALID)); 270 return pte; 271 } 272 273 static inline pmd_t pmd_mkcont(pmd_t pmd) 274 { 275 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 276 } 277 278 static inline pte_t pte_mkdevmap(pte_t pte) 279 { 280 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 281 } 282 283 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 284 static inline int pte_uffd_wp(pte_t pte) 285 { 286 return !!(pte_val(pte) & PTE_UFFD_WP); 287 } 288 289 static inline pte_t pte_mkuffd_wp(pte_t pte) 290 { 291 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP))); 292 } 293 294 static inline pte_t pte_clear_uffd_wp(pte_t pte) 295 { 296 return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP)); 297 } 298 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 299 300 static inline void __set_pte_nosync(pte_t *ptep, pte_t pte) 301 { 302 WRITE_ONCE(*ptep, pte); 303 } 304 305 static inline void __set_pte(pte_t *ptep, pte_t pte) 306 { 307 __set_pte_nosync(ptep, pte); 308 309 /* 310 * Only if the new pte is valid and kernel, otherwise TLB maintenance 311 * or update_mmu_cache() have the necessary barriers. 312 */ 313 if (pte_valid_not_user(pte)) { 314 dsb(ishst); 315 isb(); 316 } 317 } 318 319 static inline pte_t __ptep_get(pte_t *ptep) 320 { 321 return READ_ONCE(*ptep); 322 } 323 324 extern void __sync_icache_dcache(pte_t pteval); 325 bool pgattr_change_is_safe(u64 old, u64 new); 326 327 /* 328 * PTE bits configuration in the presence of hardware Dirty Bit Management 329 * (PTE_WRITE == PTE_DBM): 330 * 331 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 332 * 0 0 | 1 0 0 333 * 0 1 | 1 1 0 334 * 1 0 | 1 0 1 335 * 1 1 | 0 1 x 336 * 337 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 338 * the page fault mechanism. Checking the dirty status of a pte becomes: 339 * 340 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 341 */ 342 343 static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 344 pte_t pte) 345 { 346 pte_t old_pte; 347 348 if (!IS_ENABLED(CONFIG_DEBUG_VM)) 349 return; 350 351 old_pte = __ptep_get(ptep); 352 353 if (!pte_valid(old_pte) || !pte_valid(pte)) 354 return; 355 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 356 return; 357 358 /* 359 * Check for potential race with hardware updates of the pte 360 * (__ptep_set_access_flags safely changes valid ptes without going 361 * through an invalid entry). 362 */ 363 VM_WARN_ONCE(!pte_young(pte), 364 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 365 __func__, pte_val(old_pte), pte_val(pte)); 366 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 367 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 368 __func__, pte_val(old_pte), pte_val(pte)); 369 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 370 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 371 __func__, pte_val(old_pte), pte_val(pte)); 372 } 373 374 static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 375 { 376 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 377 __sync_icache_dcache(pte); 378 379 /* 380 * If the PTE would provide user space access to the tags associated 381 * with it then ensure that the MTE tags are synchronised. Although 382 * pte_access_permitted() returns false for exec only mappings, they 383 * don't expose tags (instruction fetches don't check tags). 384 */ 385 if (system_supports_mte() && pte_access_permitted(pte, false) && 386 !pte_special(pte) && pte_tagged(pte)) 387 mte_sync_tags(pte, nr_pages); 388 } 389 390 /* 391 * Select all bits except the pfn 392 */ 393 static inline pgprot_t pte_pgprot(pte_t pte) 394 { 395 unsigned long pfn = pte_pfn(pte); 396 397 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 398 } 399 400 #define pte_advance_pfn pte_advance_pfn 401 static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr) 402 { 403 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte)); 404 } 405 406 static inline void __set_ptes(struct mm_struct *mm, 407 unsigned long __always_unused addr, 408 pte_t *ptep, pte_t pte, unsigned int nr) 409 { 410 page_table_check_ptes_set(mm, ptep, pte, nr); 411 __sync_cache_and_tags(pte, nr); 412 413 for (;;) { 414 __check_safe_pte_update(mm, ptep, pte); 415 __set_pte(ptep, pte); 416 if (--nr == 0) 417 break; 418 ptep++; 419 pte = pte_advance_pfn(pte, 1); 420 } 421 } 422 423 /* 424 * Huge pte definitions. 425 */ 426 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 427 428 /* 429 * Hugetlb definitions. 430 */ 431 #define HUGE_MAX_HSTATE 4 432 #define HPAGE_SHIFT PMD_SHIFT 433 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 434 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 435 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 436 437 static inline pte_t pgd_pte(pgd_t pgd) 438 { 439 return __pte(pgd_val(pgd)); 440 } 441 442 static inline pte_t p4d_pte(p4d_t p4d) 443 { 444 return __pte(p4d_val(p4d)); 445 } 446 447 static inline pte_t pud_pte(pud_t pud) 448 { 449 return __pte(pud_val(pud)); 450 } 451 452 static inline pud_t pte_pud(pte_t pte) 453 { 454 return __pud(pte_val(pte)); 455 } 456 457 static inline pmd_t pud_pmd(pud_t pud) 458 { 459 return __pmd(pud_val(pud)); 460 } 461 462 static inline pte_t pmd_pte(pmd_t pmd) 463 { 464 return __pte(pmd_val(pmd)); 465 } 466 467 static inline pmd_t pte_pmd(pte_t pte) 468 { 469 return __pmd(pte_val(pte)); 470 } 471 472 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 473 { 474 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 475 } 476 477 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 478 { 479 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 480 } 481 482 static inline pte_t pte_swp_mkexclusive(pte_t pte) 483 { 484 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 485 } 486 487 static inline int pte_swp_exclusive(pte_t pte) 488 { 489 return pte_val(pte) & PTE_SWP_EXCLUSIVE; 490 } 491 492 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 493 { 494 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 495 } 496 497 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 498 static inline pte_t pte_swp_mkuffd_wp(pte_t pte) 499 { 500 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 501 } 502 503 static inline int pte_swp_uffd_wp(pte_t pte) 504 { 505 return !!(pte_val(pte) & PTE_SWP_UFFD_WP); 506 } 507 508 static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) 509 { 510 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP)); 511 } 512 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 513 514 #ifdef CONFIG_NUMA_BALANCING 515 /* 516 * See the comment in include/linux/pgtable.h 517 */ 518 static inline int pte_protnone(pte_t pte) 519 { 520 /* 521 * pte_present_invalid() tells us that the pte is invalid from HW 522 * perspective but present from SW perspective, so the fields are to be 523 * interpretted as per the HW layout. The second 2 checks are the unique 524 * encoding that we use for PROT_NONE. It is insufficient to only use 525 * the first check because we share the same encoding scheme with pmds 526 * which support pmd_mkinvalid(), so can be present-invalid without 527 * being PROT_NONE. 528 */ 529 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte); 530 } 531 532 static inline int pmd_protnone(pmd_t pmd) 533 { 534 return pte_protnone(pmd_pte(pmd)); 535 } 536 #endif 537 538 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 539 540 /* 541 * THP definitions. 542 */ 543 544 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 545 static inline int pmd_trans_huge(pmd_t pmd) 546 { 547 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 548 } 549 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 550 551 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 552 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 553 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 554 #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 555 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 556 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 557 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 558 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 559 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 560 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 561 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 562 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 563 #define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd))) 564 #ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP 565 #define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd)) 566 #define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))) 567 #define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))) 568 #define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd)) 569 #define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))) 570 #define pmd_swp_clear_uffd_wp(pmd) \ 571 pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))) 572 #endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ 573 574 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 575 576 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 577 578 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 579 580 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 581 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 582 #endif 583 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 584 { 585 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 586 } 587 588 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 589 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 590 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 591 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 592 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 593 594 #define pud_young(pud) pte_young(pud_pte(pud)) 595 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 596 #define pud_write(pud) pte_write(pud_pte(pud)) 597 598 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 599 600 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 601 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 602 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 603 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 604 605 static inline void __set_pte_at(struct mm_struct *mm, 606 unsigned long __always_unused addr, 607 pte_t *ptep, pte_t pte, unsigned int nr) 608 { 609 __sync_cache_and_tags(pte, nr); 610 __check_safe_pte_update(mm, ptep, pte); 611 __set_pte(ptep, pte); 612 } 613 614 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 615 pmd_t *pmdp, pmd_t pmd) 616 { 617 page_table_check_pmd_set(mm, pmdp, pmd); 618 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 619 PMD_SIZE >> PAGE_SHIFT); 620 } 621 622 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 623 pud_t *pudp, pud_t pud) 624 { 625 page_table_check_pud_set(mm, pudp, pud); 626 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 627 PUD_SIZE >> PAGE_SHIFT); 628 } 629 630 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 631 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 632 633 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 634 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 635 636 #define __pgprot_modify(prot,mask,bits) \ 637 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 638 639 #define pgprot_nx(prot) \ 640 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 641 642 /* 643 * Mark the prot value as uncacheable and unbufferable. 644 */ 645 #define pgprot_noncached(prot) \ 646 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 647 #define pgprot_writecombine(prot) \ 648 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 649 #define pgprot_device(prot) \ 650 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 651 #define pgprot_tagged(prot) \ 652 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 653 #define pgprot_mhp pgprot_tagged 654 /* 655 * DMA allocations for non-coherent devices use what the Arm architecture calls 656 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 657 * and merging of writes. This is different from "Device-nGnR[nE]" memory which 658 * is intended for MMIO and thus forbids speculation, preserves access size, 659 * requires strict alignment and can also force write responses to come from the 660 * endpoint. 661 */ 662 #define pgprot_dmacoherent(prot) \ 663 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 664 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 665 666 #define __HAVE_PHYS_MEM_ACCESS_PROT 667 struct file; 668 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 669 unsigned long size, pgprot_t vma_prot); 670 671 #define pmd_none(pmd) (!pmd_val(pmd)) 672 673 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 674 PMD_TYPE_TABLE) 675 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 676 PMD_TYPE_SECT) 677 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 678 #define pmd_bad(pmd) (!pmd_table(pmd)) 679 680 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 681 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 682 683 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 684 static inline bool pud_sect(pud_t pud) { return false; } 685 static inline bool pud_table(pud_t pud) { return true; } 686 #else 687 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 688 PUD_TYPE_SECT) 689 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 690 PUD_TYPE_TABLE) 691 #endif 692 693 extern pgd_t init_pg_dir[]; 694 extern pgd_t init_pg_end[]; 695 extern pgd_t swapper_pg_dir[]; 696 extern pgd_t idmap_pg_dir[]; 697 extern pgd_t tramp_pg_dir[]; 698 extern pgd_t reserved_pg_dir[]; 699 700 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 701 702 static inline bool in_swapper_pgdir(void *addr) 703 { 704 return ((unsigned long)addr & PAGE_MASK) == 705 ((unsigned long)swapper_pg_dir & PAGE_MASK); 706 } 707 708 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 709 { 710 #ifdef __PAGETABLE_PMD_FOLDED 711 if (in_swapper_pgdir(pmdp)) { 712 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 713 return; 714 } 715 #endif /* __PAGETABLE_PMD_FOLDED */ 716 717 WRITE_ONCE(*pmdp, pmd); 718 719 if (pmd_valid(pmd)) { 720 dsb(ishst); 721 isb(); 722 } 723 } 724 725 static inline void pmd_clear(pmd_t *pmdp) 726 { 727 set_pmd(pmdp, __pmd(0)); 728 } 729 730 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 731 { 732 return __pmd_to_phys(pmd); 733 } 734 735 static inline unsigned long pmd_page_vaddr(pmd_t pmd) 736 { 737 return (unsigned long)__va(pmd_page_paddr(pmd)); 738 } 739 740 /* Find an entry in the third-level page table. */ 741 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 742 743 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 744 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 745 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 746 747 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 748 749 /* use ONLY for statically allocated translation tables */ 750 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 751 752 /* 753 * Conversion functions: convert a page and protection to a page entry, 754 * and a page entry and page directory to the page they refer to. 755 */ 756 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 757 758 #if CONFIG_PGTABLE_LEVELS > 2 759 760 #define pmd_ERROR(e) \ 761 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 762 763 #define pud_none(pud) (!pud_val(pud)) 764 #define pud_bad(pud) (!pud_table(pud)) 765 #define pud_present(pud) pte_present(pud_pte(pud)) 766 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 767 #define pud_valid(pud) pte_valid(pud_pte(pud)) 768 #define pud_user(pud) pte_user(pud_pte(pud)) 769 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 770 771 static inline bool pgtable_l4_enabled(void); 772 773 static inline void set_pud(pud_t *pudp, pud_t pud) 774 { 775 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) { 776 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 777 return; 778 } 779 780 WRITE_ONCE(*pudp, pud); 781 782 if (pud_valid(pud)) { 783 dsb(ishst); 784 isb(); 785 } 786 } 787 788 static inline void pud_clear(pud_t *pudp) 789 { 790 set_pud(pudp, __pud(0)); 791 } 792 793 static inline phys_addr_t pud_page_paddr(pud_t pud) 794 { 795 return __pud_to_phys(pud); 796 } 797 798 static inline pmd_t *pud_pgtable(pud_t pud) 799 { 800 return (pmd_t *)__va(pud_page_paddr(pud)); 801 } 802 803 /* Find an entry in the second-level page table. */ 804 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 805 806 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 807 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 808 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 809 810 #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 811 812 /* use ONLY for statically allocated translation tables */ 813 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 814 815 #else 816 817 #define pud_valid(pud) false 818 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 819 #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 820 821 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 822 #define pmd_set_fixmap(addr) NULL 823 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 824 #define pmd_clear_fixmap() 825 826 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 827 828 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 829 830 #if CONFIG_PGTABLE_LEVELS > 3 831 832 static __always_inline bool pgtable_l4_enabled(void) 833 { 834 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2)) 835 return true; 836 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 837 return vabits_actual == VA_BITS; 838 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 839 } 840 841 static inline bool mm_pud_folded(const struct mm_struct *mm) 842 { 843 return !pgtable_l4_enabled(); 844 } 845 #define mm_pud_folded mm_pud_folded 846 847 #define pud_ERROR(e) \ 848 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 849 850 #define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d)) 851 #define p4d_bad(p4d) (pgtable_l4_enabled() && !(p4d_val(p4d) & 2)) 852 #define p4d_present(p4d) (!p4d_none(p4d)) 853 854 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 855 { 856 if (in_swapper_pgdir(p4dp)) { 857 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 858 return; 859 } 860 861 WRITE_ONCE(*p4dp, p4d); 862 dsb(ishst); 863 isb(); 864 } 865 866 static inline void p4d_clear(p4d_t *p4dp) 867 { 868 if (pgtable_l4_enabled()) 869 set_p4d(p4dp, __p4d(0)); 870 } 871 872 static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 873 { 874 return __p4d_to_phys(p4d); 875 } 876 877 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 878 879 static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr) 880 { 881 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr); 882 } 883 884 static inline pud_t *p4d_pgtable(p4d_t p4d) 885 { 886 return (pud_t *)__va(p4d_page_paddr(p4d)); 887 } 888 889 static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr) 890 { 891 BUG_ON(!pgtable_l4_enabled()); 892 893 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t); 894 } 895 896 static inline 897 pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr) 898 { 899 if (!pgtable_l4_enabled()) 900 return p4d_to_folded_pud(p4dp, addr); 901 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr); 902 } 903 #define pud_offset_lockless pud_offset_lockless 904 905 static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr) 906 { 907 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr); 908 } 909 #define pud_offset pud_offset 910 911 static inline pud_t *pud_set_fixmap(unsigned long addr) 912 { 913 if (!pgtable_l4_enabled()) 914 return NULL; 915 return (pud_t *)set_fixmap_offset(FIX_PUD, addr); 916 } 917 918 static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr) 919 { 920 if (!pgtable_l4_enabled()) 921 return p4d_to_folded_pud(p4dp, addr); 922 return pud_set_fixmap(pud_offset_phys(p4dp, addr)); 923 } 924 925 static inline void pud_clear_fixmap(void) 926 { 927 if (pgtable_l4_enabled()) 928 clear_fixmap(FIX_PUD); 929 } 930 931 /* use ONLY for statically allocated translation tables */ 932 static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr) 933 { 934 if (!pgtable_l4_enabled()) 935 return p4d_to_folded_pud(p4dp, addr); 936 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr)); 937 } 938 939 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 940 941 #else 942 943 static inline bool pgtable_l4_enabled(void) { return false; } 944 945 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 946 947 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 948 #define pud_set_fixmap(addr) NULL 949 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 950 #define pud_clear_fixmap() 951 952 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 953 954 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 955 956 #if CONFIG_PGTABLE_LEVELS > 4 957 958 static __always_inline bool pgtable_l5_enabled(void) 959 { 960 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT)) 961 return vabits_actual == VA_BITS; 962 return alternative_has_cap_unlikely(ARM64_HAS_VA52); 963 } 964 965 static inline bool mm_p4d_folded(const struct mm_struct *mm) 966 { 967 return !pgtable_l5_enabled(); 968 } 969 #define mm_p4d_folded mm_p4d_folded 970 971 #define p4d_ERROR(e) \ 972 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e)) 973 974 #define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd)) 975 #define pgd_bad(pgd) (pgtable_l5_enabled() && !(pgd_val(pgd) & 2)) 976 #define pgd_present(pgd) (!pgd_none(pgd)) 977 978 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 979 { 980 if (in_swapper_pgdir(pgdp)) { 981 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd))); 982 return; 983 } 984 985 WRITE_ONCE(*pgdp, pgd); 986 dsb(ishst); 987 isb(); 988 } 989 990 static inline void pgd_clear(pgd_t *pgdp) 991 { 992 if (pgtable_l5_enabled()) 993 set_pgd(pgdp, __pgd(0)); 994 } 995 996 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 997 { 998 return __pgd_to_phys(pgd); 999 } 1000 1001 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1002 1003 static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr) 1004 { 1005 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr); 1006 } 1007 1008 static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr) 1009 { 1010 BUG_ON(!pgtable_l5_enabled()); 1011 1012 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t); 1013 } 1014 1015 static inline 1016 p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr) 1017 { 1018 if (!pgtable_l5_enabled()) 1019 return pgd_to_folded_p4d(pgdp, addr); 1020 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr); 1021 } 1022 #define p4d_offset_lockless p4d_offset_lockless 1023 1024 static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr) 1025 { 1026 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr); 1027 } 1028 1029 static inline p4d_t *p4d_set_fixmap(unsigned long addr) 1030 { 1031 if (!pgtable_l5_enabled()) 1032 return NULL; 1033 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr); 1034 } 1035 1036 static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr) 1037 { 1038 if (!pgtable_l5_enabled()) 1039 return pgd_to_folded_p4d(pgdp, addr); 1040 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr)); 1041 } 1042 1043 static inline void p4d_clear_fixmap(void) 1044 { 1045 if (pgtable_l5_enabled()) 1046 clear_fixmap(FIX_P4D); 1047 } 1048 1049 /* use ONLY for statically allocated translation tables */ 1050 static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr) 1051 { 1052 if (!pgtable_l5_enabled()) 1053 return pgd_to_folded_p4d(pgdp, addr); 1054 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr)); 1055 } 1056 1057 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 1058 1059 #else 1060 1061 static inline bool pgtable_l5_enabled(void) { return false; } 1062 1063 #define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1)) 1064 1065 /* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */ 1066 #define p4d_set_fixmap(addr) NULL 1067 #define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp) 1068 #define p4d_clear_fixmap() 1069 1070 #define p4d_offset_kimg(dir,addr) ((p4d_t *)dir) 1071 1072 #endif /* CONFIG_PGTABLE_LEVELS > 4 */ 1073 1074 #define pgd_ERROR(e) \ 1075 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 1076 1077 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 1078 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 1079 1080 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 1081 { 1082 /* 1083 * Normal and Normal-Tagged are two different memory types and indices 1084 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 1085 */ 1086 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 1087 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE | 1088 PTE_GP | PTE_ATTRINDX_MASK; 1089 /* preserve the hardware dirty information */ 1090 if (pte_hw_dirty(pte)) 1091 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1092 1093 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 1094 /* 1095 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 1096 * dirtiness again. 1097 */ 1098 if (pte_sw_dirty(pte)) 1099 pte = pte_mkdirty(pte); 1100 return pte; 1101 } 1102 1103 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 1104 { 1105 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 1106 } 1107 1108 extern int __ptep_set_access_flags(struct vm_area_struct *vma, 1109 unsigned long address, pte_t *ptep, 1110 pte_t entry, int dirty); 1111 1112 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1113 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1114 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 1115 unsigned long address, pmd_t *pmdp, 1116 pmd_t entry, int dirty) 1117 { 1118 return __ptep_set_access_flags(vma, address, (pte_t *)pmdp, 1119 pmd_pte(entry), dirty); 1120 } 1121 1122 static inline int pud_devmap(pud_t pud) 1123 { 1124 return 0; 1125 } 1126 1127 static inline int pgd_devmap(pgd_t pgd) 1128 { 1129 return 0; 1130 } 1131 #endif 1132 1133 #ifdef CONFIG_PAGE_TABLE_CHECK 1134 static inline bool pte_user_accessible_page(pte_t pte) 1135 { 1136 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte)); 1137 } 1138 1139 static inline bool pmd_user_accessible_page(pmd_t pmd) 1140 { 1141 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 1142 } 1143 1144 static inline bool pud_user_accessible_page(pud_t pud) 1145 { 1146 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud)); 1147 } 1148 #endif 1149 1150 /* 1151 * Atomic pte/pmd modifications. 1152 */ 1153 static inline int __ptep_test_and_clear_young(struct vm_area_struct *vma, 1154 unsigned long address, 1155 pte_t *ptep) 1156 { 1157 pte_t old_pte, pte; 1158 1159 pte = __ptep_get(ptep); 1160 do { 1161 old_pte = pte; 1162 pte = pte_mkold(pte); 1163 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1164 pte_val(old_pte), pte_val(pte)); 1165 } while (pte_val(pte) != pte_val(old_pte)); 1166 1167 return pte_young(pte); 1168 } 1169 1170 static inline int __ptep_clear_flush_young(struct vm_area_struct *vma, 1171 unsigned long address, pte_t *ptep) 1172 { 1173 int young = __ptep_test_and_clear_young(vma, address, ptep); 1174 1175 if (young) { 1176 /* 1177 * We can elide the trailing DSB here since the worst that can 1178 * happen is that a CPU continues to use the young entry in its 1179 * TLB and we mistakenly reclaim the associated page. The 1180 * window for such an event is bounded by the next 1181 * context-switch, which provides a DSB to complete the TLB 1182 * invalidation. 1183 */ 1184 flush_tlb_page_nosync(vma, address); 1185 } 1186 1187 return young; 1188 } 1189 1190 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1191 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1192 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1193 unsigned long address, 1194 pmd_t *pmdp) 1195 { 1196 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 1197 } 1198 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1199 1200 static inline pte_t __ptep_get_and_clear(struct mm_struct *mm, 1201 unsigned long address, pte_t *ptep) 1202 { 1203 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 1204 1205 page_table_check_pte_clear(mm, pte); 1206 1207 return pte; 1208 } 1209 1210 static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1211 pte_t *ptep, unsigned int nr, int full) 1212 { 1213 for (;;) { 1214 __ptep_get_and_clear(mm, addr, ptep); 1215 if (--nr == 0) 1216 break; 1217 ptep++; 1218 addr += PAGE_SIZE; 1219 } 1220 } 1221 1222 static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm, 1223 unsigned long addr, pte_t *ptep, 1224 unsigned int nr, int full) 1225 { 1226 pte_t pte, tmp_pte; 1227 1228 pte = __ptep_get_and_clear(mm, addr, ptep); 1229 while (--nr) { 1230 ptep++; 1231 addr += PAGE_SIZE; 1232 tmp_pte = __ptep_get_and_clear(mm, addr, ptep); 1233 if (pte_dirty(tmp_pte)) 1234 pte = pte_mkdirty(pte); 1235 if (pte_young(tmp_pte)) 1236 pte = pte_mkyoung(pte); 1237 } 1238 return pte; 1239 } 1240 1241 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1242 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1243 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1244 unsigned long address, pmd_t *pmdp) 1245 { 1246 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 1247 1248 page_table_check_pmd_clear(mm, pmd); 1249 1250 return pmd; 1251 } 1252 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1253 1254 static inline void ___ptep_set_wrprotect(struct mm_struct *mm, 1255 unsigned long address, pte_t *ptep, 1256 pte_t pte) 1257 { 1258 pte_t old_pte; 1259 1260 do { 1261 old_pte = pte; 1262 pte = pte_wrprotect(pte); 1263 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 1264 pte_val(old_pte), pte_val(pte)); 1265 } while (pte_val(pte) != pte_val(old_pte)); 1266 } 1267 1268 /* 1269 * __ptep_set_wrprotect - mark read-only while trasferring potential hardware 1270 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 1271 */ 1272 static inline void __ptep_set_wrprotect(struct mm_struct *mm, 1273 unsigned long address, pte_t *ptep) 1274 { 1275 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep)); 1276 } 1277 1278 static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address, 1279 pte_t *ptep, unsigned int nr) 1280 { 1281 unsigned int i; 1282 1283 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++) 1284 __ptep_set_wrprotect(mm, address, ptep); 1285 } 1286 1287 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1288 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1289 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 1290 unsigned long address, pmd_t *pmdp) 1291 { 1292 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 1293 } 1294 1295 #define pmdp_establish pmdp_establish 1296 static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 1297 unsigned long address, pmd_t *pmdp, pmd_t pmd) 1298 { 1299 page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 1300 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 1301 } 1302 #endif 1303 1304 /* 1305 * Encode and decode a swap entry: 1306 * bits 0-1: present (must be zero) 1307 * bits 2: remember PG_anon_exclusive 1308 * bit 3: remember uffd-wp state 1309 * bits 6-10: swap type 1310 * bit 11: PTE_PRESENT_INVALID (must be zero) 1311 * bits 12-61: swap offset 1312 */ 1313 #define __SWP_TYPE_SHIFT 6 1314 #define __SWP_TYPE_BITS 5 1315 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 1316 #define __SWP_OFFSET_SHIFT 12 1317 #define __SWP_OFFSET_BITS 50 1318 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 1319 1320 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 1321 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 1322 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 1323 1324 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 1325 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 1326 1327 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1328 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 1329 #define __swp_entry_to_pmd(swp) __pmd((swp).val) 1330 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 1331 1332 /* 1333 * Ensure that there are not more swap files than can be encoded in the kernel 1334 * PTEs. 1335 */ 1336 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 1337 1338 #ifdef CONFIG_ARM64_MTE 1339 1340 #define __HAVE_ARCH_PREPARE_TO_SWAP 1341 static inline int arch_prepare_to_swap(struct page *page) 1342 { 1343 if (system_supports_mte()) 1344 return mte_save_tags(page); 1345 return 0; 1346 } 1347 1348 #define __HAVE_ARCH_SWAP_INVALIDATE 1349 static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 1350 { 1351 if (system_supports_mte()) 1352 mte_invalidate_tags(type, offset); 1353 } 1354 1355 static inline void arch_swap_invalidate_area(int type) 1356 { 1357 if (system_supports_mte()) 1358 mte_invalidate_tags_area(type); 1359 } 1360 1361 #define __HAVE_ARCH_SWAP_RESTORE 1362 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 1363 { 1364 if (system_supports_mte()) 1365 mte_restore_tags(entry, &folio->page); 1366 } 1367 1368 #endif /* CONFIG_ARM64_MTE */ 1369 1370 /* 1371 * On AArch64, the cache coherency is handled via the __set_ptes() function. 1372 */ 1373 static inline void update_mmu_cache_range(struct vm_fault *vmf, 1374 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 1375 unsigned int nr) 1376 { 1377 /* 1378 * We don't do anything here, so there's a very small chance of 1379 * us retaking a user fault which we just fixed up. The alternative 1380 * is doing a dsb(ishst), but that penalises the fastpath. 1381 */ 1382 } 1383 1384 #define update_mmu_cache(vma, addr, ptep) \ 1385 update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1386 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1387 1388 #ifdef CONFIG_ARM64_PA_BITS_52 1389 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1390 #else 1391 #define phys_to_ttbr(addr) (addr) 1392 #endif 1393 1394 /* 1395 * On arm64 without hardware Access Flag, copying from user will fail because 1396 * the pte is old and cannot be marked young. So we always end up with zeroed 1397 * page after fork() + CoW for pfn mappings. We don't always have a 1398 * hardware-managed access flag on arm64. 1399 */ 1400 #define arch_has_hw_pte_young cpu_has_hw_af 1401 1402 /* 1403 * Experimentally, it's cheap to set the access flag in hardware and we 1404 * benefit from prefaulting mappings as 'old' to start with. 1405 */ 1406 #define arch_wants_old_prefaulted_pte cpu_has_hw_af 1407 1408 static inline bool pud_sect_supported(void) 1409 { 1410 return PAGE_SIZE == SZ_4K; 1411 } 1412 1413 1414 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1415 #define ptep_modify_prot_start ptep_modify_prot_start 1416 extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 1417 unsigned long addr, pte_t *ptep); 1418 1419 #define ptep_modify_prot_commit ptep_modify_prot_commit 1420 extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 1421 unsigned long addr, pte_t *ptep, 1422 pte_t old_pte, pte_t new_pte); 1423 1424 #ifdef CONFIG_ARM64_CONTPTE 1425 1426 /* 1427 * The contpte APIs are used to transparently manage the contiguous bit in ptes 1428 * where it is possible and makes sense to do so. The PTE_CONT bit is considered 1429 * a private implementation detail of the public ptep API (see below). 1430 */ 1431 extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr, 1432 pte_t *ptep, pte_t pte); 1433 extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr, 1434 pte_t *ptep, pte_t pte); 1435 extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte); 1436 extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep); 1437 extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr, 1438 pte_t *ptep, pte_t pte, unsigned int nr); 1439 extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1440 pte_t *ptep, unsigned int nr, int full); 1441 extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm, 1442 unsigned long addr, pte_t *ptep, 1443 unsigned int nr, int full); 1444 extern int contpte_ptep_test_and_clear_young(struct vm_area_struct *vma, 1445 unsigned long addr, pte_t *ptep); 1446 extern int contpte_ptep_clear_flush_young(struct vm_area_struct *vma, 1447 unsigned long addr, pte_t *ptep); 1448 extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr, 1449 pte_t *ptep, unsigned int nr); 1450 extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma, 1451 unsigned long addr, pte_t *ptep, 1452 pte_t entry, int dirty); 1453 1454 static __always_inline void contpte_try_fold(struct mm_struct *mm, 1455 unsigned long addr, pte_t *ptep, pte_t pte) 1456 { 1457 /* 1458 * Only bother trying if both the virtual and physical addresses are 1459 * aligned and correspond to the last entry in a contig range. The core 1460 * code mostly modifies ranges from low to high, so this is the likely 1461 * the last modification in the contig range, so a good time to fold. 1462 * We can't fold special mappings, because there is no associated folio. 1463 */ 1464 1465 const unsigned long contmask = CONT_PTES - 1; 1466 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask; 1467 1468 if (unlikely(valign)) { 1469 bool palign = (pte_pfn(pte) & contmask) == contmask; 1470 1471 if (unlikely(palign && 1472 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte))) 1473 __contpte_try_fold(mm, addr, ptep, pte); 1474 } 1475 } 1476 1477 static __always_inline void contpte_try_unfold(struct mm_struct *mm, 1478 unsigned long addr, pte_t *ptep, pte_t pte) 1479 { 1480 if (unlikely(pte_valid_cont(pte))) 1481 __contpte_try_unfold(mm, addr, ptep, pte); 1482 } 1483 1484 #define pte_batch_hint pte_batch_hint 1485 static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte) 1486 { 1487 if (!pte_valid_cont(pte)) 1488 return 1; 1489 1490 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1)); 1491 } 1492 1493 /* 1494 * The below functions constitute the public API that arm64 presents to the 1495 * core-mm to manipulate PTE entries within their page tables (or at least this 1496 * is the subset of the API that arm64 needs to implement). These public 1497 * versions will automatically and transparently apply the contiguous bit where 1498 * it makes sense to do so. Therefore any users that are contig-aware (e.g. 1499 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the 1500 * private versions, which are prefixed with double underscore. All of these 1501 * APIs except for ptep_get_lockless() are expected to be called with the PTL 1502 * held. Although the contiguous bit is considered private to the 1503 * implementation, it is deliberately allowed to leak through the getters (e.g. 1504 * ptep_get()), back to core code. This is required so that pte_leaf_size() can 1505 * provide an accurate size for perf_get_pgtable_size(). But this leakage means 1506 * its possible a pte will be passed to a setter with the contiguous bit set, so 1507 * we explicitly clear the contiguous bit in those cases to prevent accidentally 1508 * setting it in the pgtable. 1509 */ 1510 1511 #define ptep_get ptep_get 1512 static inline pte_t ptep_get(pte_t *ptep) 1513 { 1514 pte_t pte = __ptep_get(ptep); 1515 1516 if (likely(!pte_valid_cont(pte))) 1517 return pte; 1518 1519 return contpte_ptep_get(ptep, pte); 1520 } 1521 1522 #define ptep_get_lockless ptep_get_lockless 1523 static inline pte_t ptep_get_lockless(pte_t *ptep) 1524 { 1525 pte_t pte = __ptep_get(ptep); 1526 1527 if (likely(!pte_valid_cont(pte))) 1528 return pte; 1529 1530 return contpte_ptep_get_lockless(ptep); 1531 } 1532 1533 static inline void set_pte(pte_t *ptep, pte_t pte) 1534 { 1535 /* 1536 * We don't have the mm or vaddr so cannot unfold contig entries (since 1537 * it requires tlb maintenance). set_pte() is not used in core code, so 1538 * this should never even be called. Regardless do our best to service 1539 * any call and emit a warning if there is any attempt to set a pte on 1540 * top of an existing contig range. 1541 */ 1542 pte_t orig_pte = __ptep_get(ptep); 1543 1544 WARN_ON_ONCE(pte_valid_cont(orig_pte)); 1545 __set_pte(ptep, pte_mknoncont(pte)); 1546 } 1547 1548 #define set_ptes set_ptes 1549 static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr, 1550 pte_t *ptep, pte_t pte, unsigned int nr) 1551 { 1552 pte = pte_mknoncont(pte); 1553 1554 if (likely(nr == 1)) { 1555 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1556 __set_ptes(mm, addr, ptep, pte, 1); 1557 contpte_try_fold(mm, addr, ptep, pte); 1558 } else { 1559 contpte_set_ptes(mm, addr, ptep, pte, nr); 1560 } 1561 } 1562 1563 static inline void pte_clear(struct mm_struct *mm, 1564 unsigned long addr, pte_t *ptep) 1565 { 1566 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1567 __pte_clear(mm, addr, ptep); 1568 } 1569 1570 #define clear_full_ptes clear_full_ptes 1571 static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr, 1572 pte_t *ptep, unsigned int nr, int full) 1573 { 1574 if (likely(nr == 1)) { 1575 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1576 __clear_full_ptes(mm, addr, ptep, nr, full); 1577 } else { 1578 contpte_clear_full_ptes(mm, addr, ptep, nr, full); 1579 } 1580 } 1581 1582 #define get_and_clear_full_ptes get_and_clear_full_ptes 1583 static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm, 1584 unsigned long addr, pte_t *ptep, 1585 unsigned int nr, int full) 1586 { 1587 pte_t pte; 1588 1589 if (likely(nr == 1)) { 1590 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1591 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1592 } else { 1593 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full); 1594 } 1595 1596 return pte; 1597 } 1598 1599 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1600 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 1601 unsigned long addr, pte_t *ptep) 1602 { 1603 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep)); 1604 return __ptep_get_and_clear(mm, addr, ptep); 1605 } 1606 1607 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1608 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 1609 unsigned long addr, pte_t *ptep) 1610 { 1611 pte_t orig_pte = __ptep_get(ptep); 1612 1613 if (likely(!pte_valid_cont(orig_pte))) 1614 return __ptep_test_and_clear_young(vma, addr, ptep); 1615 1616 return contpte_ptep_test_and_clear_young(vma, addr, ptep); 1617 } 1618 1619 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1620 static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 1621 unsigned long addr, pte_t *ptep) 1622 { 1623 pte_t orig_pte = __ptep_get(ptep); 1624 1625 if (likely(!pte_valid_cont(orig_pte))) 1626 return __ptep_clear_flush_young(vma, addr, ptep); 1627 1628 return contpte_ptep_clear_flush_young(vma, addr, ptep); 1629 } 1630 1631 #define wrprotect_ptes wrprotect_ptes 1632 static __always_inline void wrprotect_ptes(struct mm_struct *mm, 1633 unsigned long addr, pte_t *ptep, unsigned int nr) 1634 { 1635 if (likely(nr == 1)) { 1636 /* 1637 * Optimization: wrprotect_ptes() can only be called for present 1638 * ptes so we only need to check contig bit as condition for 1639 * unfold, and we can remove the contig bit from the pte we read 1640 * to avoid re-reading. This speeds up fork() which is sensitive 1641 * for order-0 folios. Equivalent to contpte_try_unfold(). 1642 */ 1643 pte_t orig_pte = __ptep_get(ptep); 1644 1645 if (unlikely(pte_cont(orig_pte))) { 1646 __contpte_try_unfold(mm, addr, ptep, orig_pte); 1647 orig_pte = pte_mknoncont(orig_pte); 1648 } 1649 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte); 1650 } else { 1651 contpte_wrprotect_ptes(mm, addr, ptep, nr); 1652 } 1653 } 1654 1655 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1656 static inline void ptep_set_wrprotect(struct mm_struct *mm, 1657 unsigned long addr, pte_t *ptep) 1658 { 1659 wrprotect_ptes(mm, addr, ptep, 1); 1660 } 1661 1662 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1663 static inline int ptep_set_access_flags(struct vm_area_struct *vma, 1664 unsigned long addr, pte_t *ptep, 1665 pte_t entry, int dirty) 1666 { 1667 pte_t orig_pte = __ptep_get(ptep); 1668 1669 entry = pte_mknoncont(entry); 1670 1671 if (likely(!pte_valid_cont(orig_pte))) 1672 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1673 1674 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty); 1675 } 1676 1677 #else /* CONFIG_ARM64_CONTPTE */ 1678 1679 #define ptep_get __ptep_get 1680 #define set_pte __set_pte 1681 #define set_ptes __set_ptes 1682 #define pte_clear __pte_clear 1683 #define clear_full_ptes __clear_full_ptes 1684 #define get_and_clear_full_ptes __get_and_clear_full_ptes 1685 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 1686 #define ptep_get_and_clear __ptep_get_and_clear 1687 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 1688 #define ptep_test_and_clear_young __ptep_test_and_clear_young 1689 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 1690 #define ptep_clear_flush_young __ptep_clear_flush_young 1691 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 1692 #define ptep_set_wrprotect __ptep_set_wrprotect 1693 #define wrprotect_ptes __wrprotect_ptes 1694 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 1695 #define ptep_set_access_flags __ptep_set_access_flags 1696 1697 #endif /* CONFIG_ARM64_CONTPTE */ 1698 1699 #endif /* !__ASSEMBLY__ */ 1700 1701 #endif /* __ASM_PGTABLE_H */ 1702