1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_PGTABLE_H 17 #define __ASM_PGTABLE_H 18 19 #include <asm/bug.h> 20 #include <asm/proc-fns.h> 21 22 #include <asm/memory.h> 23 #include <asm/pgtable-hwdef.h> 24 #include <asm/pgtable-prot.h> 25 26 /* 27 * VMALLOC range. 28 * 29 * VMALLOC_START: beginning of the kernel vmalloc space 30 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 31 * and fixed mappings 32 */ 33 #define VMALLOC_START (MODULES_END) 34 #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 35 36 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 37 38 #define FIRST_USER_ADDRESS 0UL 39 40 #ifndef __ASSEMBLY__ 41 42 #include <asm/fixmap.h> 43 #include <linux/mmdebug.h> 44 45 extern void __pte_error(const char *file, int line, unsigned long val); 46 extern void __pmd_error(const char *file, int line, unsigned long val); 47 extern void __pud_error(const char *file, int line, unsigned long val); 48 extern void __pgd_error(const char *file, int line, unsigned long val); 49 50 /* 51 * ZERO_PAGE is a global shared page that is always zero: used 52 * for zero-mapped memory areas etc.. 53 */ 54 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 55 #define ZERO_PAGE(vaddr) pfn_to_page(PHYS_PFN(__pa(empty_zero_page))) 56 57 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 58 59 #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 60 61 #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 62 63 #define pte_none(pte) (!pte_val(pte)) 64 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 65 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 66 67 /* 68 * The following only work if pte_present(). Undefined behaviour otherwise. 69 */ 70 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 71 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 72 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 73 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 74 #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) 75 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 76 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 77 78 #ifdef CONFIG_ARM64_HW_AFDBM 79 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 80 #else 81 #define pte_hw_dirty(pte) (0) 82 #endif 83 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 84 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 85 86 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 87 #define pte_valid_not_user(pte) \ 88 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 89 #define pte_valid_young(pte) \ 90 ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 91 92 /* 93 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 94 * so that we don't erroneously return false for pages that have been 95 * remapped as PROT_NONE but are yet to be flushed from the TLB. 96 */ 97 #define pte_accessible(mm, pte) \ 98 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 99 100 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 101 { 102 pte_val(pte) &= ~pgprot_val(prot); 103 return pte; 104 } 105 106 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 107 { 108 pte_val(pte) |= pgprot_val(prot); 109 return pte; 110 } 111 112 static inline pte_t pte_wrprotect(pte_t pte) 113 { 114 return clear_pte_bit(pte, __pgprot(PTE_WRITE)); 115 } 116 117 static inline pte_t pte_mkwrite(pte_t pte) 118 { 119 return set_pte_bit(pte, __pgprot(PTE_WRITE)); 120 } 121 122 static inline pte_t pte_mkclean(pte_t pte) 123 { 124 return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 125 } 126 127 static inline pte_t pte_mkdirty(pte_t pte) 128 { 129 return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 130 } 131 132 static inline pte_t pte_mkold(pte_t pte) 133 { 134 return clear_pte_bit(pte, __pgprot(PTE_AF)); 135 } 136 137 static inline pte_t pte_mkyoung(pte_t pte) 138 { 139 return set_pte_bit(pte, __pgprot(PTE_AF)); 140 } 141 142 static inline pte_t pte_mkspecial(pte_t pte) 143 { 144 return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 145 } 146 147 static inline pte_t pte_mkcont(pte_t pte) 148 { 149 pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 150 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 151 } 152 153 static inline pte_t pte_mknoncont(pte_t pte) 154 { 155 return clear_pte_bit(pte, __pgprot(PTE_CONT)); 156 } 157 158 static inline pmd_t pmd_mkcont(pmd_t pmd) 159 { 160 return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 161 } 162 163 static inline void set_pte(pte_t *ptep, pte_t pte) 164 { 165 *ptep = pte; 166 167 /* 168 * Only if the new pte is valid and kernel, otherwise TLB maintenance 169 * or update_mmu_cache() have the necessary barriers. 170 */ 171 if (pte_valid_not_user(pte)) { 172 dsb(ishst); 173 isb(); 174 } 175 } 176 177 struct mm_struct; 178 struct vm_area_struct; 179 180 extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 181 182 /* 183 * PTE bits configuration in the presence of hardware Dirty Bit Management 184 * (PTE_WRITE == PTE_DBM): 185 * 186 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 187 * 0 0 | 1 0 0 188 * 0 1 | 1 1 0 189 * 1 0 | 1 0 1 190 * 1 1 | 0 1 x 191 * 192 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 193 * the page fault mechanism. Checking the dirty status of a pte becomes: 194 * 195 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 196 */ 197 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 198 pte_t *ptep, pte_t pte) 199 { 200 if (pte_present(pte)) { 201 if (pte_sw_dirty(pte) && pte_write(pte)) 202 pte_val(pte) &= ~PTE_RDONLY; 203 else 204 pte_val(pte) |= PTE_RDONLY; 205 if (pte_user(pte) && pte_exec(pte) && !pte_special(pte)) 206 __sync_icache_dcache(pte, addr); 207 } 208 209 /* 210 * If the existing pte is valid, check for potential race with 211 * hardware updates of the pte (ptep_set_access_flags safely changes 212 * valid ptes without going through an invalid entry). 213 */ 214 if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 215 pte_valid(*ptep) && pte_valid(pte)) { 216 VM_WARN_ONCE(!pte_young(pte), 217 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 218 __func__, pte_val(*ptep), pte_val(pte)); 219 VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), 220 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 221 __func__, pte_val(*ptep), pte_val(pte)); 222 } 223 224 set_pte(ptep, pte); 225 } 226 227 #define __HAVE_ARCH_PTE_SAME 228 static inline int pte_same(pte_t pte_a, pte_t pte_b) 229 { 230 pteval_t lhs, rhs; 231 232 lhs = pte_val(pte_a); 233 rhs = pte_val(pte_b); 234 235 if (pte_present(pte_a)) 236 lhs &= ~PTE_RDONLY; 237 238 if (pte_present(pte_b)) 239 rhs &= ~PTE_RDONLY; 240 241 return (lhs == rhs); 242 } 243 244 /* 245 * Huge pte definitions. 246 */ 247 #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 248 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 249 250 /* 251 * Hugetlb definitions. 252 */ 253 #define HUGE_MAX_HSTATE 4 254 #define HPAGE_SHIFT PMD_SHIFT 255 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 256 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 257 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 258 259 #define __HAVE_ARCH_PTE_SPECIAL 260 261 static inline pte_t pud_pte(pud_t pud) 262 { 263 return __pte(pud_val(pud)); 264 } 265 266 static inline pmd_t pud_pmd(pud_t pud) 267 { 268 return __pmd(pud_val(pud)); 269 } 270 271 static inline pte_t pmd_pte(pmd_t pmd) 272 { 273 return __pte(pmd_val(pmd)); 274 } 275 276 static inline pmd_t pte_pmd(pte_t pte) 277 { 278 return __pmd(pte_val(pte)); 279 } 280 281 static inline pgprot_t mk_sect_prot(pgprot_t prot) 282 { 283 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 284 } 285 286 #ifdef CONFIG_NUMA_BALANCING 287 /* 288 * See the comment in include/asm-generic/pgtable.h 289 */ 290 static inline int pte_protnone(pte_t pte) 291 { 292 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 293 } 294 295 static inline int pmd_protnone(pmd_t pmd) 296 { 297 return pte_protnone(pmd_pte(pmd)); 298 } 299 #endif 300 301 /* 302 * THP definitions. 303 */ 304 305 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 306 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 307 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 308 309 #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 310 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 311 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 312 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 313 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 314 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 315 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 316 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 317 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 318 #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 319 320 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 321 322 #define __HAVE_ARCH_PMD_WRITE 323 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 324 325 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 326 327 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 328 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 329 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 330 331 #define pud_write(pud) pte_write(pud_pte(pud)) 332 #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 333 334 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 335 336 #define __pgprot_modify(prot,mask,bits) \ 337 __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 338 339 /* 340 * Mark the prot value as uncacheable and unbufferable. 341 */ 342 #define pgprot_noncached(prot) \ 343 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 344 #define pgprot_writecombine(prot) \ 345 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 346 #define pgprot_device(prot) \ 347 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 348 #define __HAVE_PHYS_MEM_ACCESS_PROT 349 struct file; 350 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 351 unsigned long size, pgprot_t vma_prot); 352 353 #define pmd_none(pmd) (!pmd_val(pmd)) 354 355 #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 356 357 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 358 PMD_TYPE_TABLE) 359 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 360 PMD_TYPE_SECT) 361 362 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 363 #define pud_sect(pud) (0) 364 #define pud_table(pud) (1) 365 #else 366 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 367 PUD_TYPE_SECT) 368 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 369 PUD_TYPE_TABLE) 370 #endif 371 372 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 373 { 374 *pmdp = pmd; 375 dsb(ishst); 376 isb(); 377 } 378 379 static inline void pmd_clear(pmd_t *pmdp) 380 { 381 set_pmd(pmdp, __pmd(0)); 382 } 383 384 static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 385 { 386 return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; 387 } 388 389 /* Find an entry in the third-level page table. */ 390 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 391 392 #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) 393 #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 394 395 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 396 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 397 #define pte_unmap(pte) do { } while (0) 398 #define pte_unmap_nested(pte) do { } while (0) 399 400 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 401 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 402 #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 403 404 #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 405 406 /* use ONLY for statically allocated translation tables */ 407 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 408 409 /* 410 * Conversion functions: convert a page and protection to a page entry, 411 * and a page entry and page directory to the page they refer to. 412 */ 413 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 414 415 #if CONFIG_PGTABLE_LEVELS > 2 416 417 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 418 419 #define pud_none(pud) (!pud_val(pud)) 420 #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 421 #define pud_present(pud) (pud_val(pud)) 422 423 static inline void set_pud(pud_t *pudp, pud_t pud) 424 { 425 *pudp = pud; 426 dsb(ishst); 427 isb(); 428 } 429 430 static inline void pud_clear(pud_t *pudp) 431 { 432 set_pud(pudp, __pud(0)); 433 } 434 435 static inline phys_addr_t pud_page_paddr(pud_t pud) 436 { 437 return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; 438 } 439 440 /* Find an entry in the second-level page table. */ 441 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 442 443 #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) 444 #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 445 446 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 447 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 448 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 449 450 #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 451 452 /* use ONLY for statically allocated translation tables */ 453 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 454 455 #else 456 457 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 458 459 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 460 #define pmd_set_fixmap(addr) NULL 461 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 462 #define pmd_clear_fixmap() 463 464 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 465 466 #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 467 468 #if CONFIG_PGTABLE_LEVELS > 3 469 470 #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 471 472 #define pgd_none(pgd) (!pgd_val(pgd)) 473 #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 474 #define pgd_present(pgd) (pgd_val(pgd)) 475 476 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 477 { 478 *pgdp = pgd; 479 dsb(ishst); 480 } 481 482 static inline void pgd_clear(pgd_t *pgdp) 483 { 484 set_pgd(pgdp, __pgd(0)); 485 } 486 487 static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 488 { 489 return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; 490 } 491 492 /* Find an entry in the frst-level page table. */ 493 #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 494 495 #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) 496 #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 497 498 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 499 #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 500 #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 501 502 #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 503 504 /* use ONLY for statically allocated translation tables */ 505 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 506 507 #else 508 509 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 510 511 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 512 #define pud_set_fixmap(addr) NULL 513 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 514 #define pud_clear_fixmap() 515 516 #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 517 518 #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 519 520 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 521 522 /* to find an entry in a page-table-directory */ 523 #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 524 525 #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 526 527 #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 528 529 /* to find an entry in a kernel page-table-directory */ 530 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 531 532 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 533 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 534 535 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 536 { 537 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 538 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 539 /* preserve the hardware dirty information */ 540 if (pte_hw_dirty(pte)) 541 pte = pte_mkdirty(pte); 542 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 543 return pte; 544 } 545 546 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 547 { 548 return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 549 } 550 551 #ifdef CONFIG_ARM64_HW_AFDBM 552 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 553 extern int ptep_set_access_flags(struct vm_area_struct *vma, 554 unsigned long address, pte_t *ptep, 555 pte_t entry, int dirty); 556 557 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 558 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 559 static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 560 unsigned long address, pmd_t *pmdp, 561 pmd_t entry, int dirty) 562 { 563 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 564 } 565 #endif 566 567 /* 568 * Atomic pte/pmd modifications. 569 */ 570 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 571 static inline int __ptep_test_and_clear_young(pte_t *ptep) 572 { 573 pteval_t pteval; 574 unsigned int tmp, res; 575 576 asm volatile("// __ptep_test_and_clear_young\n" 577 " prfm pstl1strm, %2\n" 578 "1: ldxr %0, %2\n" 579 " ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n" 580 " and %0, %0, %4 // clear PTE_AF\n" 581 " stxr %w1, %0, %2\n" 582 " cbnz %w1, 1b\n" 583 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res) 584 : "L" (~PTE_AF), "I" (ilog2(PTE_AF))); 585 586 return res; 587 } 588 589 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 590 unsigned long address, 591 pte_t *ptep) 592 { 593 return __ptep_test_and_clear_young(ptep); 594 } 595 596 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 597 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 598 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 599 unsigned long address, 600 pmd_t *pmdp) 601 { 602 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 603 } 604 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 605 606 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 607 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 608 unsigned long address, pte_t *ptep) 609 { 610 pteval_t old_pteval; 611 unsigned int tmp; 612 613 asm volatile("// ptep_get_and_clear\n" 614 " prfm pstl1strm, %2\n" 615 "1: ldxr %0, %2\n" 616 " stxr %w1, xzr, %2\n" 617 " cbnz %w1, 1b\n" 618 : "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))); 619 620 return __pte(old_pteval); 621 } 622 623 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 624 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 625 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 626 unsigned long address, pmd_t *pmdp) 627 { 628 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 629 } 630 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 631 632 /* 633 * ptep_set_wrprotect - mark read-only while trasferring potential hardware 634 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 635 */ 636 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 637 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 638 { 639 pteval_t pteval; 640 unsigned long tmp; 641 642 asm volatile("// ptep_set_wrprotect\n" 643 " prfm pstl1strm, %2\n" 644 "1: ldxr %0, %2\n" 645 " tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n" 646 " csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n" 647 " orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n" 648 " and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n" 649 " stxr %w1, %0, %2\n" 650 " cbnz %w1, 1b\n" 651 : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)) 652 : "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE) 653 : "cc"); 654 } 655 656 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 657 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 658 static inline void pmdp_set_wrprotect(struct mm_struct *mm, 659 unsigned long address, pmd_t *pmdp) 660 { 661 ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 662 } 663 #endif 664 #endif /* CONFIG_ARM64_HW_AFDBM */ 665 666 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 667 extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 668 669 /* 670 * Encode and decode a swap entry: 671 * bits 0-1: present (must be zero) 672 * bits 2-7: swap type 673 * bits 8-57: swap offset 674 * bit 58: PTE_PROT_NONE (must be zero) 675 */ 676 #define __SWP_TYPE_SHIFT 2 677 #define __SWP_TYPE_BITS 6 678 #define __SWP_OFFSET_BITS 50 679 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 680 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 681 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 682 683 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 684 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 685 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 686 687 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 688 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 689 690 /* 691 * Ensure that there are not more swap files than can be encoded in the kernel 692 * PTEs. 693 */ 694 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 695 696 extern int kern_addr_valid(unsigned long addr); 697 698 #include <asm-generic/pgtable.h> 699 700 void pgd_cache_init(void); 701 #define pgtable_cache_init pgd_cache_init 702 703 /* 704 * On AArch64, the cache coherency is handled via the set_pte_at() function. 705 */ 706 static inline void update_mmu_cache(struct vm_area_struct *vma, 707 unsigned long addr, pte_t *ptep) 708 { 709 /* 710 * We don't do anything here, so there's a very small chance of 711 * us retaking a user fault which we just fixed up. The alternative 712 * is doing a dsb(ishst), but that penalises the fastpath. 713 */ 714 } 715 716 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 717 718 #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 719 #define kc_offset_to_vaddr(o) ((o) | VA_START) 720 721 #endif /* !__ASSEMBLY__ */ 722 723 #endif /* __ASM_PGTABLE_H */ 724