1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 223e1907d5SArd Biesheuvel * and fixed mappings 234f04d8f0SCatalin Marinas */ 24f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2514c127c9SSteve Capper #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 264f04d8f0SCatalin Marinas 277bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 287bc1a0f9SArd Biesheuvel 29d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 304f04d8f0SCatalin Marinas 314f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 322f4b829cSCatalin Marinas 333bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 34961faac1SMark Rutland #include <asm/fixmap.h> 352f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3686c9e812SWill Deacon #include <linux/mm_types.h> 3786c9e812SWill Deacon #include <linux/sched.h> 382f4b829cSCatalin Marinas 39a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 40a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 41a7ac1cfaSZhenyu Ye 42a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 43a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 44a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 45a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 46a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 47a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 48a7ac1cfaSZhenyu Ye 494f04d8f0SCatalin Marinas /* 506a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 516a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 526a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 536a1bdb17SWill Deacon * does not need to perform additional invalidation. 546a1bdb17SWill Deacon */ 556a1bdb17SWill Deacon #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 566a1bdb17SWill Deacon 576a1bdb17SWill Deacon /* 584f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 594f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 604f04d8f0SCatalin Marinas */ 615227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 622077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 634f04d8f0SCatalin Marinas 642cf660ebSGavin Shan #define pte_ERROR(e) \ 652cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 667078db46SCatalin Marinas 6775387b92SKristina Martsenko /* 6875387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6975387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 7075387b92SKristina Martsenko */ 7175387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 7275387b92SKristina Martsenko #define __pte_to_phys(pte) \ 7375387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 7475387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 7575387b92SKristina Martsenko #else 7675387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 7775387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 7875387b92SKristina Martsenko #endif 794f04d8f0SCatalin Marinas 8075387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 8175387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 8275387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 834f04d8f0SCatalin Marinas 844f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 854f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 864f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 877078db46SCatalin Marinas 884f04d8f0SCatalin Marinas /* 894f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 904f04d8f0SCatalin Marinas */ 9184fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 9284fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 9384fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 9484fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 95ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 9693ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 9773b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 9834bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 9934bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 1004f04d8f0SCatalin Marinas 101d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 102d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 103d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 104d27cfa1fSArd Biesheuvel }) 105d27cfa1fSArd Biesheuvel 106d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 107d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 108d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 109d27cfa1fSArd Biesheuvel }) 110d27cfa1fSArd Biesheuvel 111b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1122f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1132f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1142f4b829cSCatalin Marinas 115766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 116ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 11724cecc37SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 1186218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1196218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 12076c714beSWill Deacon 12176c714beSWill Deacon /* 12276c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 12376c714beSWill Deacon * so that we don't erroneously return false for pages that have been 12476c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 12507509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 12607509e10SWill Deacon * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 12707509e10SWill Deacon * TLB. 12876c714beSWill Deacon */ 12976c714beSWill Deacon #define pte_accessible(mm, pte) \ 13007509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1314f04d8f0SCatalin Marinas 1326218f96cSCatalin Marinas /* 1336218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 13424cecc37SCatalin Marinas * write permission check). PROT_NONE mappings do not have the PTE_VALID bit 13524cecc37SCatalin Marinas * set. 1366218f96cSCatalin Marinas */ 1376218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1386218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1396218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1406218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1416218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1426218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1436218f96cSCatalin Marinas 144b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 145b6d4f280SLaura Abbott { 146b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 147b6d4f280SLaura Abbott return pte; 148b6d4f280SLaura Abbott } 149b6d4f280SLaura Abbott 150b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 151b6d4f280SLaura Abbott { 152b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 153b6d4f280SLaura Abbott return pte; 154b6d4f280SLaura Abbott } 155b6d4f280SLaura Abbott 156b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 157b65399f6SAnshuman Khandual { 158b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 159b65399f6SAnshuman Khandual return pmd; 160b65399f6SAnshuman Khandual } 161b65399f6SAnshuman Khandual 162b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 163b65399f6SAnshuman Khandual { 164b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 165b65399f6SAnshuman Khandual return pmd; 166b65399f6SAnshuman Khandual } 167b65399f6SAnshuman Khandual 16844b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 16944b6dfc5SSteve Capper { 17073e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 17173e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 17273e86cb0SCatalin Marinas return pte; 17344b6dfc5SSteve Capper } 17444b6dfc5SSteve Capper 17544b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 17644b6dfc5SSteve Capper { 1778781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1788781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1798781bcbcSSteve Capper 1808781bcbcSSteve Capper return pte; 18144b6dfc5SSteve Capper } 18244b6dfc5SSteve Capper 18344b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 18444b6dfc5SSteve Capper { 1858781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1868781bcbcSSteve Capper 1878781bcbcSSteve Capper if (pte_write(pte)) 1888781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1898781bcbcSSteve Capper 1908781bcbcSSteve Capper return pte; 19144b6dfc5SSteve Capper } 19244b6dfc5SSteve Capper 193*ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 194*ff1712f9SWill Deacon { 195*ff1712f9SWill Deacon /* 196*ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 197*ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 198*ff1712f9SWill Deacon */ 199*ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 200*ff1712f9SWill Deacon pte = pte_mkdirty(pte); 201*ff1712f9SWill Deacon 202*ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 203*ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 204*ff1712f9SWill Deacon return pte; 205*ff1712f9SWill Deacon } 206*ff1712f9SWill Deacon 20744b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 20844b6dfc5SSteve Capper { 209b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 21044b6dfc5SSteve Capper } 21144b6dfc5SSteve Capper 21244b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 21344b6dfc5SSteve Capper { 214b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 21544b6dfc5SSteve Capper } 21644b6dfc5SSteve Capper 21744b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 21844b6dfc5SSteve Capper { 219b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 22044b6dfc5SSteve Capper } 2214f04d8f0SCatalin Marinas 22293ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 22393ef666aSJeremy Linton { 22466b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 22566b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 22693ef666aSJeremy Linton } 22793ef666aSJeremy Linton 22893ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 22993ef666aSJeremy Linton { 23093ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 23193ef666aSJeremy Linton } 23293ef666aSJeremy Linton 2335ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2345ebe3a44SJames Morse { 2355ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2365ebe3a44SJames Morse } 2375ebe3a44SJames Morse 23866b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 23966b3923aSDavid Woods { 24066b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 24166b3923aSDavid Woods } 24266b3923aSDavid Woods 24373b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 24473b20c84SRobin Murphy { 24530e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 24673b20c84SRobin Murphy } 24773b20c84SRobin Murphy 2484f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2494f04d8f0SCatalin Marinas { 25020a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2517f0b1bf0SCatalin Marinas 2527f0b1bf0SCatalin Marinas /* 2537f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2547f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2557f0b1bf0SCatalin Marinas */ 256d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2577f0b1bf0SCatalin Marinas dsb(ishst); 258d0b7a302SWill Deacon isb(); 259d0b7a302SWill Deacon } 2604f04d8f0SCatalin Marinas } 2614f04d8f0SCatalin Marinas 262907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2634f04d8f0SCatalin Marinas 2642f4b829cSCatalin Marinas /* 2652f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2662f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2672f4b829cSCatalin Marinas * 2682f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2692f4b829cSCatalin Marinas * 0 0 | 1 0 0 2702f4b829cSCatalin Marinas * 0 1 | 1 1 0 2712f4b829cSCatalin Marinas * 1 0 | 1 0 1 2722f4b829cSCatalin Marinas * 1 1 | 0 1 x 2732f4b829cSCatalin Marinas * 2742f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2752f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2762f4b829cSCatalin Marinas * 277b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2782f4b829cSCatalin Marinas */ 2799b604722SMark Rutland 2809b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2819b604722SMark Rutland pte_t pte) 2824f04d8f0SCatalin Marinas { 28320a004e7SWill Deacon pte_t old_pte; 28420a004e7SWill Deacon 2859b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2869b604722SMark Rutland return; 2879b604722SMark Rutland 2889b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2899b604722SMark Rutland 2909b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2919b604722SMark Rutland return; 2929b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2939b604722SMark Rutland return; 29402522463SWill Deacon 2952f4b829cSCatalin Marinas /* 2969b604722SMark Rutland * Check for potential race with hardware updates of the pte 2979b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2989b604722SMark Rutland * through an invalid entry). 2992f4b829cSCatalin Marinas */ 30082d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 30182d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 30220a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 30320a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 30482d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 30520a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 3062f4b829cSCatalin Marinas } 3072f4b829cSCatalin Marinas 3089b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 3099b604722SMark Rutland pte_t *ptep, pte_t pte) 3109b604722SMark Rutland { 3119b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3129b604722SMark Rutland __sync_icache_dcache(pte); 3139b604722SMark Rutland 31434bfeea4SCatalin Marinas if (system_supports_mte() && 31534bfeea4SCatalin Marinas pte_present(pte) && pte_tagged(pte) && !pte_special(pte)) 31634bfeea4SCatalin Marinas mte_sync_tags(ptep, pte); 31734bfeea4SCatalin Marinas 3189b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 3199b604722SMark Rutland 3204f04d8f0SCatalin Marinas set_pte(ptep, pte); 3214f04d8f0SCatalin Marinas } 3224f04d8f0SCatalin Marinas 3234f04d8f0SCatalin Marinas /* 3244f04d8f0SCatalin Marinas * Huge pte definitions. 3254f04d8f0SCatalin Marinas */ 326084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 327084bd298SSteve Capper 328084bd298SSteve Capper /* 329084bd298SSteve Capper * Hugetlb definitions. 330084bd298SSteve Capper */ 33166b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 332084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 333084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 334084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 335084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3364f04d8f0SCatalin Marinas 33775387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 33875387b92SKristina Martsenko { 33975387b92SKristina Martsenko return __pte(pgd_val(pgd)); 34075387b92SKristina Martsenko } 34175387b92SKristina Martsenko 342e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 343e9f63768SMike Rapoport { 344e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 345e9f63768SMike Rapoport } 346e9f63768SMike Rapoport 34729e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 34829e56940SSteve Capper { 34929e56940SSteve Capper return __pte(pud_val(pud)); 35029e56940SSteve Capper } 35129e56940SSteve Capper 352eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 353eb3f0624SPunit Agrawal { 354eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 355eb3f0624SPunit Agrawal } 356eb3f0624SPunit Agrawal 35729e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 35829e56940SSteve Capper { 35929e56940SSteve Capper return __pmd(pud_val(pud)); 36029e56940SSteve Capper } 36129e56940SSteve Capper 3629c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3639c7e535fSSteve Capper { 3649c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3659c7e535fSSteve Capper } 366af074848SSteve Capper 3679c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3689c7e535fSSteve Capper { 3699c7e535fSSteve Capper return __pmd(pte_val(pte)); 3709c7e535fSSteve Capper } 371af074848SSteve Capper 372f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3738ce837ceSArd Biesheuvel { 374f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 375f7f0097aSAnshuman Khandual } 376f7f0097aSAnshuman Khandual 377f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 378f7f0097aSAnshuman Khandual { 379f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3808ce837ceSArd Biesheuvel } 3818ce837ceSArd Biesheuvel 38256166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 38356166230SGanapatrao Kulkarni /* 384ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 38556166230SGanapatrao Kulkarni */ 38656166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 38756166230SGanapatrao Kulkarni { 38856166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 38956166230SGanapatrao Kulkarni } 39056166230SGanapatrao Kulkarni 39156166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 39256166230SGanapatrao Kulkarni { 39356166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 39456166230SGanapatrao Kulkarni } 39556166230SGanapatrao Kulkarni #endif 39656166230SGanapatrao Kulkarni 397b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 398b65399f6SAnshuman Khandual 399b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 400b65399f6SAnshuman Khandual { 401b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 402b65399f6SAnshuman Khandual } 403b65399f6SAnshuman Khandual 404af074848SSteve Capper /* 405af074848SSteve Capper * THP definitions. 406af074848SSteve Capper */ 407af074848SSteve Capper 408af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 409b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 410b65399f6SAnshuman Khandual { 411b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 412b65399f6SAnshuman Khandual } 41329e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 414af074848SSteve Capper 415c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 4169c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 4170795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 4189c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 4199c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 4209c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 42105ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 4229c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 4239c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 424b65399f6SAnshuman Khandual 425b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 426b65399f6SAnshuman Khandual { 427b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 428b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 429b65399f6SAnshuman Khandual 430b65399f6SAnshuman Khandual return pmd; 431b65399f6SAnshuman Khandual } 432af074848SSteve Capper 4330dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 4340dbd3b18SSuzuki K Poulose 4359c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 436af074848SSteve Capper 437af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 438af074848SSteve Capper 43973b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44073b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 44173b20c84SRobin Murphy #endif 44230e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 44330e23538SJia He { 44430e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 44530e23538SJia He } 44673b20c84SRobin Murphy 44775387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 44875387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 44975387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 45075387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 451af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 452af074848SSteve Capper 45335a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 454eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 45529e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 45675387b92SKristina Martsenko 457b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 458b8e0ba7cSPunit Agrawal 45975387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 46075387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 46175387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 46275387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 463af074848SSteve Capper 464ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 465af074848SSteve Capper 466e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 467e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 468e9f63768SMike Rapoport 46975387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 47075387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 47175387b92SKristina Martsenko 472a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 473a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 474a501e324SCatalin Marinas 475cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 476034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 477cca98e9fSChristoph Hellwig 478af074848SSteve Capper /* 4794f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4804f04d8f0SCatalin Marinas */ 4814f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 482de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4834f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 484de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 485d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 486d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4873e4e1d3fSChristoph Hellwig /* 4883e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 4893e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 4903e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 4913e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 4923e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 4933e4e1d3fSChristoph Hellwig * endpoint. 4943e4e1d3fSChristoph Hellwig */ 495419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 496419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 497419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 498419e2f18SChristoph Hellwig 4994f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 5004f04d8f0SCatalin Marinas struct file; 5014f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 5024f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 5034f04d8f0SCatalin Marinas 5044f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 5054f04d8f0SCatalin Marinas 506ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 5074f04d8f0SCatalin Marinas 50836311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 50936311607SMarc Zyngier PMD_TYPE_TABLE) 51036311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 51136311607SMarc Zyngier PMD_TYPE_SECT) 5128aa82df3SSteven Price #define pmd_leaf(pmd) pmd_sect(pmd) 51336311607SMarc Zyngier 514cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 5157d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 5167d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 517206a2a73SSteve Capper #else 518206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 519206a2a73SSteve Capper PUD_TYPE_SECT) 520523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 521523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 522206a2a73SSteve Capper #endif 52336311607SMarc Zyngier 5242330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 5252330b7caSJun Yao extern pgd_t init_pg_end[]; 5262330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 5272330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 5289d2d75edSGavin Shan extern pgd_t idmap_pg_end[]; 5292330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 5302330b7caSJun Yao 5312330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 5322330b7caSJun Yao 5332330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 5342330b7caSJun Yao { 5352330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 5362330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 5372330b7caSJun Yao } 5382330b7caSJun Yao 5394f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 5404f04d8f0SCatalin Marinas { 541e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 542e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 5432330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 5442330b7caSJun Yao return; 5452330b7caSJun Yao } 546e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 5472330b7caSJun Yao 54820a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 5490795edafSWill Deacon 550d0b7a302SWill Deacon if (pmd_valid(pmd)) { 55198f7685eSWill Deacon dsb(ishst); 552d0b7a302SWill Deacon isb(); 553d0b7a302SWill Deacon } 5544f04d8f0SCatalin Marinas } 5554f04d8f0SCatalin Marinas 5564f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 5574f04d8f0SCatalin Marinas { 5584f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 5594f04d8f0SCatalin Marinas } 5604f04d8f0SCatalin Marinas 561dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 5624f04d8f0SCatalin Marinas { 56375387b92SKristina Martsenko return __pmd_to_phys(pmd); 5644f04d8f0SCatalin Marinas } 5654f04d8f0SCatalin Marinas 566974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 567974b9b2cSMike Rapoport { 568974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 569974b9b2cSMike Rapoport } 57074dd022fSQian Cai 571053520f7SMark Rutland /* Find an entry in the third-level page table. */ 572f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 573053520f7SMark Rutland 574961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 575961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 576961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 577961faac1SMark Rutland 57868ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 5794f04d8f0SCatalin Marinas 5806533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5816533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 5826533945aSArd Biesheuvel 5834f04d8f0SCatalin Marinas /* 5844f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 5854f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 5864f04d8f0SCatalin Marinas */ 5874f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 5884f04d8f0SCatalin Marinas 5899f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 5904f04d8f0SCatalin Marinas 5912cf660ebSGavin Shan #define pmd_ERROR(e) \ 5922cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 5937078db46SCatalin Marinas 5944f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 595ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 596f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5978aa82df3SSteven Price #define pud_leaf(pud) pud_sect(pud) 5980795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5994f04d8f0SCatalin Marinas 6004f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 6014f04d8f0SCatalin Marinas { 602e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 603e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 6042330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 6052330b7caSJun Yao return; 6062330b7caSJun Yao } 607e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 6082330b7caSJun Yao 60920a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 6100795edafSWill Deacon 611d0b7a302SWill Deacon if (pud_valid(pud)) { 61298f7685eSWill Deacon dsb(ishst); 613d0b7a302SWill Deacon isb(); 614d0b7a302SWill Deacon } 6154f04d8f0SCatalin Marinas } 6164f04d8f0SCatalin Marinas 6174f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 6184f04d8f0SCatalin Marinas { 6194f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 6204f04d8f0SCatalin Marinas } 6214f04d8f0SCatalin Marinas 622dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 6234f04d8f0SCatalin Marinas { 62475387b92SKristina Martsenko return __pud_to_phys(pud); 6254f04d8f0SCatalin Marinas } 6264f04d8f0SCatalin Marinas 627974b9b2cSMike Rapoport static inline unsigned long pud_page_vaddr(pud_t pud) 628974b9b2cSMike Rapoport { 629974b9b2cSMike Rapoport return (unsigned long)__va(pud_page_paddr(pud)); 630974b9b2cSMike Rapoport } 6317078db46SCatalin Marinas 632974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 63320a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 6347078db46SCatalin Marinas 635961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 636961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 637961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 6384f04d8f0SCatalin Marinas 63968ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 64029e56940SSteve Capper 6416533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6426533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 6436533945aSArd Biesheuvel 644dca56dcaSMark Rutland #else 645dca56dcaSMark Rutland 646dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 647dca56dcaSMark Rutland 648961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 649961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 650961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 651961faac1SMark Rutland #define pmd_clear_fixmap() 652961faac1SMark Rutland 6536533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 6546533945aSArd Biesheuvel 6559f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 6564f04d8f0SCatalin Marinas 6579f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 658c79b954bSJungseok Lee 6592cf660ebSGavin Shan #define pud_ERROR(e) \ 6602cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 6617078db46SCatalin Marinas 662e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 663e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 664e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 665c79b954bSJungseok Lee 666e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 667c79b954bSJungseok Lee { 668e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 669e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 6702330b7caSJun Yao return; 6712330b7caSJun Yao } 6722330b7caSJun Yao 673e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 674c79b954bSJungseok Lee dsb(ishst); 675eb6a4dccSWill Deacon isb(); 676c79b954bSJungseok Lee } 677c79b954bSJungseok Lee 678e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 679c79b954bSJungseok Lee { 680e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 681c79b954bSJungseok Lee } 682c79b954bSJungseok Lee 683e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 684c79b954bSJungseok Lee { 685e9f63768SMike Rapoport return __p4d_to_phys(p4d); 686c79b954bSJungseok Lee } 687c79b954bSJungseok Lee 688974b9b2cSMike Rapoport static inline unsigned long p4d_page_vaddr(p4d_t p4d) 689974b9b2cSMike Rapoport { 690974b9b2cSMike Rapoport return (unsigned long)__va(p4d_page_paddr(p4d)); 691974b9b2cSMike Rapoport } 6927078db46SCatalin Marinas 693974b9b2cSMike Rapoport /* Find an entry in the frst-level page table. */ 694e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 6957078db46SCatalin Marinas 696961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 697e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 698961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 699c79b954bSJungseok Lee 700e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 7015d96e0cbSJungseok Lee 7026533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7036533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 7046533945aSArd Biesheuvel 705dca56dcaSMark Rutland #else 706dca56dcaSMark Rutland 707e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 708dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 709dca56dcaSMark Rutland 710961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 711961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 712961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 713961faac1SMark Rutland #define pud_clear_fixmap() 714961faac1SMark Rutland 7156533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 7166533945aSArd Biesheuvel 7179f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 718c79b954bSJungseok Lee 7192cf660ebSGavin Shan #define pgd_ERROR(e) \ 7202cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 7217078db46SCatalin Marinas 722961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 723961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 724961faac1SMark Rutland 7254f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 7264f04d8f0SCatalin Marinas { 7279f341931SCatalin Marinas /* 7289f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 7299f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 7309f341931SCatalin Marinas */ 731a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 7329f341931SCatalin Marinas PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 7339f341931SCatalin Marinas PTE_ATTRINDX_MASK; 7342f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 7352f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 73662d96c71SCatalin Marinas pte = pte_mkdirty(pte); 7374f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 7384f04d8f0SCatalin Marinas return pte; 7394f04d8f0SCatalin Marinas } 7404f04d8f0SCatalin Marinas 7419c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 7429c7e535fSSteve Capper { 7439c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 7449c7e535fSSteve Capper } 7459c7e535fSSteve Capper 74666dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 74766dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 74866dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 74966dbd6e6SCatalin Marinas pte_t entry, int dirty); 75066dbd6e6SCatalin Marinas 751282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 752282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 753282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 754282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 755282aa705SCatalin Marinas pmd_t entry, int dirty) 756282aa705SCatalin Marinas { 757282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 758282aa705SCatalin Marinas } 75973b20c84SRobin Murphy 76073b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 76173b20c84SRobin Murphy { 76273b20c84SRobin Murphy return 0; 76373b20c84SRobin Murphy } 76473b20c84SRobin Murphy 76573b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 76673b20c84SRobin Murphy { 76773b20c84SRobin Murphy return 0; 76873b20c84SRobin Murphy } 769282aa705SCatalin Marinas #endif 770282aa705SCatalin Marinas 7712f4b829cSCatalin Marinas /* 7722f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7732f4b829cSCatalin Marinas */ 7742f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 77506485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 7762f4b829cSCatalin Marinas { 7773bbf7157SCatalin Marinas pte_t old_pte, pte; 7782f4b829cSCatalin Marinas 7793bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7803bbf7157SCatalin Marinas do { 7813bbf7157SCatalin Marinas old_pte = pte; 7823bbf7157SCatalin Marinas pte = pte_mkold(pte); 7833bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7843bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7853bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7862f4b829cSCatalin Marinas 7873bbf7157SCatalin Marinas return pte_young(pte); 7882f4b829cSCatalin Marinas } 7892f4b829cSCatalin Marinas 79006485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 79106485053SCatalin Marinas unsigned long address, 79206485053SCatalin Marinas pte_t *ptep) 79306485053SCatalin Marinas { 79406485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 79506485053SCatalin Marinas } 79606485053SCatalin Marinas 7973403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 7983403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 7993403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 8003403e56bSAlex Van Brunt { 8013403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 8023403e56bSAlex Van Brunt 8033403e56bSAlex Van Brunt if (young) { 8043403e56bSAlex Van Brunt /* 8053403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 8063403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 8073403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 8083403e56bSAlex Van Brunt * window for such an event is bounded by the next 8093403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 8103403e56bSAlex Van Brunt * invalidation. 8113403e56bSAlex Van Brunt */ 8123403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 8133403e56bSAlex Van Brunt } 8143403e56bSAlex Van Brunt 8153403e56bSAlex Van Brunt return young; 8163403e56bSAlex Van Brunt } 8173403e56bSAlex Van Brunt 8182f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8192f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 8202f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 8212f4b829cSCatalin Marinas unsigned long address, 8222f4b829cSCatalin Marinas pmd_t *pmdp) 8232f4b829cSCatalin Marinas { 8242f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 8252f4b829cSCatalin Marinas } 8262f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8272f4b829cSCatalin Marinas 8282f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 8292f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 8302f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 8312f4b829cSCatalin Marinas { 8323bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 8332f4b829cSCatalin Marinas } 8342f4b829cSCatalin Marinas 8352f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 836911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 837911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 8382f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8392f4b829cSCatalin Marinas { 8402f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 8412f4b829cSCatalin Marinas } 8422f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8432f4b829cSCatalin Marinas 8442f4b829cSCatalin Marinas /* 8458781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 8468781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 8472f4b829cSCatalin Marinas */ 8482f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 8492f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 8502f4b829cSCatalin Marinas { 8513bbf7157SCatalin Marinas pte_t old_pte, pte; 8522f4b829cSCatalin Marinas 8533bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 8543bbf7157SCatalin Marinas do { 8553bbf7157SCatalin Marinas old_pte = pte; 8563bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 8573bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8583bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8593bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8602f4b829cSCatalin Marinas } 8612f4b829cSCatalin Marinas 8622f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8632f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8642f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8652f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8662f4b829cSCatalin Marinas { 8672f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8682f4b829cSCatalin Marinas } 8691d78a62cSCatalin Marinas 8701d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8711d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8721d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8731d78a62cSCatalin Marinas { 8741d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 8751d78a62cSCatalin Marinas } 8762f4b829cSCatalin Marinas #endif 8772f4b829cSCatalin Marinas 8784f04d8f0SCatalin Marinas /* 8794f04d8f0SCatalin Marinas * Encode and decode a swap entry: 8803676f9efSCatalin Marinas * bits 0-1: present (must be zero) 8819b3e661eSKirill A. Shutemov * bits 2-7: swap type 8829b3e661eSKirill A. Shutemov * bits 8-57: swap offset 883fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 8844f04d8f0SCatalin Marinas */ 8859b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 8864f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 8879b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 8884f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 8894f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 8903676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 8914f04d8f0SCatalin Marinas 8924f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 8933676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 8944f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 8954f04d8f0SCatalin Marinas 8964f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 8974f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 8984f04d8f0SCatalin Marinas 89953fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 90053fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 90153fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 90253fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 90353fa117bSAnshuman Khandual 9044f04d8f0SCatalin Marinas /* 9054f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 906aad9061bSGeert Uytterhoeven * PTEs. 9074f04d8f0SCatalin Marinas */ 9084f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 9094f04d8f0SCatalin Marinas 9104f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 9114f04d8f0SCatalin Marinas 91236943abaSSteven Price #ifdef CONFIG_ARM64_MTE 91336943abaSSteven Price 91436943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 91536943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 91636943abaSSteven Price { 91736943abaSSteven Price if (system_supports_mte()) 91836943abaSSteven Price return mte_save_tags(page); 91936943abaSSteven Price return 0; 92036943abaSSteven Price } 92136943abaSSteven Price 92236943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 92336943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 92436943abaSSteven Price { 92536943abaSSteven Price if (system_supports_mte()) 92636943abaSSteven Price mte_invalidate_tags(type, offset); 92736943abaSSteven Price } 92836943abaSSteven Price 92936943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 93036943abaSSteven Price { 93136943abaSSteven Price if (system_supports_mte()) 93236943abaSSteven Price mte_invalidate_tags_area(type); 93336943abaSSteven Price } 93436943abaSSteven Price 93536943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 93636943abaSSteven Price static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 93736943abaSSteven Price { 93836943abaSSteven Price if (system_supports_mte() && mte_restore_tags(entry, page)) 93936943abaSSteven Price set_bit(PG_mte_tagged, &page->flags); 94036943abaSSteven Price } 94136943abaSSteven Price 94236943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 94336943abaSSteven Price 944cba3574fSWill Deacon /* 945cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 946cba3574fSWill Deacon */ 947cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 948cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 949cba3574fSWill Deacon { 950cba3574fSWill Deacon /* 951120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 952120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 953120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 954cba3574fSWill Deacon */ 955cba3574fSWill Deacon } 956cba3574fSWill Deacon 957cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 958cba3574fSWill Deacon 959529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 960529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 961529c4b05SKristina Martsenko #else 962529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 963529c4b05SKristina Martsenko #endif 964529c4b05SKristina Martsenko 9656af31226SJia He /* 9666af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 9676af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 9686af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 9696af31226SJia He * hardware-managed access flag on arm64. 9706af31226SJia He */ 9716af31226SJia He static inline bool arch_faults_on_old_pte(void) 9726af31226SJia He { 9736af31226SJia He WARN_ON(preemptible()); 9746af31226SJia He 9756af31226SJia He return !cpu_has_hw_af(); 9766af31226SJia He } 9776af31226SJia He #define arch_faults_on_old_pte arch_faults_on_old_pte 9786af31226SJia He 9794f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 9804f04d8f0SCatalin Marinas 9814f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 982