1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 223e1907d5SArd Biesheuvel * and fixed mappings 234f04d8f0SCatalin Marinas */ 24f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 259ad7c6d5SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START - SZ_256M) 264f04d8f0SCatalin Marinas 277bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 287bc1a0f9SArd Biesheuvel 294f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 302f4b829cSCatalin Marinas 313bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 32961faac1SMark Rutland #include <asm/fixmap.h> 332f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3486c9e812SWill Deacon #include <linux/mm_types.h> 3586c9e812SWill Deacon #include <linux/sched.h> 362f4b829cSCatalin Marinas 37a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 38a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 39a7ac1cfaSZhenyu Ye 40a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 41a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 42a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 43a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 44a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 45a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 46a7ac1cfaSZhenyu Ye 474f04d8f0SCatalin Marinas /* 486a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 496a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 506a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 516a1bdb17SWill Deacon * does not need to perform additional invalidation. 526a1bdb17SWill Deacon */ 536a1bdb17SWill Deacon #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0) 546a1bdb17SWill Deacon 556a1bdb17SWill Deacon /* 564f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 574f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 584f04d8f0SCatalin Marinas */ 595227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 602077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 614f04d8f0SCatalin Marinas 622cf660ebSGavin Shan #define pte_ERROR(e) \ 632cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 647078db46SCatalin Marinas 6575387b92SKristina Martsenko /* 6675387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6775387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 6875387b92SKristina Martsenko */ 6975387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 7075387b92SKristina Martsenko #define __pte_to_phys(pte) \ 7175387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 7275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 7375387b92SKristina Martsenko #else 7475387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 7575387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 7675387b92SKristina Martsenko #endif 774f04d8f0SCatalin Marinas 7875387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 7975387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 8075387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 814f04d8f0SCatalin Marinas 824f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 834f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 844f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 857078db46SCatalin Marinas 864f04d8f0SCatalin Marinas /* 874f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 884f04d8f0SCatalin Marinas */ 8984fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 9084fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 9184fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 9284fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 93ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 9493ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 9573b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 9634bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 9734bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 984f04d8f0SCatalin Marinas 99d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 100d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 101d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 102d27cfa1fSArd Biesheuvel }) 103d27cfa1fSArd Biesheuvel 104d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 105d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 106d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 107d27cfa1fSArd Biesheuvel }) 108d27cfa1fSArd Biesheuvel 109b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1102f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1112f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1122f4b829cSCatalin Marinas 113766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 11418107f8aSVladimir Murzin /* 11518107f8aSVladimir Murzin * Execute-only user mappings do not have the PTE_USER bit set. All valid 11618107f8aSVladimir Murzin * kernel mappings have the PTE_UXN bit set. 11718107f8aSVladimir Murzin */ 118ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 11918107f8aSVladimir Murzin ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 12076c714beSWill Deacon /* 12176c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 12276c714beSWill Deacon * so that we don't erroneously return false for pages that have been 12376c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 12407509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 12507509e10SWill Deacon * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 12607509e10SWill Deacon * TLB. 12776c714beSWill Deacon */ 12876c714beSWill Deacon #define pte_accessible(mm, pte) \ 12907509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1304f04d8f0SCatalin Marinas 1316218f96cSCatalin Marinas /* 13218107f8aSVladimir Murzin * p??_access_permitted() is true for valid user mappings (PTE_USER 13318107f8aSVladimir Murzin * bit set, subject to the write permission check). For execute-only 13418107f8aSVladimir Murzin * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 13518107f8aSVladimir Murzin * not set) must return false. PROT_NONE mappings do not have the 13618107f8aSVladimir Murzin * PTE_VALID bit set. 1376218f96cSCatalin Marinas */ 1386218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 13918107f8aSVladimir Murzin (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 1406218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1416218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1426218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1436218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1446218f96cSCatalin Marinas 145b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 146b6d4f280SLaura Abbott { 147b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 148b6d4f280SLaura Abbott return pte; 149b6d4f280SLaura Abbott } 150b6d4f280SLaura Abbott 151b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 152b6d4f280SLaura Abbott { 153b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 154b6d4f280SLaura Abbott return pte; 155b6d4f280SLaura Abbott } 156b6d4f280SLaura Abbott 157b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 158b65399f6SAnshuman Khandual { 159b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 160b65399f6SAnshuman Khandual return pmd; 161b65399f6SAnshuman Khandual } 162b65399f6SAnshuman Khandual 163b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 164b65399f6SAnshuman Khandual { 165b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 166b65399f6SAnshuman Khandual return pmd; 167b65399f6SAnshuman Khandual } 168b65399f6SAnshuman Khandual 16944b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 17044b6dfc5SSteve Capper { 17173e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 17273e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 17373e86cb0SCatalin Marinas return pte; 17444b6dfc5SSteve Capper } 17544b6dfc5SSteve Capper 17644b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 17744b6dfc5SSteve Capper { 1788781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1798781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1808781bcbcSSteve Capper 1818781bcbcSSteve Capper return pte; 18244b6dfc5SSteve Capper } 18344b6dfc5SSteve Capper 18444b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 18544b6dfc5SSteve Capper { 1868781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1878781bcbcSSteve Capper 1888781bcbcSSteve Capper if (pte_write(pte)) 1898781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1908781bcbcSSteve Capper 1918781bcbcSSteve Capper return pte; 19244b6dfc5SSteve Capper } 19344b6dfc5SSteve Capper 194ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 195ff1712f9SWill Deacon { 196ff1712f9SWill Deacon /* 197ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 198ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 199ff1712f9SWill Deacon */ 200ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 201ff1712f9SWill Deacon pte = pte_mkdirty(pte); 202ff1712f9SWill Deacon 203ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 204ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 205ff1712f9SWill Deacon return pte; 206ff1712f9SWill Deacon } 207ff1712f9SWill Deacon 20844b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 20944b6dfc5SSteve Capper { 210b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 21144b6dfc5SSteve Capper } 21244b6dfc5SSteve Capper 21344b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 21444b6dfc5SSteve Capper { 215b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 21644b6dfc5SSteve Capper } 21744b6dfc5SSteve Capper 21844b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 21944b6dfc5SSteve Capper { 220b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 22144b6dfc5SSteve Capper } 2224f04d8f0SCatalin Marinas 22393ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 22493ef666aSJeremy Linton { 22566b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 22666b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 22793ef666aSJeremy Linton } 22893ef666aSJeremy Linton 22993ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 23093ef666aSJeremy Linton { 23193ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 23293ef666aSJeremy Linton } 23393ef666aSJeremy Linton 2345ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2355ebe3a44SJames Morse { 2365ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2375ebe3a44SJames Morse } 2385ebe3a44SJames Morse 23966b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 24066b3923aSDavid Woods { 24166b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 24266b3923aSDavid Woods } 24366b3923aSDavid Woods 24473b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 24573b20c84SRobin Murphy { 24630e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 24773b20c84SRobin Murphy } 24873b20c84SRobin Murphy 2494f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2504f04d8f0SCatalin Marinas { 25120a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2527f0b1bf0SCatalin Marinas 2537f0b1bf0SCatalin Marinas /* 2547f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2557f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2567f0b1bf0SCatalin Marinas */ 257d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2587f0b1bf0SCatalin Marinas dsb(ishst); 259d0b7a302SWill Deacon isb(); 260d0b7a302SWill Deacon } 2614f04d8f0SCatalin Marinas } 2624f04d8f0SCatalin Marinas 263907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2644f04d8f0SCatalin Marinas 2652f4b829cSCatalin Marinas /* 2662f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2672f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2682f4b829cSCatalin Marinas * 2692f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2702f4b829cSCatalin Marinas * 0 0 | 1 0 0 2712f4b829cSCatalin Marinas * 0 1 | 1 1 0 2722f4b829cSCatalin Marinas * 1 0 | 1 0 1 2732f4b829cSCatalin Marinas * 1 1 | 0 1 x 2742f4b829cSCatalin Marinas * 2752f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2762f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2772f4b829cSCatalin Marinas * 278b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2792f4b829cSCatalin Marinas */ 2809b604722SMark Rutland 2819b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2829b604722SMark Rutland pte_t pte) 2834f04d8f0SCatalin Marinas { 28420a004e7SWill Deacon pte_t old_pte; 28520a004e7SWill Deacon 2869b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2879b604722SMark Rutland return; 2889b604722SMark Rutland 2899b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2909b604722SMark Rutland 2919b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2929b604722SMark Rutland return; 2939b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2949b604722SMark Rutland return; 29502522463SWill Deacon 2962f4b829cSCatalin Marinas /* 2979b604722SMark Rutland * Check for potential race with hardware updates of the pte 2989b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2999b604722SMark Rutland * through an invalid entry). 3002f4b829cSCatalin Marinas */ 30182d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 30282d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 30320a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 30420a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 30582d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 30620a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 3072f4b829cSCatalin Marinas } 3082f4b829cSCatalin Marinas 3099b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 3109b604722SMark Rutland pte_t *ptep, pte_t pte) 3119b604722SMark Rutland { 3129b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3139b604722SMark Rutland __sync_icache_dcache(pte); 3149b604722SMark Rutland 31569e3b846SSteven Price /* 31669e3b846SSteven Price * If the PTE would provide user space access to the tags associated 31769e3b846SSteven Price * with it then ensure that the MTE tags are synchronised. Although 31869e3b846SSteven Price * pte_access_permitted() returns false for exec only mappings, they 31969e3b846SSteven Price * don't expose tags (instruction fetches don't check tags). 32069e3b846SSteven Price */ 32169e3b846SSteven Price if (system_supports_mte() && pte_access_permitted(pte, false) && 32269e3b846SSteven Price !pte_special(pte)) { 32369e3b846SSteven Price pte_t old_pte = READ_ONCE(*ptep); 32469e3b846SSteven Price /* 32569e3b846SSteven Price * We only need to synchronise if the new PTE has tags enabled 32669e3b846SSteven Price * or if swapping in (in which case another mapping may have 32769e3b846SSteven Price * set tags in the past even if this PTE isn't tagged). 32869e3b846SSteven Price * (!pte_none() && !pte_present()) is an open coded version of 32969e3b846SSteven Price * is_swap_pte() 33069e3b846SSteven Price */ 33169e3b846SSteven Price if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte))) 33269e3b846SSteven Price mte_sync_tags(old_pte, pte); 33369e3b846SSteven Price } 33434bfeea4SCatalin Marinas 3359b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 3369b604722SMark Rutland 3374f04d8f0SCatalin Marinas set_pte(ptep, pte); 3384f04d8f0SCatalin Marinas } 3394f04d8f0SCatalin Marinas 3404f04d8f0SCatalin Marinas /* 3414f04d8f0SCatalin Marinas * Huge pte definitions. 3424f04d8f0SCatalin Marinas */ 343084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 344084bd298SSteve Capper 345084bd298SSteve Capper /* 346084bd298SSteve Capper * Hugetlb definitions. 347084bd298SSteve Capper */ 34866b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 349084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 350084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 351084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 352084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3534f04d8f0SCatalin Marinas 35475387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 35575387b92SKristina Martsenko { 35675387b92SKristina Martsenko return __pte(pgd_val(pgd)); 35775387b92SKristina Martsenko } 35875387b92SKristina Martsenko 359e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 360e9f63768SMike Rapoport { 361e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 362e9f63768SMike Rapoport } 363e9f63768SMike Rapoport 36429e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 36529e56940SSteve Capper { 36629e56940SSteve Capper return __pte(pud_val(pud)); 36729e56940SSteve Capper } 36829e56940SSteve Capper 369eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 370eb3f0624SPunit Agrawal { 371eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 372eb3f0624SPunit Agrawal } 373eb3f0624SPunit Agrawal 37429e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 37529e56940SSteve Capper { 37629e56940SSteve Capper return __pmd(pud_val(pud)); 37729e56940SSteve Capper } 37829e56940SSteve Capper 3799c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3809c7e535fSSteve Capper { 3819c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3829c7e535fSSteve Capper } 383af074848SSteve Capper 3849c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3859c7e535fSSteve Capper { 3869c7e535fSSteve Capper return __pmd(pte_val(pte)); 3879c7e535fSSteve Capper } 388af074848SSteve Capper 389f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3908ce837ceSArd Biesheuvel { 391f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 392f7f0097aSAnshuman Khandual } 393f7f0097aSAnshuman Khandual 394f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 395f7f0097aSAnshuman Khandual { 396f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3978ce837ceSArd Biesheuvel } 3988ce837ceSArd Biesheuvel 39956166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 40056166230SGanapatrao Kulkarni /* 401ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 40256166230SGanapatrao Kulkarni */ 40356166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 40456166230SGanapatrao Kulkarni { 40556166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 40656166230SGanapatrao Kulkarni } 40756166230SGanapatrao Kulkarni 40856166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 40956166230SGanapatrao Kulkarni { 41056166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 41156166230SGanapatrao Kulkarni } 41256166230SGanapatrao Kulkarni #endif 41356166230SGanapatrao Kulkarni 414b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 415b65399f6SAnshuman Khandual 416b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 417b65399f6SAnshuman Khandual { 418b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 419b65399f6SAnshuman Khandual } 420b65399f6SAnshuman Khandual 421af074848SSteve Capper /* 422af074848SSteve Capper * THP definitions. 423af074848SSteve Capper */ 424af074848SSteve Capper 425af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 426b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 427b65399f6SAnshuman Khandual { 428b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 429b65399f6SAnshuman Khandual } 43029e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 431af074848SSteve Capper 432c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 4339c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 4340795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 435d55863dbSPeter Zijlstra #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 4369c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 4379c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 4389c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 43905ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 4409c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 4419c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 442b65399f6SAnshuman Khandual 443b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 444b65399f6SAnshuman Khandual { 445b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 446b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 447b65399f6SAnshuman Khandual 448b65399f6SAnshuman Khandual return pmd; 449b65399f6SAnshuman Khandual } 450af074848SSteve Capper 4510dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 4520dbd3b18SSuzuki K Poulose 4539c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 454af074848SSteve Capper 455af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 456af074848SSteve Capper 45773b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 45873b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 45973b20c84SRobin Murphy #endif 46030e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 46130e23538SJia He { 46230e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 46330e23538SJia He } 46473b20c84SRobin Murphy 46575387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 46675387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 46775387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 46875387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 469af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 470af074848SSteve Capper 47135a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 472eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 47329e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 47475387b92SKristina Martsenko 475b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 476b8e0ba7cSPunit Agrawal 47775387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 47875387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 47975387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 48075387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 481af074848SSteve Capper 482ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 483f5308c89SKalesh Singh #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)) 484af074848SSteve Capper 485e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 486e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 487e9f63768SMike Rapoport 48875387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 48975387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 49075387b92SKristina Martsenko 491a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 492a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 493a501e324SCatalin Marinas 494cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 495034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 496cca98e9fSChristoph Hellwig 497af074848SSteve Capper /* 4984f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4994f04d8f0SCatalin Marinas */ 5004f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 501de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 5024f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 503de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 504d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 505d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 506d15dfd31SCatalin Marinas #define pgprot_tagged(prot) \ 507d15dfd31SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 508d15dfd31SCatalin Marinas #define pgprot_mhp pgprot_tagged 5093e4e1d3fSChristoph Hellwig /* 5103e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 5113e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 5123e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 5133e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 5143e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 5153e4e1d3fSChristoph Hellwig * endpoint. 5163e4e1d3fSChristoph Hellwig */ 517419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 518419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 519419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 520419e2f18SChristoph Hellwig 5214f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 5224f04d8f0SCatalin Marinas struct file; 5234f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 5244f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 5254f04d8f0SCatalin Marinas 5264f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 5274f04d8f0SCatalin Marinas 52836311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 52936311607SMarc Zyngier PMD_TYPE_TABLE) 53036311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 53136311607SMarc Zyngier PMD_TYPE_SECT) 5328aa82df3SSteven Price #define pmd_leaf(pmd) pmd_sect(pmd) 533e377ab82SAnshuman Khandual #define pmd_bad(pmd) (!pmd_table(pmd)) 53436311607SMarc Zyngier 535d55863dbSPeter Zijlstra #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 536d55863dbSPeter Zijlstra #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 537d55863dbSPeter Zijlstra 538cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 5397d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 5407d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 541206a2a73SSteve Capper #else 542206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 543206a2a73SSteve Capper PUD_TYPE_SECT) 544523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 545523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 546206a2a73SSteve Capper #endif 54736311607SMarc Zyngier 5482330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 5492330b7caSJun Yao extern pgd_t init_pg_end[]; 5502330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 5512330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 5529d2d75edSGavin Shan extern pgd_t idmap_pg_end[]; 5532330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 554833be850SMark Rutland extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 5552330b7caSJun Yao 5562330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 5572330b7caSJun Yao 5582330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 5592330b7caSJun Yao { 5602330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 5612330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 5622330b7caSJun Yao } 5632330b7caSJun Yao 5644f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 5654f04d8f0SCatalin Marinas { 566e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 567e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 5682330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 5692330b7caSJun Yao return; 5702330b7caSJun Yao } 571e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 5722330b7caSJun Yao 57320a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 5740795edafSWill Deacon 575d0b7a302SWill Deacon if (pmd_valid(pmd)) { 57698f7685eSWill Deacon dsb(ishst); 577d0b7a302SWill Deacon isb(); 578d0b7a302SWill Deacon } 5794f04d8f0SCatalin Marinas } 5804f04d8f0SCatalin Marinas 5814f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 5824f04d8f0SCatalin Marinas { 5834f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 5844f04d8f0SCatalin Marinas } 5854f04d8f0SCatalin Marinas 586dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 5874f04d8f0SCatalin Marinas { 58875387b92SKristina Martsenko return __pmd_to_phys(pmd); 5894f04d8f0SCatalin Marinas } 5904f04d8f0SCatalin Marinas 591974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 592974b9b2cSMike Rapoport { 593974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 594974b9b2cSMike Rapoport } 59574dd022fSQian Cai 596053520f7SMark Rutland /* Find an entry in the third-level page table. */ 597f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 598053520f7SMark Rutland 599961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 600961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 601961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 602961faac1SMark Rutland 60368ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 6044f04d8f0SCatalin Marinas 6056533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6066533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 6076533945aSArd Biesheuvel 6084f04d8f0SCatalin Marinas /* 6094f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 6104f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 6114f04d8f0SCatalin Marinas */ 6124f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 6134f04d8f0SCatalin Marinas 6149f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 6154f04d8f0SCatalin Marinas 6162cf660ebSGavin Shan #define pmd_ERROR(e) \ 6172cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 6187078db46SCatalin Marinas 6194f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 620e377ab82SAnshuman Khandual #define pud_bad(pud) (!pud_table(pud)) 621f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 6228aa82df3SSteven Price #define pud_leaf(pud) pud_sect(pud) 6230795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 6244f04d8f0SCatalin Marinas 6254f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 6264f04d8f0SCatalin Marinas { 627e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 628e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 6292330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 6302330b7caSJun Yao return; 6312330b7caSJun Yao } 632e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 6332330b7caSJun Yao 63420a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 6350795edafSWill Deacon 636d0b7a302SWill Deacon if (pud_valid(pud)) { 63798f7685eSWill Deacon dsb(ishst); 638d0b7a302SWill Deacon isb(); 639d0b7a302SWill Deacon } 6404f04d8f0SCatalin Marinas } 6414f04d8f0SCatalin Marinas 6424f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 6434f04d8f0SCatalin Marinas { 6444f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 6454f04d8f0SCatalin Marinas } 6464f04d8f0SCatalin Marinas 647dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 6484f04d8f0SCatalin Marinas { 64975387b92SKristina Martsenko return __pud_to_phys(pud); 6504f04d8f0SCatalin Marinas } 6514f04d8f0SCatalin Marinas 6529cf6fa24SAneesh Kumar K.V static inline pmd_t *pud_pgtable(pud_t pud) 653974b9b2cSMike Rapoport { 6549cf6fa24SAneesh Kumar K.V return (pmd_t *)__va(pud_page_paddr(pud)); 655974b9b2cSMike Rapoport } 6567078db46SCatalin Marinas 657974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 65820a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 6597078db46SCatalin Marinas 660961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 661961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 662961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 6634f04d8f0SCatalin Marinas 66468ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 66529e56940SSteve Capper 6666533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6676533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 6686533945aSArd Biesheuvel 669dca56dcaSMark Rutland #else 670dca56dcaSMark Rutland 671dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 672dca56dcaSMark Rutland 673961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 674961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 675961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 676961faac1SMark Rutland #define pmd_clear_fixmap() 677961faac1SMark Rutland 6786533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 6796533945aSArd Biesheuvel 6809f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 6814f04d8f0SCatalin Marinas 6829f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 683c79b954bSJungseok Lee 6842cf660ebSGavin Shan #define pud_ERROR(e) \ 6852cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 6867078db46SCatalin Marinas 687e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 688e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 689e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 690c79b954bSJungseok Lee 691e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 692c79b954bSJungseok Lee { 693e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 694e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 6952330b7caSJun Yao return; 6962330b7caSJun Yao } 6972330b7caSJun Yao 698e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 699c79b954bSJungseok Lee dsb(ishst); 700eb6a4dccSWill Deacon isb(); 701c79b954bSJungseok Lee } 702c79b954bSJungseok Lee 703e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 704c79b954bSJungseok Lee { 705e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 706c79b954bSJungseok Lee } 707c79b954bSJungseok Lee 708e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 709c79b954bSJungseok Lee { 710e9f63768SMike Rapoport return __p4d_to_phys(p4d); 711c79b954bSJungseok Lee } 712c79b954bSJungseok Lee 713*dc4875f0SAneesh Kumar K.V static inline pud_t *p4d_pgtable(p4d_t p4d) 714974b9b2cSMike Rapoport { 715*dc4875f0SAneesh Kumar K.V return (pud_t *)__va(p4d_page_paddr(p4d)); 716974b9b2cSMike Rapoport } 7177078db46SCatalin Marinas 718974b9b2cSMike Rapoport /* Find an entry in the frst-level page table. */ 719e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 7207078db46SCatalin Marinas 721961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 722e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 723961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 724c79b954bSJungseok Lee 725e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 7265d96e0cbSJungseok Lee 7276533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7286533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 7296533945aSArd Biesheuvel 730dca56dcaSMark Rutland #else 731dca56dcaSMark Rutland 732e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 733dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 734dca56dcaSMark Rutland 735961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 736961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 737961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 738961faac1SMark Rutland #define pud_clear_fixmap() 739961faac1SMark Rutland 7406533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 7416533945aSArd Biesheuvel 7429f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 743c79b954bSJungseok Lee 7442cf660ebSGavin Shan #define pgd_ERROR(e) \ 7452cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 7467078db46SCatalin Marinas 747961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 748961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 749961faac1SMark Rutland 7504f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 7514f04d8f0SCatalin Marinas { 7529f341931SCatalin Marinas /* 7539f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 7549f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 7559f341931SCatalin Marinas */ 756a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 7579f341931SCatalin Marinas PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 7589f341931SCatalin Marinas PTE_ATTRINDX_MASK; 7592f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 7602f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 76162d96c71SCatalin Marinas pte = pte_mkdirty(pte); 7624f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 7634f04d8f0SCatalin Marinas return pte; 7644f04d8f0SCatalin Marinas } 7654f04d8f0SCatalin Marinas 7669c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 7679c7e535fSSteve Capper { 7689c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 7699c7e535fSSteve Capper } 7709c7e535fSSteve Capper 77166dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 77266dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 77366dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 77466dbd6e6SCatalin Marinas pte_t entry, int dirty); 77566dbd6e6SCatalin Marinas 776282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 777282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 778282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 779282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 780282aa705SCatalin Marinas pmd_t entry, int dirty) 781282aa705SCatalin Marinas { 782282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 783282aa705SCatalin Marinas } 78473b20c84SRobin Murphy 78573b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 78673b20c84SRobin Murphy { 78773b20c84SRobin Murphy return 0; 78873b20c84SRobin Murphy } 78973b20c84SRobin Murphy 79073b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 79173b20c84SRobin Murphy { 79273b20c84SRobin Murphy return 0; 79373b20c84SRobin Murphy } 794282aa705SCatalin Marinas #endif 795282aa705SCatalin Marinas 7962f4b829cSCatalin Marinas /* 7972f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7982f4b829cSCatalin Marinas */ 7992f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 80006485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 8012f4b829cSCatalin Marinas { 8023bbf7157SCatalin Marinas pte_t old_pte, pte; 8032f4b829cSCatalin Marinas 8043bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 8053bbf7157SCatalin Marinas do { 8063bbf7157SCatalin Marinas old_pte = pte; 8073bbf7157SCatalin Marinas pte = pte_mkold(pte); 8083bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8093bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8103bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8112f4b829cSCatalin Marinas 8123bbf7157SCatalin Marinas return pte_young(pte); 8132f4b829cSCatalin Marinas } 8142f4b829cSCatalin Marinas 81506485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 81606485053SCatalin Marinas unsigned long address, 81706485053SCatalin Marinas pte_t *ptep) 81806485053SCatalin Marinas { 81906485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 82006485053SCatalin Marinas } 82106485053SCatalin Marinas 8223403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 8233403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 8243403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 8253403e56bSAlex Van Brunt { 8263403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 8273403e56bSAlex Van Brunt 8283403e56bSAlex Van Brunt if (young) { 8293403e56bSAlex Van Brunt /* 8303403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 8313403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 8323403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 8333403e56bSAlex Van Brunt * window for such an event is bounded by the next 8343403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 8353403e56bSAlex Van Brunt * invalidation. 8363403e56bSAlex Van Brunt */ 8373403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 8383403e56bSAlex Van Brunt } 8393403e56bSAlex Van Brunt 8403403e56bSAlex Van Brunt return young; 8413403e56bSAlex Van Brunt } 8423403e56bSAlex Van Brunt 8432f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8442f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 8452f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 8462f4b829cSCatalin Marinas unsigned long address, 8472f4b829cSCatalin Marinas pmd_t *pmdp) 8482f4b829cSCatalin Marinas { 8492f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 8502f4b829cSCatalin Marinas } 8512f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8522f4b829cSCatalin Marinas 8532f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 8542f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 8552f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 8562f4b829cSCatalin Marinas { 8573bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 8582f4b829cSCatalin Marinas } 8592f4b829cSCatalin Marinas 8602f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 861911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 862911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 8632f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8642f4b829cSCatalin Marinas { 8652f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 8662f4b829cSCatalin Marinas } 8672f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8682f4b829cSCatalin Marinas 8692f4b829cSCatalin Marinas /* 8708781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 8718781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 8722f4b829cSCatalin Marinas */ 8732f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 8742f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 8752f4b829cSCatalin Marinas { 8763bbf7157SCatalin Marinas pte_t old_pte, pte; 8772f4b829cSCatalin Marinas 8783bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 8793bbf7157SCatalin Marinas do { 8803bbf7157SCatalin Marinas old_pte = pte; 8813bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 8823bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8833bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8843bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8852f4b829cSCatalin Marinas } 8862f4b829cSCatalin Marinas 8872f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8882f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8892f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8902f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8912f4b829cSCatalin Marinas { 8922f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8932f4b829cSCatalin Marinas } 8941d78a62cSCatalin Marinas 8951d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8961d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8971d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8981d78a62cSCatalin Marinas { 8991d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 9001d78a62cSCatalin Marinas } 9012f4b829cSCatalin Marinas #endif 9022f4b829cSCatalin Marinas 9034f04d8f0SCatalin Marinas /* 9044f04d8f0SCatalin Marinas * Encode and decode a swap entry: 9053676f9efSCatalin Marinas * bits 0-1: present (must be zero) 9069b3e661eSKirill A. Shutemov * bits 2-7: swap type 9079b3e661eSKirill A. Shutemov * bits 8-57: swap offset 908fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 9094f04d8f0SCatalin Marinas */ 9109b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 9114f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 9129b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 9134f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 9144f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 9153676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 9164f04d8f0SCatalin Marinas 9174f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 9183676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 9194f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 9204f04d8f0SCatalin Marinas 9214f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 9224f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 9234f04d8f0SCatalin Marinas 92453fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 92553fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 92653fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 92753fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 92853fa117bSAnshuman Khandual 9294f04d8f0SCatalin Marinas /* 9304f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 931aad9061bSGeert Uytterhoeven * PTEs. 9324f04d8f0SCatalin Marinas */ 9334f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 9344f04d8f0SCatalin Marinas 9354f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 9364f04d8f0SCatalin Marinas 93736943abaSSteven Price #ifdef CONFIG_ARM64_MTE 93836943abaSSteven Price 93936943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 94036943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 94136943abaSSteven Price { 94236943abaSSteven Price if (system_supports_mte()) 94336943abaSSteven Price return mte_save_tags(page); 94436943abaSSteven Price return 0; 94536943abaSSteven Price } 94636943abaSSteven Price 94736943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 94836943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 94936943abaSSteven Price { 95036943abaSSteven Price if (system_supports_mte()) 95136943abaSSteven Price mte_invalidate_tags(type, offset); 95236943abaSSteven Price } 95336943abaSSteven Price 95436943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 95536943abaSSteven Price { 95636943abaSSteven Price if (system_supports_mte()) 95736943abaSSteven Price mte_invalidate_tags_area(type); 95836943abaSSteven Price } 95936943abaSSteven Price 96036943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 96136943abaSSteven Price static inline void arch_swap_restore(swp_entry_t entry, struct page *page) 96236943abaSSteven Price { 96336943abaSSteven Price if (system_supports_mte() && mte_restore_tags(entry, page)) 96436943abaSSteven Price set_bit(PG_mte_tagged, &page->flags); 96536943abaSSteven Price } 96636943abaSSteven Price 96736943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 96836943abaSSteven Price 969cba3574fSWill Deacon /* 970cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 971cba3574fSWill Deacon */ 972cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 973cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 974cba3574fSWill Deacon { 975cba3574fSWill Deacon /* 976120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 977120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 978120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 979cba3574fSWill Deacon */ 980cba3574fSWill Deacon } 981cba3574fSWill Deacon 982cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 983cba3574fSWill Deacon 984529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 985529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 986529c4b05SKristina Martsenko #else 987529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 988529c4b05SKristina Martsenko #endif 989529c4b05SKristina Martsenko 9906af31226SJia He /* 9916af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 9926af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 9936af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 9946af31226SJia He * hardware-managed access flag on arm64. 9956af31226SJia He */ 9966af31226SJia He static inline bool arch_faults_on_old_pte(void) 9976af31226SJia He { 9986af31226SJia He WARN_ON(preemptible()); 9996af31226SJia He 10006af31226SJia He return !cpu_has_hw_af(); 10016af31226SJia He } 10026af31226SJia He #define arch_faults_on_old_pte arch_faults_on_old_pte 10030388f9c7SWill Deacon 10040388f9c7SWill Deacon /* 10050388f9c7SWill Deacon * Experimentally, it's cheap to set the access flag in hardware and we 10060388f9c7SWill Deacon * benefit from prefaulting mappings as 'old' to start with. 10070388f9c7SWill Deacon */ 10080388f9c7SWill Deacon static inline bool arch_wants_old_prefaulted_pte(void) 10090388f9c7SWill Deacon { 10100388f9c7SWill Deacon return !arch_faults_on_old_pte(); 10110388f9c7SWill Deacon } 10120388f9c7SWill Deacon #define arch_wants_old_prefaulted_pte arch_wants_old_prefaulted_pte 10136af31226SJia He 101418107f8aSVladimir Murzin static inline pgprot_t arch_filter_pgprot(pgprot_t prot) 101518107f8aSVladimir Murzin { 101618107f8aSVladimir Murzin if (cpus_have_const_cap(ARM64_HAS_EPAN)) 101718107f8aSVladimir Murzin return prot; 101818107f8aSVladimir Murzin 101918107f8aSVladimir Murzin if (pgprot_val(prot) != pgprot_val(PAGE_EXECONLY)) 102018107f8aSVladimir Murzin return prot; 102118107f8aSVladimir Murzin 102218107f8aSVladimir Murzin return PAGE_READONLY_EXEC; 102318107f8aSVladimir Murzin } 102418107f8aSVladimir Murzin 102518107f8aSVladimir Murzin 10264f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 10274f04d8f0SCatalin Marinas 10284f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 1029