1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 124f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 133eca86e7SMark Rutland #include <asm/pgtable-prot.h> 143403e56bSAlex Van Brunt #include <asm/tlbflush.h> 154f04d8f0SCatalin Marinas 164f04d8f0SCatalin Marinas /* 173e1907d5SArd Biesheuvel * VMALLOC range. 1808375198SCatalin Marinas * 19f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 203e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 213e1907d5SArd Biesheuvel * and fixed mappings 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2408375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 254f04d8f0SCatalin Marinas 263bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 274f04d8f0SCatalin Marinas 28d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 294f04d8f0SCatalin Marinas 304f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 312f4b829cSCatalin Marinas 323bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 33961faac1SMark Rutland #include <asm/fixmap.h> 342f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3586c9e812SWill Deacon #include <linux/mm_types.h> 3686c9e812SWill Deacon #include <linux/sched.h> 372f4b829cSCatalin Marinas 384f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 394f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 40c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 414f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 424f04d8f0SCatalin Marinas 434f04d8f0SCatalin Marinas /* 444f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 454f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 464f04d8f0SCatalin Marinas */ 475227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 482077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 494f04d8f0SCatalin Marinas 507078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 517078db46SCatalin Marinas 5275387b92SKristina Martsenko /* 5375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 5475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 5575387b92SKristina Martsenko */ 5675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 5775387b92SKristina Martsenko #define __pte_to_phys(pte) \ 5875387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 5975387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 6075387b92SKristina Martsenko #else 6175387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 6275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 6375387b92SKristina Martsenko #endif 644f04d8f0SCatalin Marinas 6575387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 6675387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 6775387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 684f04d8f0SCatalin Marinas 694f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 704f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 714f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 727078db46SCatalin Marinas 734f04d8f0SCatalin Marinas /* 744f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 754f04d8f0SCatalin Marinas */ 7684fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 7784fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 7884fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 7984fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 80ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 8193ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 8273b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 834f04d8f0SCatalin Marinas 84d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 85d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 86d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 87d27cfa1fSArd Biesheuvel }) 88d27cfa1fSArd Biesheuvel 89d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 90d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 91d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 92d27cfa1fSArd Biesheuvel }) 93d27cfa1fSArd Biesheuvel 94b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 952f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 962f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 972f4b829cSCatalin Marinas 98766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 99ec663d96SCatalin Marinas /* 100ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 101ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 102ec663d96SCatalin Marinas */ 103ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 104ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 10576c714beSWill Deacon #define pte_valid_young(pte) \ 10676c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1076218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1086218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 10976c714beSWill Deacon 11076c714beSWill Deacon /* 11176c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 11276c714beSWill Deacon * so that we don't erroneously return false for pages that have been 11376c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 11476c714beSWill Deacon */ 11576c714beSWill Deacon #define pte_accessible(mm, pte) \ 11676c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1174f04d8f0SCatalin Marinas 1186218f96cSCatalin Marinas /* 1196218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 1206218f96cSCatalin Marinas * write permission check) other than user execute-only which do not have the 1216218f96cSCatalin Marinas * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 1226218f96cSCatalin Marinas */ 1236218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1246218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1256218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1266218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1276218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1286218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1296218f96cSCatalin Marinas 130b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 131b6d4f280SLaura Abbott { 132b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 133b6d4f280SLaura Abbott return pte; 134b6d4f280SLaura Abbott } 135b6d4f280SLaura Abbott 136b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 137b6d4f280SLaura Abbott { 138b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 139b6d4f280SLaura Abbott return pte; 140b6d4f280SLaura Abbott } 141b6d4f280SLaura Abbott 14244b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 14344b6dfc5SSteve Capper { 14473e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 14573e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 14673e86cb0SCatalin Marinas return pte; 14744b6dfc5SSteve Capper } 1484f04d8f0SCatalin Marinas 14944b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 15044b6dfc5SSteve Capper { 15173e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 15273e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 15373e86cb0SCatalin Marinas return pte; 15444b6dfc5SSteve Capper } 15544b6dfc5SSteve Capper 15644b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 15744b6dfc5SSteve Capper { 1588781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1598781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1608781bcbcSSteve Capper 1618781bcbcSSteve Capper return pte; 16244b6dfc5SSteve Capper } 16344b6dfc5SSteve Capper 16444b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 16544b6dfc5SSteve Capper { 1668781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1678781bcbcSSteve Capper 1688781bcbcSSteve Capper if (pte_write(pte)) 1698781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1708781bcbcSSteve Capper 1718781bcbcSSteve Capper return pte; 17244b6dfc5SSteve Capper } 17344b6dfc5SSteve Capper 17444b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 17544b6dfc5SSteve Capper { 176b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 17744b6dfc5SSteve Capper } 17844b6dfc5SSteve Capper 17944b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 18044b6dfc5SSteve Capper { 181b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 18244b6dfc5SSteve Capper } 18344b6dfc5SSteve Capper 18444b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 18544b6dfc5SSteve Capper { 186b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 18744b6dfc5SSteve Capper } 1884f04d8f0SCatalin Marinas 18993ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 19093ef666aSJeremy Linton { 19166b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 19266b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 19393ef666aSJeremy Linton } 19493ef666aSJeremy Linton 19593ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 19693ef666aSJeremy Linton { 19793ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 19893ef666aSJeremy Linton } 19993ef666aSJeremy Linton 2005ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2015ebe3a44SJames Morse { 2025ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2035ebe3a44SJames Morse } 2045ebe3a44SJames Morse 20566b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 20666b3923aSDavid Woods { 20766b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 20866b3923aSDavid Woods } 20966b3923aSDavid Woods 21073b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 21173b20c84SRobin Murphy { 21273b20c84SRobin Murphy return set_pte_bit(pte, __pgprot(PTE_DEVMAP)); 21373b20c84SRobin Murphy } 21473b20c84SRobin Murphy 2154f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2164f04d8f0SCatalin Marinas { 21720a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2187f0b1bf0SCatalin Marinas 2197f0b1bf0SCatalin Marinas /* 2207f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2217f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2227f0b1bf0SCatalin Marinas */ 223*d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2247f0b1bf0SCatalin Marinas dsb(ishst); 225*d0b7a302SWill Deacon isb(); 226*d0b7a302SWill Deacon } 2274f04d8f0SCatalin Marinas } 2284f04d8f0SCatalin Marinas 229907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2304f04d8f0SCatalin Marinas 2312f4b829cSCatalin Marinas /* 2322f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2332f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2342f4b829cSCatalin Marinas * 2352f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2362f4b829cSCatalin Marinas * 0 0 | 1 0 0 2372f4b829cSCatalin Marinas * 0 1 | 1 1 0 2382f4b829cSCatalin Marinas * 1 0 | 1 0 1 2392f4b829cSCatalin Marinas * 1 1 | 0 1 x 2402f4b829cSCatalin Marinas * 2412f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2422f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2432f4b829cSCatalin Marinas * 244b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2452f4b829cSCatalin Marinas */ 2469b604722SMark Rutland 2479b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2489b604722SMark Rutland pte_t pte) 2494f04d8f0SCatalin Marinas { 25020a004e7SWill Deacon pte_t old_pte; 25120a004e7SWill Deacon 2529b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2539b604722SMark Rutland return; 2549b604722SMark Rutland 2559b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2569b604722SMark Rutland 2579b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2589b604722SMark Rutland return; 2599b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2609b604722SMark Rutland return; 26102522463SWill Deacon 2622f4b829cSCatalin Marinas /* 2639b604722SMark Rutland * Check for potential race with hardware updates of the pte 2649b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2659b604722SMark Rutland * through an invalid entry). 2662f4b829cSCatalin Marinas */ 26782d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 26882d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 26920a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 27020a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 27182d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 27220a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2732f4b829cSCatalin Marinas } 2742f4b829cSCatalin Marinas 2759b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2769b604722SMark Rutland pte_t *ptep, pte_t pte) 2779b604722SMark Rutland { 2789b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 2799b604722SMark Rutland __sync_icache_dcache(pte); 2809b604722SMark Rutland 2819b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 2829b604722SMark Rutland 2834f04d8f0SCatalin Marinas set_pte(ptep, pte); 2844f04d8f0SCatalin Marinas } 2854f04d8f0SCatalin Marinas 286747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 287747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 288747a70e6SSteve Capper { 289747a70e6SSteve Capper pteval_t lhs, rhs; 290747a70e6SSteve Capper 291747a70e6SSteve Capper lhs = pte_val(pte_a); 292747a70e6SSteve Capper rhs = pte_val(pte_b); 293747a70e6SSteve Capper 294747a70e6SSteve Capper if (pte_present(pte_a)) 295747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 296747a70e6SSteve Capper 297747a70e6SSteve Capper if (pte_present(pte_b)) 298747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 299747a70e6SSteve Capper 300747a70e6SSteve Capper return (lhs == rhs); 301747a70e6SSteve Capper } 302747a70e6SSteve Capper 3034f04d8f0SCatalin Marinas /* 3044f04d8f0SCatalin Marinas * Huge pte definitions. 3054f04d8f0SCatalin Marinas */ 306084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 307084bd298SSteve Capper 308084bd298SSteve Capper /* 309084bd298SSteve Capper * Hugetlb definitions. 310084bd298SSteve Capper */ 31166b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 312084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 313084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 314084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 315084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3164f04d8f0SCatalin Marinas 31775387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 31875387b92SKristina Martsenko { 31975387b92SKristina Martsenko return __pte(pgd_val(pgd)); 32075387b92SKristina Martsenko } 32175387b92SKristina Martsenko 32229e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 32329e56940SSteve Capper { 32429e56940SSteve Capper return __pte(pud_val(pud)); 32529e56940SSteve Capper } 32629e56940SSteve Capper 327eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 328eb3f0624SPunit Agrawal { 329eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 330eb3f0624SPunit Agrawal } 331eb3f0624SPunit Agrawal 33229e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 33329e56940SSteve Capper { 33429e56940SSteve Capper return __pmd(pud_val(pud)); 33529e56940SSteve Capper } 33629e56940SSteve Capper 3379c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3389c7e535fSSteve Capper { 3399c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3409c7e535fSSteve Capper } 341af074848SSteve Capper 3429c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3439c7e535fSSteve Capper { 3449c7e535fSSteve Capper return __pmd(pte_val(pte)); 3459c7e535fSSteve Capper } 346af074848SSteve Capper 347f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3488ce837ceSArd Biesheuvel { 349f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 350f7f0097aSAnshuman Khandual } 351f7f0097aSAnshuman Khandual 352f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 353f7f0097aSAnshuman Khandual { 354f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3558ce837ceSArd Biesheuvel } 3568ce837ceSArd Biesheuvel 35756166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 35856166230SGanapatrao Kulkarni /* 35956166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 36056166230SGanapatrao Kulkarni */ 36156166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 36256166230SGanapatrao Kulkarni { 36356166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 36456166230SGanapatrao Kulkarni } 36556166230SGanapatrao Kulkarni 36656166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 36756166230SGanapatrao Kulkarni { 36856166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 36956166230SGanapatrao Kulkarni } 37056166230SGanapatrao Kulkarni #endif 37156166230SGanapatrao Kulkarni 372af074848SSteve Capper /* 373af074848SSteve Capper * THP definitions. 374af074848SSteve Capper */ 375af074848SSteve Capper 376af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 377af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 37829e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 379af074848SSteve Capper 3805bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 381c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3829c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3830795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3849c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3859c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3869c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 38705ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3889c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3899c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3905bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 391af074848SSteve Capper 3920dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3930dbd3b18SSuzuki K Poulose 3949c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 395af074848SSteve Capper 396af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 397af074848SSteve Capper 39873b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39973b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 40073b20c84SRobin Murphy #endif 40173b20c84SRobin Murphy #define pmd_mkdevmap(pmd) pte_pmd(pte_mkdevmap(pmd_pte(pmd))) 40273b20c84SRobin Murphy 40375387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 40475387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 40575387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 40675387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 407af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 408af074848SSteve Capper 40935a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 410eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 41129e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 41275387b92SKristina Martsenko 413b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 414b8e0ba7cSPunit Agrawal 41575387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 41675387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 41775387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 41875387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 419af074848SSteve Capper 420ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 421af074848SSteve Capper 42275387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 42375387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 42475387b92SKristina Martsenko 425a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 426a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 427a501e324SCatalin Marinas 428af074848SSteve Capper /* 4294f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4304f04d8f0SCatalin Marinas */ 4314f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 432de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4334f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 434de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 435d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 436d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4374f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4384f04d8f0SCatalin Marinas struct file; 4394f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4404f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4414f04d8f0SCatalin Marinas 4424f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4434f04d8f0SCatalin Marinas 444ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4454f04d8f0SCatalin Marinas 44636311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 44736311607SMarc Zyngier PMD_TYPE_TABLE) 44836311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 44936311607SMarc Zyngier PMD_TYPE_SECT) 45036311607SMarc Zyngier 451cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 4527d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 4537d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 454206a2a73SSteve Capper #else 455206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 456206a2a73SSteve Capper PUD_TYPE_SECT) 457523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 458523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 459206a2a73SSteve Capper #endif 46036311607SMarc Zyngier 4612330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 4622330b7caSJun Yao extern pgd_t init_pg_end[]; 4632330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 4642330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 4652330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 4662330b7caSJun Yao 4672330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 4682330b7caSJun Yao 4692330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 4702330b7caSJun Yao { 4712330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 4722330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 4732330b7caSJun Yao } 4742330b7caSJun Yao 4754f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4764f04d8f0SCatalin Marinas { 477e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 478e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 4792330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 4802330b7caSJun Yao return; 4812330b7caSJun Yao } 482e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 4832330b7caSJun Yao 48420a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 4850795edafSWill Deacon 486*d0b7a302SWill Deacon if (pmd_valid(pmd)) { 48798f7685eSWill Deacon dsb(ishst); 488*d0b7a302SWill Deacon isb(); 489*d0b7a302SWill Deacon } 4904f04d8f0SCatalin Marinas } 4914f04d8f0SCatalin Marinas 4924f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4934f04d8f0SCatalin Marinas { 4944f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4954f04d8f0SCatalin Marinas } 4964f04d8f0SCatalin Marinas 497dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4984f04d8f0SCatalin Marinas { 49975387b92SKristina Martsenko return __pmd_to_phys(pmd); 5004f04d8f0SCatalin Marinas } 5014f04d8f0SCatalin Marinas 50274dd022fSQian Cai static inline void pte_unmap(pte_t *pte) { } 50374dd022fSQian Cai 504053520f7SMark Rutland /* Find an entry in the third-level page table. */ 505053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 506053520f7SMark Rutland 507f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 508dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 509053520f7SMark Rutland 510053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 511053520f7SMark Rutland 512961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 513961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 514961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 515961faac1SMark Rutland 51675387b92SKristina Martsenko #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 5174f04d8f0SCatalin Marinas 5186533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5196533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 5206533945aSArd Biesheuvel 5214f04d8f0SCatalin Marinas /* 5224f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 5234f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 5244f04d8f0SCatalin Marinas */ 5254f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 5264f04d8f0SCatalin Marinas 5279f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 5284f04d8f0SCatalin Marinas 5297078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 5307078db46SCatalin Marinas 5314f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 532ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 533f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5340795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5354f04d8f0SCatalin Marinas 5364f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5374f04d8f0SCatalin Marinas { 538e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 539e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5402330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5412330b7caSJun Yao return; 5422330b7caSJun Yao } 543e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5442330b7caSJun Yao 54520a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5460795edafSWill Deacon 547*d0b7a302SWill Deacon if (pud_valid(pud)) { 54898f7685eSWill Deacon dsb(ishst); 549*d0b7a302SWill Deacon isb(); 550*d0b7a302SWill Deacon } 5514f04d8f0SCatalin Marinas } 5524f04d8f0SCatalin Marinas 5534f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5544f04d8f0SCatalin Marinas { 5554f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 5564f04d8f0SCatalin Marinas } 5574f04d8f0SCatalin Marinas 558dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 5594f04d8f0SCatalin Marinas { 56075387b92SKristina Martsenko return __pud_to_phys(pud); 5614f04d8f0SCatalin Marinas } 5624f04d8f0SCatalin Marinas 5637078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 5647078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 5657078db46SCatalin Marinas 56620a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 567dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 5687078db46SCatalin Marinas 569961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 570961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 571961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5724f04d8f0SCatalin Marinas 57375387b92SKristina Martsenko #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 57429e56940SSteve Capper 5756533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5766533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5776533945aSArd Biesheuvel 578dca56dcaSMark Rutland #else 579dca56dcaSMark Rutland 580dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 581dca56dcaSMark Rutland 582961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 583961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 584961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 585961faac1SMark Rutland #define pmd_clear_fixmap() 586961faac1SMark Rutland 5876533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 5886533945aSArd Biesheuvel 5899f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 5904f04d8f0SCatalin Marinas 5919f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 592c79b954bSJungseok Lee 5937078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 5947078db46SCatalin Marinas 595c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 596c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 597c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 598c79b954bSJungseok Lee 599c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 600c79b954bSJungseok Lee { 6012330b7caSJun Yao if (in_swapper_pgdir(pgdp)) { 6022330b7caSJun Yao set_swapper_pgd(pgdp, pgd); 6032330b7caSJun Yao return; 6042330b7caSJun Yao } 6052330b7caSJun Yao 60620a004e7SWill Deacon WRITE_ONCE(*pgdp, pgd); 607c79b954bSJungseok Lee dsb(ishst); 608c79b954bSJungseok Lee } 609c79b954bSJungseok Lee 610c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 611c79b954bSJungseok Lee { 612c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 613c79b954bSJungseok Lee } 614c79b954bSJungseok Lee 615dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 616c79b954bSJungseok Lee { 61775387b92SKristina Martsenko return __pgd_to_phys(pgd); 618c79b954bSJungseok Lee } 619c79b954bSJungseok Lee 6207078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 6217078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 6227078db46SCatalin Marinas 62320a004e7SWill Deacon #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 624dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 6257078db46SCatalin Marinas 626961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 627961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 628961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 629c79b954bSJungseok Lee 63075387b92SKristina Martsenko #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 6315d96e0cbSJungseok Lee 6326533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6336533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6346533945aSArd Biesheuvel 635dca56dcaSMark Rutland #else 636dca56dcaSMark Rutland 637dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 638dca56dcaSMark Rutland 639961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 640961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 641961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 642961faac1SMark Rutland #define pud_clear_fixmap() 643961faac1SMark Rutland 6446533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6456533945aSArd Biesheuvel 6469f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 647c79b954bSJungseok Lee 6487078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 6497078db46SCatalin Marinas 6504f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 6514f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 6524f04d8f0SCatalin Marinas 653dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 654dca56dcaSMark Rutland 655dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 6564f04d8f0SCatalin Marinas 6574f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 6584f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 6594f04d8f0SCatalin Marinas 660961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 661961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 662961faac1SMark Rutland 6634f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 6644f04d8f0SCatalin Marinas { 665a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6661a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 6672f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6682f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 66962d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6704f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6714f04d8f0SCatalin Marinas return pte; 6724f04d8f0SCatalin Marinas } 6734f04d8f0SCatalin Marinas 6749c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6759c7e535fSSteve Capper { 6769c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6779c7e535fSSteve Capper } 6789c7e535fSSteve Capper 67966dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 68066dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 68166dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 68266dbd6e6SCatalin Marinas pte_t entry, int dirty); 68366dbd6e6SCatalin Marinas 684282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 685282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 686282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 687282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 688282aa705SCatalin Marinas pmd_t entry, int dirty) 689282aa705SCatalin Marinas { 690282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 691282aa705SCatalin Marinas } 69273b20c84SRobin Murphy 69373b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 69473b20c84SRobin Murphy { 69573b20c84SRobin Murphy return 0; 69673b20c84SRobin Murphy } 69773b20c84SRobin Murphy 69873b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 69973b20c84SRobin Murphy { 70073b20c84SRobin Murphy return 0; 70173b20c84SRobin Murphy } 702282aa705SCatalin Marinas #endif 703282aa705SCatalin Marinas 7042f4b829cSCatalin Marinas /* 7052f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7062f4b829cSCatalin Marinas */ 7072f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 70806485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 7092f4b829cSCatalin Marinas { 7103bbf7157SCatalin Marinas pte_t old_pte, pte; 7112f4b829cSCatalin Marinas 7123bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7133bbf7157SCatalin Marinas do { 7143bbf7157SCatalin Marinas old_pte = pte; 7153bbf7157SCatalin Marinas pte = pte_mkold(pte); 7163bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7173bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7183bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7192f4b829cSCatalin Marinas 7203bbf7157SCatalin Marinas return pte_young(pte); 7212f4b829cSCatalin Marinas } 7222f4b829cSCatalin Marinas 72306485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 72406485053SCatalin Marinas unsigned long address, 72506485053SCatalin Marinas pte_t *ptep) 72606485053SCatalin Marinas { 72706485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 72806485053SCatalin Marinas } 72906485053SCatalin Marinas 7303403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 7313403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 7323403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 7333403e56bSAlex Van Brunt { 7343403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 7353403e56bSAlex Van Brunt 7363403e56bSAlex Van Brunt if (young) { 7373403e56bSAlex Van Brunt /* 7383403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 7393403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 7403403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 7413403e56bSAlex Van Brunt * window for such an event is bounded by the next 7423403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 7433403e56bSAlex Van Brunt * invalidation. 7443403e56bSAlex Van Brunt */ 7453403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 7463403e56bSAlex Van Brunt } 7473403e56bSAlex Van Brunt 7483403e56bSAlex Van Brunt return young; 7493403e56bSAlex Van Brunt } 7503403e56bSAlex Van Brunt 7512f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7522f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7532f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7542f4b829cSCatalin Marinas unsigned long address, 7552f4b829cSCatalin Marinas pmd_t *pmdp) 7562f4b829cSCatalin Marinas { 7572f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7582f4b829cSCatalin Marinas } 7592f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7602f4b829cSCatalin Marinas 7612f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 7622f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 7632f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 7642f4b829cSCatalin Marinas { 7653bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 7662f4b829cSCatalin Marinas } 7672f4b829cSCatalin Marinas 7682f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 769911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 770911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 7712f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7722f4b829cSCatalin Marinas { 7732f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 7742f4b829cSCatalin Marinas } 7752f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7762f4b829cSCatalin Marinas 7772f4b829cSCatalin Marinas /* 7788781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 7798781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 7802f4b829cSCatalin Marinas */ 7812f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 7822f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 7832f4b829cSCatalin Marinas { 7843bbf7157SCatalin Marinas pte_t old_pte, pte; 7852f4b829cSCatalin Marinas 7863bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7873bbf7157SCatalin Marinas do { 7883bbf7157SCatalin Marinas old_pte = pte; 7898781bcbcSSteve Capper /* 7908781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 7918781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 7928781bcbcSSteve Capper */ 7938781bcbcSSteve Capper if (pte_hw_dirty(pte)) 7948781bcbcSSteve Capper pte = pte_mkdirty(pte); 7953bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 7963bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7973bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7983bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7992f4b829cSCatalin Marinas } 8002f4b829cSCatalin Marinas 8012f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8022f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8032f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8042f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8052f4b829cSCatalin Marinas { 8062f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8072f4b829cSCatalin Marinas } 8081d78a62cSCatalin Marinas 8091d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8101d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8111d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8121d78a62cSCatalin Marinas { 8131d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 8141d78a62cSCatalin Marinas } 8152f4b829cSCatalin Marinas #endif 8162f4b829cSCatalin Marinas 8174f04d8f0SCatalin Marinas /* 8184f04d8f0SCatalin Marinas * Encode and decode a swap entry: 8193676f9efSCatalin Marinas * bits 0-1: present (must be zero) 8209b3e661eSKirill A. Shutemov * bits 2-7: swap type 8219b3e661eSKirill A. Shutemov * bits 8-57: swap offset 822fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 8234f04d8f0SCatalin Marinas */ 8249b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 8254f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 8269b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 8274f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 8284f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 8293676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 8304f04d8f0SCatalin Marinas 8314f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 8323676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 8334f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 8344f04d8f0SCatalin Marinas 8354f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 8364f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 8374f04d8f0SCatalin Marinas 8384f04d8f0SCatalin Marinas /* 8394f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 840aad9061bSGeert Uytterhoeven * PTEs. 8414f04d8f0SCatalin Marinas */ 8424f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 8434f04d8f0SCatalin Marinas 8444f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8454f04d8f0SCatalin Marinas 8464f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 8474f04d8f0SCatalin Marinas 848615c48adSMike Rapoport static inline void pgtable_cache_init(void) { } 8494f04d8f0SCatalin Marinas 850cba3574fSWill Deacon /* 851cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 852cba3574fSWill Deacon */ 853cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 854cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 855cba3574fSWill Deacon { 856cba3574fSWill Deacon /* 857120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 858120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 859120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 860cba3574fSWill Deacon */ 861cba3574fSWill Deacon } 862cba3574fSWill Deacon 863cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 864cba3574fSWill Deacon 86503875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 86603875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 8677db743c6SCatalin Marinas 868529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 869529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 870529c4b05SKristina Martsenko #else 871529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 872529c4b05SKristina Martsenko #endif 873529c4b05SKristina Martsenko 8744f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 8754f04d8f0SCatalin Marinas 8764f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 877