1*caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 124f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 133eca86e7SMark Rutland #include <asm/pgtable-prot.h> 143403e56bSAlex Van Brunt #include <asm/tlbflush.h> 154f04d8f0SCatalin Marinas 164f04d8f0SCatalin Marinas /* 173e1907d5SArd Biesheuvel * VMALLOC range. 1808375198SCatalin Marinas * 19f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 203e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 213e1907d5SArd Biesheuvel * and fixed mappings 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2408375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 254f04d8f0SCatalin Marinas 263bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 274f04d8f0SCatalin Marinas 28d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 294f04d8f0SCatalin Marinas 304f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 312f4b829cSCatalin Marinas 323bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 33961faac1SMark Rutland #include <asm/fixmap.h> 342f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3586c9e812SWill Deacon #include <linux/mm_types.h> 3686c9e812SWill Deacon #include <linux/sched.h> 372f4b829cSCatalin Marinas 384f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 394f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 40c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 414f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 424f04d8f0SCatalin Marinas 434f04d8f0SCatalin Marinas /* 444f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 454f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 464f04d8f0SCatalin Marinas */ 475227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 482077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 494f04d8f0SCatalin Marinas 507078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 517078db46SCatalin Marinas 5275387b92SKristina Martsenko /* 5375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 5475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 5575387b92SKristina Martsenko */ 5675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 5775387b92SKristina Martsenko #define __pte_to_phys(pte) \ 5875387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 5975387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 6075387b92SKristina Martsenko #else 6175387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 6275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 6375387b92SKristina Martsenko #endif 644f04d8f0SCatalin Marinas 6575387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 6675387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 6775387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 684f04d8f0SCatalin Marinas 694f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 704f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 714f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 727078db46SCatalin Marinas 734f04d8f0SCatalin Marinas /* 744f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 754f04d8f0SCatalin Marinas */ 7684fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 7784fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 7884fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 7984fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 80ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 8193ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 824f04d8f0SCatalin Marinas 83d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 84d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 85d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 86d27cfa1fSArd Biesheuvel }) 87d27cfa1fSArd Biesheuvel 88d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 89d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 90d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 91d27cfa1fSArd Biesheuvel }) 92d27cfa1fSArd Biesheuvel 93b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 942f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 952f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 962f4b829cSCatalin Marinas 97766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 98ec663d96SCatalin Marinas /* 99ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 100ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 101ec663d96SCatalin Marinas */ 102ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 103ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 10476c714beSWill Deacon #define pte_valid_young(pte) \ 10576c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1066218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1076218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 10876c714beSWill Deacon 10976c714beSWill Deacon /* 11076c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 11176c714beSWill Deacon * so that we don't erroneously return false for pages that have been 11276c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 11376c714beSWill Deacon */ 11476c714beSWill Deacon #define pte_accessible(mm, pte) \ 11576c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1164f04d8f0SCatalin Marinas 1176218f96cSCatalin Marinas /* 1186218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 1196218f96cSCatalin Marinas * write permission check) other than user execute-only which do not have the 1206218f96cSCatalin Marinas * PTE_USER bit set. PROT_NONE mappings do not have the PTE_VALID bit set. 1216218f96cSCatalin Marinas */ 1226218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1236218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1246218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1256218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1266218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1276218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1286218f96cSCatalin Marinas 129b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 130b6d4f280SLaura Abbott { 131b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 132b6d4f280SLaura Abbott return pte; 133b6d4f280SLaura Abbott } 134b6d4f280SLaura Abbott 135b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 136b6d4f280SLaura Abbott { 137b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 138b6d4f280SLaura Abbott return pte; 139b6d4f280SLaura Abbott } 140b6d4f280SLaura Abbott 14144b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 14244b6dfc5SSteve Capper { 14373e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 14473e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 14573e86cb0SCatalin Marinas return pte; 14644b6dfc5SSteve Capper } 1474f04d8f0SCatalin Marinas 14844b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 14944b6dfc5SSteve Capper { 15073e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 15173e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 15273e86cb0SCatalin Marinas return pte; 15344b6dfc5SSteve Capper } 15444b6dfc5SSteve Capper 15544b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 15644b6dfc5SSteve Capper { 1578781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1588781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1598781bcbcSSteve Capper 1608781bcbcSSteve Capper return pte; 16144b6dfc5SSteve Capper } 16244b6dfc5SSteve Capper 16344b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 16444b6dfc5SSteve Capper { 1658781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1668781bcbcSSteve Capper 1678781bcbcSSteve Capper if (pte_write(pte)) 1688781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1698781bcbcSSteve Capper 1708781bcbcSSteve Capper return pte; 17144b6dfc5SSteve Capper } 17244b6dfc5SSteve Capper 17344b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 17444b6dfc5SSteve Capper { 175b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 17644b6dfc5SSteve Capper } 17744b6dfc5SSteve Capper 17844b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 17944b6dfc5SSteve Capper { 180b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 18144b6dfc5SSteve Capper } 18244b6dfc5SSteve Capper 18344b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 18444b6dfc5SSteve Capper { 185b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 18644b6dfc5SSteve Capper } 1874f04d8f0SCatalin Marinas 18893ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 18993ef666aSJeremy Linton { 19066b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 19166b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 19293ef666aSJeremy Linton } 19393ef666aSJeremy Linton 19493ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 19593ef666aSJeremy Linton { 19693ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 19793ef666aSJeremy Linton } 19893ef666aSJeremy Linton 1995ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2005ebe3a44SJames Morse { 2015ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2025ebe3a44SJames Morse } 2035ebe3a44SJames Morse 20466b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 20566b3923aSDavid Woods { 20666b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 20766b3923aSDavid Woods } 20866b3923aSDavid Woods 2094f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2104f04d8f0SCatalin Marinas { 21120a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2127f0b1bf0SCatalin Marinas 2137f0b1bf0SCatalin Marinas /* 2147f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2157f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2167f0b1bf0SCatalin Marinas */ 21724fe1b0eSWill Deacon if (pte_valid_not_user(pte)) 2187f0b1bf0SCatalin Marinas dsb(ishst); 2194f04d8f0SCatalin Marinas } 2204f04d8f0SCatalin Marinas 221907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2224f04d8f0SCatalin Marinas 2232f4b829cSCatalin Marinas /* 2242f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2252f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2262f4b829cSCatalin Marinas * 2272f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2282f4b829cSCatalin Marinas * 0 0 | 1 0 0 2292f4b829cSCatalin Marinas * 0 1 | 1 1 0 2302f4b829cSCatalin Marinas * 1 0 | 1 0 1 2312f4b829cSCatalin Marinas * 1 1 | 0 1 x 2322f4b829cSCatalin Marinas * 2332f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2342f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2352f4b829cSCatalin Marinas * 236b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2372f4b829cSCatalin Marinas */ 2384f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2394f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2404f04d8f0SCatalin Marinas { 24120a004e7SWill Deacon pte_t old_pte; 24220a004e7SWill Deacon 24373e86cb0SCatalin Marinas if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 244907e21c1SShaokun Zhang __sync_icache_dcache(pte); 24502522463SWill Deacon 2462f4b829cSCatalin Marinas /* 2472f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2482f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2492f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2502f4b829cSCatalin Marinas */ 25120a004e7SWill Deacon old_pte = READ_ONCE(*ptep); 25220a004e7SWill Deacon if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) && 25386c9e812SWill Deacon (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) { 25482d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 25582d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 25620a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 25720a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 25882d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 25920a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2602f4b829cSCatalin Marinas } 2612f4b829cSCatalin Marinas 2624f04d8f0SCatalin Marinas set_pte(ptep, pte); 2634f04d8f0SCatalin Marinas } 2644f04d8f0SCatalin Marinas 265747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 266747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 267747a70e6SSteve Capper { 268747a70e6SSteve Capper pteval_t lhs, rhs; 269747a70e6SSteve Capper 270747a70e6SSteve Capper lhs = pte_val(pte_a); 271747a70e6SSteve Capper rhs = pte_val(pte_b); 272747a70e6SSteve Capper 273747a70e6SSteve Capper if (pte_present(pte_a)) 274747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 275747a70e6SSteve Capper 276747a70e6SSteve Capper if (pte_present(pte_b)) 277747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 278747a70e6SSteve Capper 279747a70e6SSteve Capper return (lhs == rhs); 280747a70e6SSteve Capper } 281747a70e6SSteve Capper 2824f04d8f0SCatalin Marinas /* 2834f04d8f0SCatalin Marinas * Huge pte definitions. 2844f04d8f0SCatalin Marinas */ 285084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 286084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 287084bd298SSteve Capper 288084bd298SSteve Capper /* 289084bd298SSteve Capper * Hugetlb definitions. 290084bd298SSteve Capper */ 29166b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 292084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 293084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 294084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 295084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 2964f04d8f0SCatalin Marinas 29775387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 29875387b92SKristina Martsenko { 29975387b92SKristina Martsenko return __pte(pgd_val(pgd)); 30075387b92SKristina Martsenko } 30175387b92SKristina Martsenko 30229e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 30329e56940SSteve Capper { 30429e56940SSteve Capper return __pte(pud_val(pud)); 30529e56940SSteve Capper } 30629e56940SSteve Capper 307eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 308eb3f0624SPunit Agrawal { 309eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 310eb3f0624SPunit Agrawal } 311eb3f0624SPunit Agrawal 31229e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 31329e56940SSteve Capper { 31429e56940SSteve Capper return __pmd(pud_val(pud)); 31529e56940SSteve Capper } 31629e56940SSteve Capper 3179c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3189c7e535fSSteve Capper { 3199c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3209c7e535fSSteve Capper } 321af074848SSteve Capper 3229c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3239c7e535fSSteve Capper { 3249c7e535fSSteve Capper return __pmd(pte_val(pte)); 3259c7e535fSSteve Capper } 326af074848SSteve Capper 3278ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 3288ce837ceSArd Biesheuvel { 3298ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3308ce837ceSArd Biesheuvel } 3318ce837ceSArd Biesheuvel 33256166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 33356166230SGanapatrao Kulkarni /* 33456166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 33556166230SGanapatrao Kulkarni */ 33656166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 33756166230SGanapatrao Kulkarni { 33856166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 33956166230SGanapatrao Kulkarni } 34056166230SGanapatrao Kulkarni 34156166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 34256166230SGanapatrao Kulkarni { 34356166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 34456166230SGanapatrao Kulkarni } 34556166230SGanapatrao Kulkarni #endif 34656166230SGanapatrao Kulkarni 347af074848SSteve Capper /* 348af074848SSteve Capper * THP definitions. 349af074848SSteve Capper */ 350af074848SSteve Capper 351af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 352af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 35329e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 354af074848SSteve Capper 3555bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 356c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3579c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3580795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3599c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3609c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3619c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 36205ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3639c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3649c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3655bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 366af074848SSteve Capper 3670dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3680dbd3b18SSuzuki K Poulose 3699c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 370af074848SSteve Capper 371af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 372af074848SSteve Capper 37375387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 37475387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 37575387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 37675387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 377af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 378af074848SSteve Capper 37935a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 380eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 38129e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 38275387b92SKristina Martsenko 383b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 384b8e0ba7cSPunit Agrawal 38575387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 38675387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 38775387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 38875387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 389af074848SSteve Capper 390ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 391af074848SSteve Capper 39275387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 39375387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 39475387b92SKristina Martsenko 395a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 396a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 397a501e324SCatalin Marinas 398af074848SSteve Capper /* 3994f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4004f04d8f0SCatalin Marinas */ 4014f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 402de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4034f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 404de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 405d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 406d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4074f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4084f04d8f0SCatalin Marinas struct file; 4094f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4104f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4114f04d8f0SCatalin Marinas 4124f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4134f04d8f0SCatalin Marinas 414ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4154f04d8f0SCatalin Marinas 41636311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 41736311607SMarc Zyngier PMD_TYPE_TABLE) 41836311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 41936311607SMarc Zyngier PMD_TYPE_SECT) 42036311607SMarc Zyngier 421cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 422206a2a73SSteve Capper #define pud_sect(pud) (0) 423523d6e9fSzhichang.yuan #define pud_table(pud) (1) 424206a2a73SSteve Capper #else 425206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 426206a2a73SSteve Capper PUD_TYPE_SECT) 427523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 428523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 429206a2a73SSteve Capper #endif 43036311607SMarc Zyngier 4312330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 4322330b7caSJun Yao extern pgd_t init_pg_end[]; 4332330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 4342330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 4352330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 4362330b7caSJun Yao 4372330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 4382330b7caSJun Yao 4392330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 4402330b7caSJun Yao { 4412330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 4422330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 4432330b7caSJun Yao } 4442330b7caSJun Yao 4454f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4464f04d8f0SCatalin Marinas { 447e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 448e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 4492330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 4502330b7caSJun Yao return; 4512330b7caSJun Yao } 452e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 4532330b7caSJun Yao 45420a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 4550795edafSWill Deacon 4560795edafSWill Deacon if (pmd_valid(pmd)) 45798f7685eSWill Deacon dsb(ishst); 4584f04d8f0SCatalin Marinas } 4594f04d8f0SCatalin Marinas 4604f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4614f04d8f0SCatalin Marinas { 4624f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4634f04d8f0SCatalin Marinas } 4644f04d8f0SCatalin Marinas 465dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4664f04d8f0SCatalin Marinas { 46775387b92SKristina Martsenko return __pmd_to_phys(pmd); 4684f04d8f0SCatalin Marinas } 4694f04d8f0SCatalin Marinas 47074dd022fSQian Cai static inline void pte_unmap(pte_t *pte) { } 47174dd022fSQian Cai 472053520f7SMark Rutland /* Find an entry in the third-level page table. */ 473053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 474053520f7SMark Rutland 475f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 476dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 477053520f7SMark Rutland 478053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 479053520f7SMark Rutland 480961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 481961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 482961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 483961faac1SMark Rutland 48475387b92SKristina Martsenko #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(__pmd_to_phys(pmd))) 4854f04d8f0SCatalin Marinas 4866533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4876533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 4886533945aSArd Biesheuvel 4894f04d8f0SCatalin Marinas /* 4904f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4914f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4924f04d8f0SCatalin Marinas */ 4934f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4944f04d8f0SCatalin Marinas 4959f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4964f04d8f0SCatalin Marinas 4977078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 4987078db46SCatalin Marinas 4994f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 500ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 501f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5020795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5034f04d8f0SCatalin Marinas 5044f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5054f04d8f0SCatalin Marinas { 506e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 507e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5082330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5092330b7caSJun Yao return; 5102330b7caSJun Yao } 511e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5122330b7caSJun Yao 51320a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5140795edafSWill Deacon 5150795edafSWill Deacon if (pud_valid(pud)) 51698f7685eSWill Deacon dsb(ishst); 5174f04d8f0SCatalin Marinas } 5184f04d8f0SCatalin Marinas 5194f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5204f04d8f0SCatalin Marinas { 5214f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 5224f04d8f0SCatalin Marinas } 5234f04d8f0SCatalin Marinas 524dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 5254f04d8f0SCatalin Marinas { 52675387b92SKristina Martsenko return __pud_to_phys(pud); 5274f04d8f0SCatalin Marinas } 5284f04d8f0SCatalin Marinas 5297078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 5307078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 5317078db46SCatalin Marinas 53220a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 533dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 5347078db46SCatalin Marinas 535961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 536961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 537961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5384f04d8f0SCatalin Marinas 53975387b92SKristina Martsenko #define pud_page(pud) pfn_to_page(__phys_to_pfn(__pud_to_phys(pud))) 54029e56940SSteve Capper 5416533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5426533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5436533945aSArd Biesheuvel 544dca56dcaSMark Rutland #else 545dca56dcaSMark Rutland 546dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 547dca56dcaSMark Rutland 548961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 549961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 550961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 551961faac1SMark Rutland #define pmd_clear_fixmap() 552961faac1SMark Rutland 5536533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 5546533945aSArd Biesheuvel 5559f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 5564f04d8f0SCatalin Marinas 5579f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 558c79b954bSJungseok Lee 5597078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 5607078db46SCatalin Marinas 561c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 562c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 563c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 564c79b954bSJungseok Lee 565c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 566c79b954bSJungseok Lee { 5672330b7caSJun Yao if (in_swapper_pgdir(pgdp)) { 5682330b7caSJun Yao set_swapper_pgd(pgdp, pgd); 5692330b7caSJun Yao return; 5702330b7caSJun Yao } 5712330b7caSJun Yao 57220a004e7SWill Deacon WRITE_ONCE(*pgdp, pgd); 573c79b954bSJungseok Lee dsb(ishst); 574c79b954bSJungseok Lee } 575c79b954bSJungseok Lee 576c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 577c79b954bSJungseok Lee { 578c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 579c79b954bSJungseok Lee } 580c79b954bSJungseok Lee 581dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 582c79b954bSJungseok Lee { 58375387b92SKristina Martsenko return __pgd_to_phys(pgd); 584c79b954bSJungseok Lee } 585c79b954bSJungseok Lee 5867078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5877078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5887078db46SCatalin Marinas 58920a004e7SWill Deacon #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 590dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 5917078db46SCatalin Marinas 592961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 593961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 594961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 595c79b954bSJungseok Lee 59675387b92SKristina Martsenko #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd))) 5975d96e0cbSJungseok Lee 5986533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5996533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6006533945aSArd Biesheuvel 601dca56dcaSMark Rutland #else 602dca56dcaSMark Rutland 603dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 604dca56dcaSMark Rutland 605961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 606961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 607961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 608961faac1SMark Rutland #define pud_clear_fixmap() 609961faac1SMark Rutland 6106533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6116533945aSArd Biesheuvel 6129f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 613c79b954bSJungseok Lee 6147078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 6157078db46SCatalin Marinas 6164f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 6174f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 6184f04d8f0SCatalin Marinas 619dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 620dca56dcaSMark Rutland 621dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 6224f04d8f0SCatalin Marinas 6234f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 6244f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 6254f04d8f0SCatalin Marinas 626961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 627961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 628961faac1SMark Rutland 6294f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 6304f04d8f0SCatalin Marinas { 631a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6321a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 6332f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6342f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 63562d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6364f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6374f04d8f0SCatalin Marinas return pte; 6384f04d8f0SCatalin Marinas } 6394f04d8f0SCatalin Marinas 6409c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6419c7e535fSSteve Capper { 6429c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6439c7e535fSSteve Capper } 6449c7e535fSSteve Capper 64566dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 64666dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 64766dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 64866dbd6e6SCatalin Marinas pte_t entry, int dirty); 64966dbd6e6SCatalin Marinas 650282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 651282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 652282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 653282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 654282aa705SCatalin Marinas pmd_t entry, int dirty) 655282aa705SCatalin Marinas { 656282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 657282aa705SCatalin Marinas } 658282aa705SCatalin Marinas #endif 659282aa705SCatalin Marinas 6602f4b829cSCatalin Marinas /* 6612f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 6622f4b829cSCatalin Marinas */ 6632f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 66406485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 6652f4b829cSCatalin Marinas { 6663bbf7157SCatalin Marinas pte_t old_pte, pte; 6672f4b829cSCatalin Marinas 6683bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6693bbf7157SCatalin Marinas do { 6703bbf7157SCatalin Marinas old_pte = pte; 6713bbf7157SCatalin Marinas pte = pte_mkold(pte); 6723bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6733bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6743bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6752f4b829cSCatalin Marinas 6763bbf7157SCatalin Marinas return pte_young(pte); 6772f4b829cSCatalin Marinas } 6782f4b829cSCatalin Marinas 67906485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 68006485053SCatalin Marinas unsigned long address, 68106485053SCatalin Marinas pte_t *ptep) 68206485053SCatalin Marinas { 68306485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 68406485053SCatalin Marinas } 68506485053SCatalin Marinas 6863403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 6873403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 6883403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 6893403e56bSAlex Van Brunt { 6903403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 6913403e56bSAlex Van Brunt 6923403e56bSAlex Van Brunt if (young) { 6933403e56bSAlex Van Brunt /* 6943403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 6953403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 6963403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 6973403e56bSAlex Van Brunt * window for such an event is bounded by the next 6983403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 6993403e56bSAlex Van Brunt * invalidation. 7003403e56bSAlex Van Brunt */ 7013403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 7023403e56bSAlex Van Brunt } 7033403e56bSAlex Van Brunt 7043403e56bSAlex Van Brunt return young; 7053403e56bSAlex Van Brunt } 7063403e56bSAlex Van Brunt 7072f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7082f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7092f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7102f4b829cSCatalin Marinas unsigned long address, 7112f4b829cSCatalin Marinas pmd_t *pmdp) 7122f4b829cSCatalin Marinas { 7132f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7142f4b829cSCatalin Marinas } 7152f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7162f4b829cSCatalin Marinas 7172f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 7182f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 7192f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 7202f4b829cSCatalin Marinas { 7213bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 7222f4b829cSCatalin Marinas } 7232f4b829cSCatalin Marinas 7242f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 725911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 726911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 7272f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7282f4b829cSCatalin Marinas { 7292f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 7302f4b829cSCatalin Marinas } 7312f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7322f4b829cSCatalin Marinas 7332f4b829cSCatalin Marinas /* 7348781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 7358781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 7362f4b829cSCatalin Marinas */ 7372f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 7382f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 7392f4b829cSCatalin Marinas { 7403bbf7157SCatalin Marinas pte_t old_pte, pte; 7412f4b829cSCatalin Marinas 7423bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7433bbf7157SCatalin Marinas do { 7443bbf7157SCatalin Marinas old_pte = pte; 7458781bcbcSSteve Capper /* 7468781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 7478781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 7488781bcbcSSteve Capper */ 7498781bcbcSSteve Capper if (pte_hw_dirty(pte)) 7508781bcbcSSteve Capper pte = pte_mkdirty(pte); 7513bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 7523bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7533bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7543bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7552f4b829cSCatalin Marinas } 7562f4b829cSCatalin Marinas 7572f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7582f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 7592f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 7602f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7612f4b829cSCatalin Marinas { 7622f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 7632f4b829cSCatalin Marinas } 7641d78a62cSCatalin Marinas 7651d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 7661d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 7671d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 7681d78a62cSCatalin Marinas { 7691d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 7701d78a62cSCatalin Marinas } 7712f4b829cSCatalin Marinas #endif 7722f4b829cSCatalin Marinas 7734f04d8f0SCatalin Marinas /* 7744f04d8f0SCatalin Marinas * Encode and decode a swap entry: 7753676f9efSCatalin Marinas * bits 0-1: present (must be zero) 7769b3e661eSKirill A. Shutemov * bits 2-7: swap type 7779b3e661eSKirill A. Shutemov * bits 8-57: swap offset 778fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 7794f04d8f0SCatalin Marinas */ 7809b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 7814f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 7829b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 7834f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 7844f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 7853676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 7864f04d8f0SCatalin Marinas 7874f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 7883676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 7894f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 7904f04d8f0SCatalin Marinas 7914f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 7924f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 7934f04d8f0SCatalin Marinas 7944f04d8f0SCatalin Marinas /* 7954f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 796aad9061bSGeert Uytterhoeven * PTEs. 7974f04d8f0SCatalin Marinas */ 7984f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 7994f04d8f0SCatalin Marinas 8004f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8014f04d8f0SCatalin Marinas 8024f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 8034f04d8f0SCatalin Marinas 80439b5be9bSWill Deacon void pgd_cache_init(void); 80539b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 8064f04d8f0SCatalin Marinas 807cba3574fSWill Deacon /* 808cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 809cba3574fSWill Deacon */ 810cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 811cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 812cba3574fSWill Deacon { 813cba3574fSWill Deacon /* 814120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 815120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 816120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 817cba3574fSWill Deacon */ 818cba3574fSWill Deacon } 819cba3574fSWill Deacon 820cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 821cba3574fSWill Deacon 82203875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 82303875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 8247db743c6SCatalin Marinas 825529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 826529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 827529c4b05SKristina Martsenko #else 828529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 829529c4b05SKristina Martsenko #endif 830529c4b05SKristina Martsenko 8314f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 8324f04d8f0SCatalin Marinas 8334f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 834