1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 1234bfeea4SCatalin Marinas #include <asm/mte.h> 134f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 143eca86e7SMark Rutland #include <asm/pgtable-prot.h> 153403e56bSAlex Van Brunt #include <asm/tlbflush.h> 164f04d8f0SCatalin Marinas 174f04d8f0SCatalin Marinas /* 183e1907d5SArd Biesheuvel * VMALLOC range. 1908375198SCatalin Marinas * 20f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 21a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 223e1907d5SArd Biesheuvel * and fixed mappings 234f04d8f0SCatalin Marinas */ 24f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 25*b730b0f2SArd Biesheuvel #define VMALLOC_END (VMEMMAP_START - SZ_8M) 264f04d8f0SCatalin Marinas 277bc1a0f9SArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 287bc1a0f9SArd Biesheuvel 294f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 302f4b829cSCatalin Marinas 313bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 32961faac1SMark Rutland #include <asm/fixmap.h> 332f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3486c9e812SWill Deacon #include <linux/mm_types.h> 3586c9e812SWill Deacon #include <linux/sched.h> 3642b25471SKefeng Wang #include <linux/page_table_check.h> 372f4b829cSCatalin Marinas 38a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 39a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 40a7ac1cfaSZhenyu Ye 41a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 42a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 43a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 44a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 45a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 46a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 47a7ac1cfaSZhenyu Ye 48d0637c50SBarry Song static inline bool arch_thp_swp_supported(void) 49d0637c50SBarry Song { 50d0637c50SBarry Song return !system_supports_mte(); 51d0637c50SBarry Song } 52d0637c50SBarry Song #define arch_thp_swp_supported arch_thp_swp_supported 53d0637c50SBarry Song 544f04d8f0SCatalin Marinas /* 556a1bdb17SWill Deacon * Outside of a few very special situations (e.g. hibernation), we always 566a1bdb17SWill Deacon * use broadcast TLB invalidation instructions, therefore a spurious page 576a1bdb17SWill Deacon * fault on one CPU which has been handled concurrently by another CPU 586a1bdb17SWill Deacon * does not need to perform additional invalidation. 596a1bdb17SWill Deacon */ 6099c29133SGerald Schaefer #define flush_tlb_fix_spurious_fault(vma, address, ptep) do { } while (0) 616a1bdb17SWill Deacon 626a1bdb17SWill Deacon /* 634f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 644f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 654f04d8f0SCatalin Marinas */ 665227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 672077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 684f04d8f0SCatalin Marinas 692cf660ebSGavin Shan #define pte_ERROR(e) \ 702cf660ebSGavin Shan pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e)) 717078db46SCatalin Marinas 7275387b92SKristina Martsenko /* 7375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 7475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 7575387b92SKristina Martsenko */ 7675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 77c7c386fbSArnd Bergmann static inline phys_addr_t __pte_to_phys(pte_t pte) 78c7c386fbSArnd Bergmann { 79c7c386fbSArnd Bergmann return (pte_val(pte) & PTE_ADDR_LOW) | 80a4ee2861SAnshuman Khandual ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); 81c7c386fbSArnd Bergmann } 82c7c386fbSArnd Bergmann static inline pteval_t __phys_to_pte_val(phys_addr_t phys) 83c7c386fbSArnd Bergmann { 84a4ee2861SAnshuman Khandual return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK; 85c7c386fbSArnd Bergmann } 8675387b92SKristina Martsenko #else 8775387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 8875387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 8975387b92SKristina Martsenko #endif 904f04d8f0SCatalin Marinas 9175387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 9275387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 9375387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 944f04d8f0SCatalin Marinas 954f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 964f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 974f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 987078db46SCatalin Marinas 994f04d8f0SCatalin Marinas /* 1004f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 1014f04d8f0SCatalin Marinas */ 10284fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 10384fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 10484fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 10584fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 106d0ba9612SAnshuman Khandual #define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) 10742b25471SKefeng Wang #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) 108ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 10993ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 11073b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 11134bfeea4SCatalin Marinas #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \ 11234bfeea4SCatalin Marinas PTE_ATTRINDX(MT_NORMAL_TAGGED)) 1134f04d8f0SCatalin Marinas 114d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 115d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 116d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 117d27cfa1fSArd Biesheuvel }) 118d27cfa1fSArd Biesheuvel 119d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 120d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 121d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 122d27cfa1fSArd Biesheuvel }) 123d27cfa1fSArd Biesheuvel 124d0ba9612SAnshuman Khandual #define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) 1252f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1262f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1272f4b829cSCatalin Marinas 128766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 12918107f8aSVladimir Murzin /* 13018107f8aSVladimir Murzin * Execute-only user mappings do not have the PTE_USER bit set. All valid 13118107f8aSVladimir Murzin * kernel mappings have the PTE_UXN bit set. 13218107f8aSVladimir Murzin */ 133ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 13418107f8aSVladimir Murzin ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 13576c714beSWill Deacon /* 13676c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 13776c714beSWill Deacon * so that we don't erroneously return false for pages that have been 13876c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 13907509e10SWill Deacon * Note that we can't make any assumptions based on the state of the access 14007509e10SWill Deacon * flag, since ptep_clear_flush_young() elides a DSB when invalidating the 14107509e10SWill Deacon * TLB. 14276c714beSWill Deacon */ 14376c714beSWill Deacon #define pte_accessible(mm, pte) \ 14407509e10SWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte)) 1454f04d8f0SCatalin Marinas 1466218f96cSCatalin Marinas /* 14718107f8aSVladimir Murzin * p??_access_permitted() is true for valid user mappings (PTE_USER 14818107f8aSVladimir Murzin * bit set, subject to the write permission check). For execute-only 14918107f8aSVladimir Murzin * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits 15018107f8aSVladimir Murzin * not set) must return false. PROT_NONE mappings do not have the 15118107f8aSVladimir Murzin * PTE_VALID bit set. 1526218f96cSCatalin Marinas */ 1536218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 15418107f8aSVladimir Murzin (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte))) 1556218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1566218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1576218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1586218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1596218f96cSCatalin Marinas 160b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 161b6d4f280SLaura Abbott { 162b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 163b6d4f280SLaura Abbott return pte; 164b6d4f280SLaura Abbott } 165b6d4f280SLaura Abbott 166b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 167b6d4f280SLaura Abbott { 168b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 169b6d4f280SLaura Abbott return pte; 170b6d4f280SLaura Abbott } 171b6d4f280SLaura Abbott 172b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 173b65399f6SAnshuman Khandual { 174b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 175b65399f6SAnshuman Khandual return pmd; 176b65399f6SAnshuman Khandual } 177b65399f6SAnshuman Khandual 178b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 179b65399f6SAnshuman Khandual { 180b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 181b65399f6SAnshuman Khandual return pmd; 182b65399f6SAnshuman Khandual } 183b65399f6SAnshuman Khandual 1842f0584f3SRick Edgecombe static inline pte_t pte_mkwrite_novma(pte_t pte) 18544b6dfc5SSteve Capper { 18673e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 18773e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 18873e86cb0SCatalin Marinas return pte; 18944b6dfc5SSteve Capper } 19044b6dfc5SSteve Capper 19144b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 19244b6dfc5SSteve Capper { 1938781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1948781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1958781bcbcSSteve Capper 1968781bcbcSSteve Capper return pte; 19744b6dfc5SSteve Capper } 19844b6dfc5SSteve Capper 19944b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 20044b6dfc5SSteve Capper { 2018781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 2028781bcbcSSteve Capper 2038781bcbcSSteve Capper if (pte_write(pte)) 2048781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 2058781bcbcSSteve Capper 2068781bcbcSSteve Capper return pte; 20744b6dfc5SSteve Capper } 20844b6dfc5SSteve Capper 209ff1712f9SWill Deacon static inline pte_t pte_wrprotect(pte_t pte) 210ff1712f9SWill Deacon { 211ff1712f9SWill Deacon /* 212ff1712f9SWill Deacon * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 213ff1712f9SWill Deacon * clear), set the PTE_DIRTY bit. 214ff1712f9SWill Deacon */ 215ff1712f9SWill Deacon if (pte_hw_dirty(pte)) 2166477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 217ff1712f9SWill Deacon 218ff1712f9SWill Deacon pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 219ff1712f9SWill Deacon pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 220ff1712f9SWill Deacon return pte; 221ff1712f9SWill Deacon } 222ff1712f9SWill Deacon 22344b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 22444b6dfc5SSteve Capper { 225b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 22644b6dfc5SSteve Capper } 22744b6dfc5SSteve Capper 22844b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 22944b6dfc5SSteve Capper { 230b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 23144b6dfc5SSteve Capper } 23244b6dfc5SSteve Capper 23344b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 23444b6dfc5SSteve Capper { 235b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 23644b6dfc5SSteve Capper } 2374f04d8f0SCatalin Marinas 23893ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 23993ef666aSJeremy Linton { 24066b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 24166b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 24293ef666aSJeremy Linton } 24393ef666aSJeremy Linton 24493ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 24593ef666aSJeremy Linton { 24693ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 24793ef666aSJeremy Linton } 24893ef666aSJeremy Linton 2495ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2505ebe3a44SJames Morse { 2515ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2525ebe3a44SJames Morse } 2535ebe3a44SJames Morse 25466b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 25566b3923aSDavid Woods { 25666b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 25766b3923aSDavid Woods } 25866b3923aSDavid Woods 25973b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 26073b20c84SRobin Murphy { 26130e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 26273b20c84SRobin Murphy } 26373b20c84SRobin Murphy 2644f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2654f04d8f0SCatalin Marinas { 26620a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2677f0b1bf0SCatalin Marinas 2687f0b1bf0SCatalin Marinas /* 2697f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2707f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2717f0b1bf0SCatalin Marinas */ 272d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2737f0b1bf0SCatalin Marinas dsb(ishst); 274d0b7a302SWill Deacon isb(); 275d0b7a302SWill Deacon } 2764f04d8f0SCatalin Marinas } 2774f04d8f0SCatalin Marinas 278907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 279004fc58fSAnshuman Khandual bool pgattr_change_is_safe(u64 old, u64 new); 2804f04d8f0SCatalin Marinas 2812f4b829cSCatalin Marinas /* 2822f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2832f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2842f4b829cSCatalin Marinas * 2852f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2862f4b829cSCatalin Marinas * 0 0 | 1 0 0 2872f4b829cSCatalin Marinas * 0 1 | 1 1 0 2882f4b829cSCatalin Marinas * 1 0 | 1 0 1 2892f4b829cSCatalin Marinas * 1 1 | 0 1 x 2902f4b829cSCatalin Marinas * 2912f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2922f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2932f4b829cSCatalin Marinas * 294b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2952f4b829cSCatalin Marinas */ 2969b604722SMark Rutland 297004fc58fSAnshuman Khandual static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep, 2989b604722SMark Rutland pte_t pte) 2994f04d8f0SCatalin Marinas { 30020a004e7SWill Deacon pte_t old_pte; 30120a004e7SWill Deacon 3029b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 3039b604722SMark Rutland return; 3049b604722SMark Rutland 3059b604722SMark Rutland old_pte = READ_ONCE(*ptep); 3069b604722SMark Rutland 3079b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 3089b604722SMark Rutland return; 3099b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 3109b604722SMark Rutland return; 31102522463SWill Deacon 3122f4b829cSCatalin Marinas /* 3139b604722SMark Rutland * Check for potential race with hardware updates of the pte 3149b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 3159b604722SMark Rutland * through an invalid entry). 3162f4b829cSCatalin Marinas */ 31782d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 31882d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 31920a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 32020a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 32182d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 32220a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 323004fc58fSAnshuman Khandual VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)), 324004fc58fSAnshuman Khandual "%s: unsafe attribute change: 0x%016llx -> 0x%016llx", 325004fc58fSAnshuman Khandual __func__, pte_val(old_pte), pte_val(pte)); 3262f4b829cSCatalin Marinas } 3272f4b829cSCatalin Marinas 3283425cec4SRyan Roberts static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) 3299b604722SMark Rutland { 3309b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 3319b604722SMark Rutland __sync_icache_dcache(pte); 3329b604722SMark Rutland 33369e3b846SSteven Price /* 33469e3b846SSteven Price * If the PTE would provide user space access to the tags associated 33569e3b846SSteven Price * with it then ensure that the MTE tags are synchronised. Although 33669e3b846SSteven Price * pte_access_permitted() returns false for exec only mappings, they 33769e3b846SSteven Price * don't expose tags (instruction fetches don't check tags). 33869e3b846SSteven Price */ 33969e3b846SSteven Price if (system_supports_mte() && pte_access_permitted(pte, false) && 340332c151cSPeter Collingbourne !pte_special(pte) && pte_tagged(pte)) 3413425cec4SRyan Roberts mte_sync_tags(pte, nr_pages); 3424f04d8f0SCatalin Marinas } 3434f04d8f0SCatalin Marinas 344dba2ff49SCatalin Marinas static inline void set_ptes(struct mm_struct *mm, 345dba2ff49SCatalin Marinas unsigned long __always_unused addr, 3464a169d61SMatthew Wilcox (Oracle) pte_t *ptep, pte_t pte, unsigned int nr) 34742b25471SKefeng Wang { 3484a169d61SMatthew Wilcox (Oracle) page_table_check_ptes_set(mm, ptep, pte, nr); 3493425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 3504a169d61SMatthew Wilcox (Oracle) 3514a169d61SMatthew Wilcox (Oracle) for (;;) { 3523425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 3533425cec4SRyan Roberts set_pte(ptep, pte); 3544a169d61SMatthew Wilcox (Oracle) if (--nr == 0) 3554a169d61SMatthew Wilcox (Oracle) break; 3564a169d61SMatthew Wilcox (Oracle) ptep++; 3574a169d61SMatthew Wilcox (Oracle) pte_val(pte) += PAGE_SIZE; 35842b25471SKefeng Wang } 3594a169d61SMatthew Wilcox (Oracle) } 3604a169d61SMatthew Wilcox (Oracle) #define set_ptes set_ptes 36142b25471SKefeng Wang 3624f04d8f0SCatalin Marinas /* 3634f04d8f0SCatalin Marinas * Huge pte definitions. 3644f04d8f0SCatalin Marinas */ 365084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 366084bd298SSteve Capper 367084bd298SSteve Capper /* 368084bd298SSteve Capper * Hugetlb definitions. 369084bd298SSteve Capper */ 37066b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 371084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 372084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 373084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 374084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3754f04d8f0SCatalin Marinas 37675387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 37775387b92SKristina Martsenko { 37875387b92SKristina Martsenko return __pte(pgd_val(pgd)); 37975387b92SKristina Martsenko } 38075387b92SKristina Martsenko 381e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 382e9f63768SMike Rapoport { 383e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 384e9f63768SMike Rapoport } 385e9f63768SMike Rapoport 38629e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 38729e56940SSteve Capper { 38829e56940SSteve Capper return __pte(pud_val(pud)); 38929e56940SSteve Capper } 39029e56940SSteve Capper 391eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 392eb3f0624SPunit Agrawal { 393eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 394eb3f0624SPunit Agrawal } 395eb3f0624SPunit Agrawal 39629e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 39729e56940SSteve Capper { 39829e56940SSteve Capper return __pmd(pud_val(pud)); 39929e56940SSteve Capper } 40029e56940SSteve Capper 4019c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 4029c7e535fSSteve Capper { 4039c7e535fSSteve Capper return __pte(pmd_val(pmd)); 4049c7e535fSSteve Capper } 405af074848SSteve Capper 4069c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 4079c7e535fSSteve Capper { 4089c7e535fSSteve Capper return __pmd(pte_val(pte)); 4099c7e535fSSteve Capper } 410af074848SSteve Capper 411f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 4128ce837ceSArd Biesheuvel { 413f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 414f7f0097aSAnshuman Khandual } 415f7f0097aSAnshuman Khandual 416f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 417f7f0097aSAnshuman Khandual { 418f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 4198ce837ceSArd Biesheuvel } 4208ce837ceSArd Biesheuvel 421570ef363SDavid Hildenbrand static inline pte_t pte_swp_mkexclusive(pte_t pte) 422570ef363SDavid Hildenbrand { 423570ef363SDavid Hildenbrand return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 424570ef363SDavid Hildenbrand } 425570ef363SDavid Hildenbrand 426570ef363SDavid Hildenbrand static inline int pte_swp_exclusive(pte_t pte) 427570ef363SDavid Hildenbrand { 428570ef363SDavid Hildenbrand return pte_val(pte) & PTE_SWP_EXCLUSIVE; 429570ef363SDavid Hildenbrand } 430570ef363SDavid Hildenbrand 431570ef363SDavid Hildenbrand static inline pte_t pte_swp_clear_exclusive(pte_t pte) 432570ef363SDavid Hildenbrand { 433570ef363SDavid Hildenbrand return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); 434570ef363SDavid Hildenbrand } 435570ef363SDavid Hildenbrand 436893dea9cSKefeng Wang /* 437893dea9cSKefeng Wang * Select all bits except the pfn 438893dea9cSKefeng Wang */ 439893dea9cSKefeng Wang static inline pgprot_t pte_pgprot(pte_t pte) 440893dea9cSKefeng Wang { 441893dea9cSKefeng Wang unsigned long pfn = pte_pfn(pte); 442893dea9cSKefeng Wang 443893dea9cSKefeng Wang return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); 444893dea9cSKefeng Wang } 445893dea9cSKefeng Wang 44656166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 44756166230SGanapatrao Kulkarni /* 448ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 44956166230SGanapatrao Kulkarni */ 45056166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 45156166230SGanapatrao Kulkarni { 45256166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 45356166230SGanapatrao Kulkarni } 45456166230SGanapatrao Kulkarni 45556166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 45656166230SGanapatrao Kulkarni { 45756166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 45856166230SGanapatrao Kulkarni } 45956166230SGanapatrao Kulkarni #endif 46056166230SGanapatrao Kulkarni 461b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 462b65399f6SAnshuman Khandual 463b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 464b65399f6SAnshuman Khandual { 465b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 466b65399f6SAnshuman Khandual } 467b65399f6SAnshuman Khandual 468af074848SSteve Capper /* 469af074848SSteve Capper * THP definitions. 470af074848SSteve Capper */ 471af074848SSteve Capper 472af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 473b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 474b65399f6SAnshuman Khandual { 475b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 476b65399f6SAnshuman Khandual } 47729e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 478af074848SSteve Capper 479c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 4809c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 4810795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 48242b25471SKefeng Wang #define pmd_user(pmd) pte_user(pmd_pte(pmd)) 48342b25471SKefeng Wang #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd)) 484d55863dbSPeter Zijlstra #define pmd_cont(pmd) pte_cont(pmd_pte(pmd)) 4859c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 4869c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 4872f0584f3SRick Edgecombe #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 48805ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 4899c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 4909c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 491b65399f6SAnshuman Khandual 492b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 493b65399f6SAnshuman Khandual { 494b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 495b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 496b65399f6SAnshuman Khandual 497b65399f6SAnshuman Khandual return pmd; 498b65399f6SAnshuman Khandual } 499af074848SSteve Capper 5000dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 5010dbd3b18SSuzuki K Poulose 5029c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 503af074848SSteve Capper 504af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 505af074848SSteve Capper 50673b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 50773b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 50873b20c84SRobin Murphy #endif 50930e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 51030e23538SJia He { 51130e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 51230e23538SJia He } 51373b20c84SRobin Murphy 51475387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 51575387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 51675387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 51775387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 518af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 519af074848SSteve Capper 52035a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 521eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 52229e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 52375387b92SKristina Martsenko 524b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 525b8e0ba7cSPunit Agrawal 52675387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 52775387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 52875387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 52975387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 530af074848SSteve Capper 531dba2ff49SCatalin Marinas static inline void __set_pte_at(struct mm_struct *mm, 532dba2ff49SCatalin Marinas unsigned long __always_unused addr, 5333425cec4SRyan Roberts pte_t *ptep, pte_t pte, unsigned int nr) 5343425cec4SRyan Roberts { 5353425cec4SRyan Roberts __sync_cache_and_tags(pte, nr); 5363425cec4SRyan Roberts __check_safe_pte_update(mm, ptep, pte); 5373425cec4SRyan Roberts set_pte(ptep, pte); 5383425cec4SRyan Roberts } 5393425cec4SRyan Roberts 54042b25471SKefeng Wang static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 54142b25471SKefeng Wang pmd_t *pmdp, pmd_t pmd) 54242b25471SKefeng Wang { 543a3b83713SKemeng Shi page_table_check_pmd_set(mm, pmdp, pmd); 5443425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), 5453425cec4SRyan Roberts PMD_SIZE >> PAGE_SHIFT); 54642b25471SKefeng Wang } 54742b25471SKefeng Wang 54842b25471SKefeng Wang static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, 54942b25471SKefeng Wang pud_t *pudp, pud_t pud) 55042b25471SKefeng Wang { 5516d144436SKemeng Shi page_table_check_pud_set(mm, pudp, pud); 5523425cec4SRyan Roberts return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud), 5533425cec4SRyan Roberts PUD_SIZE >> PAGE_SHIFT); 55442b25471SKefeng Wang } 555af074848SSteve Capper 556e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 557e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 558e9f63768SMike Rapoport 55975387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 56075387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 56175387b92SKristina Martsenko 562a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 563a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 564a501e324SCatalin Marinas 565cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 566034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 567cca98e9fSChristoph Hellwig 568af074848SSteve Capper /* 5694f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 5704f04d8f0SCatalin Marinas */ 5714f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 572de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 5734f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 574de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 575d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 576d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 577d15dfd31SCatalin Marinas #define pgprot_tagged(prot) \ 578d15dfd31SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED)) 579d15dfd31SCatalin Marinas #define pgprot_mhp pgprot_tagged 5803e4e1d3fSChristoph Hellwig /* 5813e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 5823e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 5833e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 5843e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 5853e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 5863e4e1d3fSChristoph Hellwig * endpoint. 5873e4e1d3fSChristoph Hellwig */ 588419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 589419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 590419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 591419e2f18SChristoph Hellwig 5924f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 5934f04d8f0SCatalin Marinas struct file; 5944f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 5954f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 5964f04d8f0SCatalin Marinas 5974f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 5984f04d8f0SCatalin Marinas 59936311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 60036311607SMarc Zyngier PMD_TYPE_TABLE) 60136311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 60236311607SMarc Zyngier PMD_TYPE_SECT) 60323bc8f69SMuchun Song #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd)) 604e377ab82SAnshuman Khandual #define pmd_bad(pmd) (!pmd_table(pmd)) 60536311607SMarc Zyngier 606d55863dbSPeter Zijlstra #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE) 607d55863dbSPeter Zijlstra #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE) 608d55863dbSPeter Zijlstra 609cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 6107d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 6117d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 612206a2a73SSteve Capper #else 613206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 614206a2a73SSteve Capper PUD_TYPE_SECT) 615523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 616523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 617206a2a73SSteve Capper #endif 61836311607SMarc Zyngier 6192330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 6202330b7caSJun Yao extern pgd_t init_pg_end[]; 6212330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 6222330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 6232330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 624833be850SMark Rutland extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; 6252330b7caSJun Yao 6262330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 6272330b7caSJun Yao 6282330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 6292330b7caSJun Yao { 6302330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 6312330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 6322330b7caSJun Yao } 6332330b7caSJun Yao 6344f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 6354f04d8f0SCatalin Marinas { 636e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 637e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 6382330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 6392330b7caSJun Yao return; 6402330b7caSJun Yao } 641e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 6422330b7caSJun Yao 64320a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 6440795edafSWill Deacon 645d0b7a302SWill Deacon if (pmd_valid(pmd)) { 64698f7685eSWill Deacon dsb(ishst); 647d0b7a302SWill Deacon isb(); 648d0b7a302SWill Deacon } 6494f04d8f0SCatalin Marinas } 6504f04d8f0SCatalin Marinas 6514f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 6524f04d8f0SCatalin Marinas { 6534f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 6544f04d8f0SCatalin Marinas } 6554f04d8f0SCatalin Marinas 656dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 6574f04d8f0SCatalin Marinas { 65875387b92SKristina Martsenko return __pmd_to_phys(pmd); 6594f04d8f0SCatalin Marinas } 6604f04d8f0SCatalin Marinas 661974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 662974b9b2cSMike Rapoport { 663974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 664974b9b2cSMike Rapoport } 66574dd022fSQian Cai 666053520f7SMark Rutland /* Find an entry in the third-level page table. */ 667f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 668053520f7SMark Rutland 669961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 670961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 671961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 672961faac1SMark Rutland 67368ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 6744f04d8f0SCatalin Marinas 6756533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6766533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 6776533945aSArd Biesheuvel 6784f04d8f0SCatalin Marinas /* 6794f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 6804f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 6814f04d8f0SCatalin Marinas */ 6824f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 6834f04d8f0SCatalin Marinas 6849f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 6854f04d8f0SCatalin Marinas 6862cf660ebSGavin Shan #define pmd_ERROR(e) \ 6872cf660ebSGavin Shan pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e)) 6887078db46SCatalin Marinas 6894f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 690e377ab82SAnshuman Khandual #define pud_bad(pud) (!pud_table(pud)) 691f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 69223bc8f69SMuchun Song #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud)) 6930795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 69442b25471SKefeng Wang #define pud_user(pud) pte_user(pud_pte(pud)) 695730a11f9SLiu Shixin #define pud_user_exec(pud) pte_user_exec(pud_pte(pud)) 6964f04d8f0SCatalin Marinas 6974f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 6984f04d8f0SCatalin Marinas { 699e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 700e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 7012330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 7022330b7caSJun Yao return; 7032330b7caSJun Yao } 704e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 7052330b7caSJun Yao 70620a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 7070795edafSWill Deacon 708d0b7a302SWill Deacon if (pud_valid(pud)) { 70998f7685eSWill Deacon dsb(ishst); 710d0b7a302SWill Deacon isb(); 711d0b7a302SWill Deacon } 7124f04d8f0SCatalin Marinas } 7134f04d8f0SCatalin Marinas 7144f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 7154f04d8f0SCatalin Marinas { 7164f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 7174f04d8f0SCatalin Marinas } 7184f04d8f0SCatalin Marinas 719dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 7204f04d8f0SCatalin Marinas { 72175387b92SKristina Martsenko return __pud_to_phys(pud); 7224f04d8f0SCatalin Marinas } 7234f04d8f0SCatalin Marinas 7249cf6fa24SAneesh Kumar K.V static inline pmd_t *pud_pgtable(pud_t pud) 725974b9b2cSMike Rapoport { 7269cf6fa24SAneesh Kumar K.V return (pmd_t *)__va(pud_page_paddr(pud)); 727974b9b2cSMike Rapoport } 7287078db46SCatalin Marinas 729974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 73020a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 7317078db46SCatalin Marinas 732961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 733961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 734961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 7354f04d8f0SCatalin Marinas 73668ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 73729e56940SSteve Capper 7386533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 7396533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 7406533945aSArd Biesheuvel 741dca56dcaSMark Rutland #else 742dca56dcaSMark Rutland 743dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 7444e4ff23aSWill Deacon #define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */ 745dca56dcaSMark Rutland 746961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 747961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 748961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 749961faac1SMark Rutland #define pmd_clear_fixmap() 750961faac1SMark Rutland 7516533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 7526533945aSArd Biesheuvel 7539f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 7544f04d8f0SCatalin Marinas 7559f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 756c79b954bSJungseok Lee 7572cf660ebSGavin Shan #define pud_ERROR(e) \ 7582cf660ebSGavin Shan pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e)) 7597078db46SCatalin Marinas 760e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 761e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 762e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 763c79b954bSJungseok Lee 764e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 765c79b954bSJungseok Lee { 766e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 767e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 7682330b7caSJun Yao return; 7692330b7caSJun Yao } 7702330b7caSJun Yao 771e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 772c79b954bSJungseok Lee dsb(ishst); 773eb6a4dccSWill Deacon isb(); 774c79b954bSJungseok Lee } 775c79b954bSJungseok Lee 776e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 777c79b954bSJungseok Lee { 778e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 779c79b954bSJungseok Lee } 780c79b954bSJungseok Lee 781e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 782c79b954bSJungseok Lee { 783e9f63768SMike Rapoport return __p4d_to_phys(p4d); 784c79b954bSJungseok Lee } 785c79b954bSJungseok Lee 786dc4875f0SAneesh Kumar K.V static inline pud_t *p4d_pgtable(p4d_t p4d) 787974b9b2cSMike Rapoport { 788dc4875f0SAneesh Kumar K.V return (pud_t *)__va(p4d_page_paddr(p4d)); 789974b9b2cSMike Rapoport } 7907078db46SCatalin Marinas 7915845e703SXujun Leng /* Find an entry in the first-level page table. */ 792e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 7937078db46SCatalin Marinas 794961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 795e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 796961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 797c79b954bSJungseok Lee 798e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 7995d96e0cbSJungseok Lee 8006533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 8016533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 8026533945aSArd Biesheuvel 803dca56dcaSMark Rutland #else 804dca56dcaSMark Rutland 805e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 806dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 807dca56dcaSMark Rutland 808961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 809961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 810961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 811961faac1SMark Rutland #define pud_clear_fixmap() 812961faac1SMark Rutland 8136533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 8146533945aSArd Biesheuvel 8159f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 816c79b954bSJungseok Lee 8172cf660ebSGavin Shan #define pgd_ERROR(e) \ 8182cf660ebSGavin Shan pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e)) 8197078db46SCatalin Marinas 820961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 821961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 822961faac1SMark Rutland 8234f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 8244f04d8f0SCatalin Marinas { 8259f341931SCatalin Marinas /* 8269f341931SCatalin Marinas * Normal and Normal-Tagged are two different memory types and indices 8279f341931SCatalin Marinas * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK. 8289f341931SCatalin Marinas */ 829a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 8309f341931SCatalin Marinas PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | 8319f341931SCatalin Marinas PTE_ATTRINDX_MASK; 8322f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 8332f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 8346477c388SAnshuman Khandual pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 8356477c388SAnshuman Khandual 8364f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 8373c069607SJames Houghton /* 8383c069607SJames Houghton * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware 8393c069607SJames Houghton * dirtiness again. 8403c069607SJames Houghton */ 8413c069607SJames Houghton if (pte_sw_dirty(pte)) 8423c069607SJames Houghton pte = pte_mkdirty(pte); 8434f04d8f0SCatalin Marinas return pte; 8444f04d8f0SCatalin Marinas } 8454f04d8f0SCatalin Marinas 8469c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 8479c7e535fSSteve Capper { 8489c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 8499c7e535fSSteve Capper } 8509c7e535fSSteve Capper 85166dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 85266dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 85366dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 85466dbd6e6SCatalin Marinas pte_t entry, int dirty); 85566dbd6e6SCatalin Marinas 856282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 857282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 858282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 859282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 860282aa705SCatalin Marinas pmd_t entry, int dirty) 861282aa705SCatalin Marinas { 862282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 863282aa705SCatalin Marinas } 86473b20c84SRobin Murphy 86573b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 86673b20c84SRobin Murphy { 86773b20c84SRobin Murphy return 0; 86873b20c84SRobin Murphy } 86973b20c84SRobin Murphy 87073b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 87173b20c84SRobin Murphy { 87273b20c84SRobin Murphy return 0; 87373b20c84SRobin Murphy } 874282aa705SCatalin Marinas #endif 875282aa705SCatalin Marinas 876ed928a34STong Tiangen #ifdef CONFIG_PAGE_TABLE_CHECK 877ed928a34STong Tiangen static inline bool pte_user_accessible_page(pte_t pte) 878ed928a34STong Tiangen { 879ed928a34STong Tiangen return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte)); 880ed928a34STong Tiangen } 881ed928a34STong Tiangen 882ed928a34STong Tiangen static inline bool pmd_user_accessible_page(pmd_t pmd) 883ed928a34STong Tiangen { 88474c2f810SLiu Shixin return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd)); 885ed928a34STong Tiangen } 886ed928a34STong Tiangen 887ed928a34STong Tiangen static inline bool pud_user_accessible_page(pud_t pud) 888ed928a34STong Tiangen { 889730a11f9SLiu Shixin return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud)); 890ed928a34STong Tiangen } 891ed928a34STong Tiangen #endif 892ed928a34STong Tiangen 8932f4b829cSCatalin Marinas /* 8942f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 8952f4b829cSCatalin Marinas */ 8962f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 89706485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 8982f4b829cSCatalin Marinas { 8993bbf7157SCatalin Marinas pte_t old_pte, pte; 9002f4b829cSCatalin Marinas 9013bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 9023bbf7157SCatalin Marinas do { 9033bbf7157SCatalin Marinas old_pte = pte; 9043bbf7157SCatalin Marinas pte = pte_mkold(pte); 9053bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 9063bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 9073bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 9082f4b829cSCatalin Marinas 9093bbf7157SCatalin Marinas return pte_young(pte); 9102f4b829cSCatalin Marinas } 9112f4b829cSCatalin Marinas 91206485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 91306485053SCatalin Marinas unsigned long address, 91406485053SCatalin Marinas pte_t *ptep) 91506485053SCatalin Marinas { 91606485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 91706485053SCatalin Marinas } 91806485053SCatalin Marinas 9193403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 9203403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 9213403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 9223403e56bSAlex Van Brunt { 9233403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 9243403e56bSAlex Van Brunt 9253403e56bSAlex Van Brunt if (young) { 9263403e56bSAlex Van Brunt /* 9273403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 9283403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 9293403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 9303403e56bSAlex Van Brunt * window for such an event is bounded by the next 9313403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 9323403e56bSAlex Van Brunt * invalidation. 9333403e56bSAlex Van Brunt */ 9343403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 9353403e56bSAlex Van Brunt } 9363403e56bSAlex Van Brunt 9373403e56bSAlex Van Brunt return young; 9383403e56bSAlex Van Brunt } 9393403e56bSAlex Van Brunt 9402f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 9412f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 9422f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 9432f4b829cSCatalin Marinas unsigned long address, 9442f4b829cSCatalin Marinas pmd_t *pmdp) 9452f4b829cSCatalin Marinas { 9462f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 9472f4b829cSCatalin Marinas } 9482f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 9492f4b829cSCatalin Marinas 9502f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 9512f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 9522f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 9532f4b829cSCatalin Marinas { 95442b25471SKefeng Wang pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0)); 95542b25471SKefeng Wang 956aa232204SKemeng Shi page_table_check_pte_clear(mm, pte); 95742b25471SKefeng Wang 95842b25471SKefeng Wang return pte; 9592f4b829cSCatalin Marinas } 9602f4b829cSCatalin Marinas 9612f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 962911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 963911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 9642f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 9652f4b829cSCatalin Marinas { 96642b25471SKefeng Wang pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0)); 96742b25471SKefeng Wang 9681831414cSKemeng Shi page_table_check_pmd_clear(mm, pmd); 96942b25471SKefeng Wang 97042b25471SKefeng Wang return pmd; 9712f4b829cSCatalin Marinas } 9722f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 9732f4b829cSCatalin Marinas 9742f4b829cSCatalin Marinas /* 9758781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 9768781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 9772f4b829cSCatalin Marinas */ 9782f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 9792f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 9802f4b829cSCatalin Marinas { 9813bbf7157SCatalin Marinas pte_t old_pte, pte; 9822f4b829cSCatalin Marinas 9833bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 9843bbf7157SCatalin Marinas do { 9853bbf7157SCatalin Marinas old_pte = pte; 9863bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 9873bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 9883bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 9893bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 9902f4b829cSCatalin Marinas } 9912f4b829cSCatalin Marinas 9922f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 9932f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 9942f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 9952f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 9962f4b829cSCatalin Marinas { 9972f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 9982f4b829cSCatalin Marinas } 9991d78a62cSCatalin Marinas 10001d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 10011d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 10021d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 10031d78a62cSCatalin Marinas { 1004a3b83713SKemeng Shi page_table_check_pmd_set(vma->vm_mm, pmdp, pmd); 10051d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 10061d78a62cSCatalin Marinas } 10072f4b829cSCatalin Marinas #endif 10082f4b829cSCatalin Marinas 10094f04d8f0SCatalin Marinas /* 10104f04d8f0SCatalin Marinas * Encode and decode a swap entry: 10113676f9efSCatalin Marinas * bits 0-1: present (must be zero) 1012570ef363SDavid Hildenbrand * bits 2: remember PG_anon_exclusive 1013570ef363SDavid Hildenbrand * bits 3-7: swap type 10149b3e661eSKirill A. Shutemov * bits 8-57: swap offset 1015fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 10164f04d8f0SCatalin Marinas */ 1017570ef363SDavid Hildenbrand #define __SWP_TYPE_SHIFT 3 1018570ef363SDavid Hildenbrand #define __SWP_TYPE_BITS 5 10199b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 10204f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 10214f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 10223676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 10234f04d8f0SCatalin Marinas 10244f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 10253676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 10264f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 10274f04d8f0SCatalin Marinas 10284f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 10294f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 10304f04d8f0SCatalin Marinas 103153fa117bSAnshuman Khandual #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 103253fa117bSAnshuman Khandual #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) }) 103353fa117bSAnshuman Khandual #define __swp_entry_to_pmd(swp) __pmd((swp).val) 103453fa117bSAnshuman Khandual #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ 103553fa117bSAnshuman Khandual 10364f04d8f0SCatalin Marinas /* 10374f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 1038aad9061bSGeert Uytterhoeven * PTEs. 10394f04d8f0SCatalin Marinas */ 10404f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 10414f04d8f0SCatalin Marinas 104236943abaSSteven Price #ifdef CONFIG_ARM64_MTE 104336943abaSSteven Price 104436943abaSSteven Price #define __HAVE_ARCH_PREPARE_TO_SWAP 104536943abaSSteven Price static inline int arch_prepare_to_swap(struct page *page) 104636943abaSSteven Price { 104736943abaSSteven Price if (system_supports_mte()) 104836943abaSSteven Price return mte_save_tags(page); 104936943abaSSteven Price return 0; 105036943abaSSteven Price } 105136943abaSSteven Price 105236943abaSSteven Price #define __HAVE_ARCH_SWAP_INVALIDATE 105336943abaSSteven Price static inline void arch_swap_invalidate_page(int type, pgoff_t offset) 105436943abaSSteven Price { 105536943abaSSteven Price if (system_supports_mte()) 105636943abaSSteven Price mte_invalidate_tags(type, offset); 105736943abaSSteven Price } 105836943abaSSteven Price 105936943abaSSteven Price static inline void arch_swap_invalidate_area(int type) 106036943abaSSteven Price { 106136943abaSSteven Price if (system_supports_mte()) 106236943abaSSteven Price mte_invalidate_tags_area(type); 106336943abaSSteven Price } 106436943abaSSteven Price 106536943abaSSteven Price #define __HAVE_ARCH_SWAP_RESTORE 1066da08e9b7SMatthew Wilcox (Oracle) static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) 106736943abaSSteven Price { 1068d77e59a8SCatalin Marinas if (system_supports_mte()) 1069d77e59a8SCatalin Marinas mte_restore_tags(entry, &folio->page); 107036943abaSSteven Price } 107136943abaSSteven Price 107236943abaSSteven Price #endif /* CONFIG_ARM64_MTE */ 107336943abaSSteven Price 1074cba3574fSWill Deacon /* 1075cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 1076cba3574fSWill Deacon */ 10774a169d61SMatthew Wilcox (Oracle) static inline void update_mmu_cache_range(struct vm_fault *vmf, 10784a169d61SMatthew Wilcox (Oracle) struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, 10794a169d61SMatthew Wilcox (Oracle) unsigned int nr) 1080cba3574fSWill Deacon { 1081cba3574fSWill Deacon /* 1082120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 1083120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 1084120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 1085cba3574fSWill Deacon */ 1086cba3574fSWill Deacon } 1087cba3574fSWill Deacon 10884a169d61SMatthew Wilcox (Oracle) #define update_mmu_cache(vma, addr, ptep) \ 10894a169d61SMatthew Wilcox (Oracle) update_mmu_cache_range(NULL, vma, addr, ptep, 1) 1090cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 1091cba3574fSWill Deacon 1092529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 1093529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 1094529c4b05SKristina Martsenko #else 1095529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 1096529c4b05SKristina Martsenko #endif 1097529c4b05SKristina Martsenko 10986af31226SJia He /* 10996af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 11006af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 11016af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 11026af31226SJia He * hardware-managed access flag on arm64. 11036af31226SJia He */ 1104e1fd09e3SYu Zhao #define arch_has_hw_pte_young cpu_has_hw_af 11050388f9c7SWill Deacon 11060388f9c7SWill Deacon /* 11070388f9c7SWill Deacon * Experimentally, it's cheap to set the access flag in hardware and we 11080388f9c7SWill Deacon * benefit from prefaulting mappings as 'old' to start with. 11090388f9c7SWill Deacon */ 1110e1fd09e3SYu Zhao #define arch_wants_old_prefaulted_pte cpu_has_hw_af 11116af31226SJia He 1112f8b46c4bSAnshuman Khandual static inline bool pud_sect_supported(void) 1113f8b46c4bSAnshuman Khandual { 1114f8b46c4bSAnshuman Khandual return PAGE_SIZE == SZ_4K; 1115f8b46c4bSAnshuman Khandual } 1116f8b46c4bSAnshuman Khandual 111718107f8aSVladimir Murzin 11185db568e7SAnshuman Khandual #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 11195db568e7SAnshuman Khandual #define ptep_modify_prot_start ptep_modify_prot_start 11205db568e7SAnshuman Khandual extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma, 11215db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep); 11225db568e7SAnshuman Khandual 11235db568e7SAnshuman Khandual #define ptep_modify_prot_commit ptep_modify_prot_commit 11245db568e7SAnshuman Khandual extern void ptep_modify_prot_commit(struct vm_area_struct *vma, 11255db568e7SAnshuman Khandual unsigned long addr, pte_t *ptep, 11265db568e7SAnshuman Khandual pte_t old_pte, pte_t new_pte); 11274f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 11284f04d8f0SCatalin Marinas 11294f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 1130