1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 124f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 133eca86e7SMark Rutland #include <asm/pgtable-prot.h> 143403e56bSAlex Van Brunt #include <asm/tlbflush.h> 154f04d8f0SCatalin Marinas 164f04d8f0SCatalin Marinas /* 173e1907d5SArd Biesheuvel * VMALLOC range. 1808375198SCatalin Marinas * 19f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 20a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 213e1907d5SArd Biesheuvel * and fixed mappings 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2414c127c9SSteve Capper #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 254f04d8f0SCatalin Marinas 26d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 274f04d8f0SCatalin Marinas 284f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 292f4b829cSCatalin Marinas 303bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 31961faac1SMark Rutland #include <asm/fixmap.h> 322f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3386c9e812SWill Deacon #include <linux/mm_types.h> 3486c9e812SWill Deacon #include <linux/sched.h> 352f4b829cSCatalin Marinas 36c8b6d2ccSSteve Capper extern struct page *vmemmap; 37c8b6d2ccSSteve Capper 384f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 394f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 40c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 414f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 424f04d8f0SCatalin Marinas 43a7ac1cfaSZhenyu Ye #ifdef CONFIG_TRANSPARENT_HUGEPAGE 44a7ac1cfaSZhenyu Ye #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE 45a7ac1cfaSZhenyu Ye 46a7ac1cfaSZhenyu Ye /* Set stride and tlb_level in flush_*_tlb_range */ 47a7ac1cfaSZhenyu Ye #define flush_pmd_tlb_range(vma, addr, end) \ 48a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2) 49a7ac1cfaSZhenyu Ye #define flush_pud_tlb_range(vma, addr, end) \ 50a7ac1cfaSZhenyu Ye __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) 51a7ac1cfaSZhenyu Ye #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 52a7ac1cfaSZhenyu Ye 534f04d8f0SCatalin Marinas /* 544f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 554f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 564f04d8f0SCatalin Marinas */ 575227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 582077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 594f04d8f0SCatalin Marinas 607078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 617078db46SCatalin Marinas 6275387b92SKristina Martsenko /* 6375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 6475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 6575387b92SKristina Martsenko */ 6675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 6775387b92SKristina Martsenko #define __pte_to_phys(pte) \ 6875387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 6975387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 7075387b92SKristina Martsenko #else 7175387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 7275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 7375387b92SKristina Martsenko #endif 744f04d8f0SCatalin Marinas 7575387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 7675387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 7775387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 784f04d8f0SCatalin Marinas 794f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 804f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 814f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 827078db46SCatalin Marinas 834f04d8f0SCatalin Marinas /* 844f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 854f04d8f0SCatalin Marinas */ 8684fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 8784fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 8884fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 8984fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 90ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 9193ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 9273b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 934f04d8f0SCatalin Marinas 94d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 95d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 96d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 97d27cfa1fSArd Biesheuvel }) 98d27cfa1fSArd Biesheuvel 99d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 100d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 101d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 102d27cfa1fSArd Biesheuvel }) 103d27cfa1fSArd Biesheuvel 104b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 1052f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 1062f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 1072f4b829cSCatalin Marinas 108766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 109ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 11024cecc37SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 11176c714beSWill Deacon #define pte_valid_young(pte) \ 11276c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1136218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1146218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 11576c714beSWill Deacon 11676c714beSWill Deacon /* 11776c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 11876c714beSWill Deacon * so that we don't erroneously return false for pages that have been 11976c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 12076c714beSWill Deacon */ 12176c714beSWill Deacon #define pte_accessible(mm, pte) \ 12276c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1234f04d8f0SCatalin Marinas 1246218f96cSCatalin Marinas /* 1256218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 12624cecc37SCatalin Marinas * write permission check). PROT_NONE mappings do not have the PTE_VALID bit 12724cecc37SCatalin Marinas * set. 1286218f96cSCatalin Marinas */ 1296218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1306218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1316218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1326218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1336218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1346218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1356218f96cSCatalin Marinas 136b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 137b6d4f280SLaura Abbott { 138b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 139b6d4f280SLaura Abbott return pte; 140b6d4f280SLaura Abbott } 141b6d4f280SLaura Abbott 142b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 143b6d4f280SLaura Abbott { 144b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 145b6d4f280SLaura Abbott return pte; 146b6d4f280SLaura Abbott } 147b6d4f280SLaura Abbott 148*b65399f6SAnshuman Khandual static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot) 149*b65399f6SAnshuman Khandual { 150*b65399f6SAnshuman Khandual pmd_val(pmd) &= ~pgprot_val(prot); 151*b65399f6SAnshuman Khandual return pmd; 152*b65399f6SAnshuman Khandual } 153*b65399f6SAnshuman Khandual 154*b65399f6SAnshuman Khandual static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) 155*b65399f6SAnshuman Khandual { 156*b65399f6SAnshuman Khandual pmd_val(pmd) |= pgprot_val(prot); 157*b65399f6SAnshuman Khandual return pmd; 158*b65399f6SAnshuman Khandual } 159*b65399f6SAnshuman Khandual 16044b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 16144b6dfc5SSteve Capper { 16273e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 16373e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 16473e86cb0SCatalin Marinas return pte; 16544b6dfc5SSteve Capper } 1664f04d8f0SCatalin Marinas 16744b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 16844b6dfc5SSteve Capper { 16973e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 17073e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 17173e86cb0SCatalin Marinas return pte; 17244b6dfc5SSteve Capper } 17344b6dfc5SSteve Capper 17444b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 17544b6dfc5SSteve Capper { 1768781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1778781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1788781bcbcSSteve Capper 1798781bcbcSSteve Capper return pte; 18044b6dfc5SSteve Capper } 18144b6dfc5SSteve Capper 18244b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 18344b6dfc5SSteve Capper { 1848781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1858781bcbcSSteve Capper 1868781bcbcSSteve Capper if (pte_write(pte)) 1878781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1888781bcbcSSteve Capper 1898781bcbcSSteve Capper return pte; 19044b6dfc5SSteve Capper } 19144b6dfc5SSteve Capper 19244b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 19344b6dfc5SSteve Capper { 194b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 19544b6dfc5SSteve Capper } 19644b6dfc5SSteve Capper 19744b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 19844b6dfc5SSteve Capper { 199b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 20044b6dfc5SSteve Capper } 20144b6dfc5SSteve Capper 20244b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 20344b6dfc5SSteve Capper { 204b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 20544b6dfc5SSteve Capper } 2064f04d8f0SCatalin Marinas 20793ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 20893ef666aSJeremy Linton { 20966b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 21066b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 21193ef666aSJeremy Linton } 21293ef666aSJeremy Linton 21393ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 21493ef666aSJeremy Linton { 21593ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 21693ef666aSJeremy Linton } 21793ef666aSJeremy Linton 2185ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 2195ebe3a44SJames Morse { 2205ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 2215ebe3a44SJames Morse } 2225ebe3a44SJames Morse 22366b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 22466b3923aSDavid Woods { 22566b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 22666b3923aSDavid Woods } 22766b3923aSDavid Woods 22873b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 22973b20c84SRobin Murphy { 23030e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 23173b20c84SRobin Murphy } 23273b20c84SRobin Murphy 2334f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2344f04d8f0SCatalin Marinas { 23520a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2367f0b1bf0SCatalin Marinas 2377f0b1bf0SCatalin Marinas /* 2387f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2397f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2407f0b1bf0SCatalin Marinas */ 241d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2427f0b1bf0SCatalin Marinas dsb(ishst); 243d0b7a302SWill Deacon isb(); 244d0b7a302SWill Deacon } 2454f04d8f0SCatalin Marinas } 2464f04d8f0SCatalin Marinas 247907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2484f04d8f0SCatalin Marinas 2492f4b829cSCatalin Marinas /* 2502f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2512f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2522f4b829cSCatalin Marinas * 2532f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2542f4b829cSCatalin Marinas * 0 0 | 1 0 0 2552f4b829cSCatalin Marinas * 0 1 | 1 1 0 2562f4b829cSCatalin Marinas * 1 0 | 1 0 1 2572f4b829cSCatalin Marinas * 1 1 | 0 1 x 2582f4b829cSCatalin Marinas * 2592f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2602f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2612f4b829cSCatalin Marinas * 262b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2632f4b829cSCatalin Marinas */ 2649b604722SMark Rutland 2659b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2669b604722SMark Rutland pte_t pte) 2674f04d8f0SCatalin Marinas { 26820a004e7SWill Deacon pte_t old_pte; 26920a004e7SWill Deacon 2709b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2719b604722SMark Rutland return; 2729b604722SMark Rutland 2739b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2749b604722SMark Rutland 2759b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2769b604722SMark Rutland return; 2779b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2789b604722SMark Rutland return; 27902522463SWill Deacon 2802f4b829cSCatalin Marinas /* 2819b604722SMark Rutland * Check for potential race with hardware updates of the pte 2829b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2839b604722SMark Rutland * through an invalid entry). 2842f4b829cSCatalin Marinas */ 28582d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 28682d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 28720a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 28820a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 28982d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 29020a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2912f4b829cSCatalin Marinas } 2922f4b829cSCatalin Marinas 2939b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2949b604722SMark Rutland pte_t *ptep, pte_t pte) 2959b604722SMark Rutland { 2969b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 2979b604722SMark Rutland __sync_icache_dcache(pte); 2989b604722SMark Rutland 2999b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 3009b604722SMark Rutland 3014f04d8f0SCatalin Marinas set_pte(ptep, pte); 3024f04d8f0SCatalin Marinas } 3034f04d8f0SCatalin Marinas 3044f04d8f0SCatalin Marinas /* 3054f04d8f0SCatalin Marinas * Huge pte definitions. 3064f04d8f0SCatalin Marinas */ 307084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 308084bd298SSteve Capper 309084bd298SSteve Capper /* 310084bd298SSteve Capper * Hugetlb definitions. 311084bd298SSteve Capper */ 31266b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 313084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 314084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 315084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 316084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 3174f04d8f0SCatalin Marinas 31875387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 31975387b92SKristina Martsenko { 32075387b92SKristina Martsenko return __pte(pgd_val(pgd)); 32175387b92SKristina Martsenko } 32275387b92SKristina Martsenko 323e9f63768SMike Rapoport static inline pte_t p4d_pte(p4d_t p4d) 324e9f63768SMike Rapoport { 325e9f63768SMike Rapoport return __pte(p4d_val(p4d)); 326e9f63768SMike Rapoport } 327e9f63768SMike Rapoport 32829e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 32929e56940SSteve Capper { 33029e56940SSteve Capper return __pte(pud_val(pud)); 33129e56940SSteve Capper } 33229e56940SSteve Capper 333eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 334eb3f0624SPunit Agrawal { 335eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 336eb3f0624SPunit Agrawal } 337eb3f0624SPunit Agrawal 33829e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 33929e56940SSteve Capper { 34029e56940SSteve Capper return __pmd(pud_val(pud)); 34129e56940SSteve Capper } 34229e56940SSteve Capper 3439c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3449c7e535fSSteve Capper { 3459c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3469c7e535fSSteve Capper } 347af074848SSteve Capper 3489c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3499c7e535fSSteve Capper { 3509c7e535fSSteve Capper return __pmd(pte_val(pte)); 3519c7e535fSSteve Capper } 352af074848SSteve Capper 353f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3548ce837ceSArd Biesheuvel { 355f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 356f7f0097aSAnshuman Khandual } 357f7f0097aSAnshuman Khandual 358f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 359f7f0097aSAnshuman Khandual { 360f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3618ce837ceSArd Biesheuvel } 3628ce837ceSArd Biesheuvel 36356166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 36456166230SGanapatrao Kulkarni /* 365ca5999fdSMike Rapoport * See the comment in include/linux/pgtable.h 36656166230SGanapatrao Kulkarni */ 36756166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 36856166230SGanapatrao Kulkarni { 36956166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 37056166230SGanapatrao Kulkarni } 37156166230SGanapatrao Kulkarni 37256166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 37356166230SGanapatrao Kulkarni { 37456166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 37556166230SGanapatrao Kulkarni } 37656166230SGanapatrao Kulkarni #endif 37756166230SGanapatrao Kulkarni 378*b65399f6SAnshuman Khandual #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID)) 379*b65399f6SAnshuman Khandual 380*b65399f6SAnshuman Khandual static inline int pmd_present(pmd_t pmd) 381*b65399f6SAnshuman Khandual { 382*b65399f6SAnshuman Khandual return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd); 383*b65399f6SAnshuman Khandual } 384*b65399f6SAnshuman Khandual 385af074848SSteve Capper /* 386af074848SSteve Capper * THP definitions. 387af074848SSteve Capper */ 388af074848SSteve Capper 389af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 390*b65399f6SAnshuman Khandual static inline int pmd_trans_huge(pmd_t pmd) 391*b65399f6SAnshuman Khandual { 392*b65399f6SAnshuman Khandual return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 393*b65399f6SAnshuman Khandual } 39429e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 395af074848SSteve Capper 396c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3979c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3980795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3999c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 4009c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 4019c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 40205ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 4039c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 4049c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 405*b65399f6SAnshuman Khandual 406*b65399f6SAnshuman Khandual static inline pmd_t pmd_mkinvalid(pmd_t pmd) 407*b65399f6SAnshuman Khandual { 408*b65399f6SAnshuman Khandual pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID)); 409*b65399f6SAnshuman Khandual pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID)); 410*b65399f6SAnshuman Khandual 411*b65399f6SAnshuman Khandual return pmd; 412*b65399f6SAnshuman Khandual } 413af074848SSteve Capper 4140dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 4150dbd3b18SSuzuki K Poulose 4169c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 417af074848SSteve Capper 418af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 419af074848SSteve Capper 42073b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 42173b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 42273b20c84SRobin Murphy #endif 42330e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 42430e23538SJia He { 42530e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 42630e23538SJia He } 42773b20c84SRobin Murphy 42875387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 42975387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 43075387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 43175387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 432af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 433af074848SSteve Capper 43435a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 435eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 43629e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 43775387b92SKristina Martsenko 438b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 439b8e0ba7cSPunit Agrawal 44075387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 44175387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 44275387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 44375387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 444af074848SSteve Capper 445ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 446af074848SSteve Capper 447e9f63768SMike Rapoport #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d)) 448e9f63768SMike Rapoport #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys) 449e9f63768SMike Rapoport 45075387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 45175387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 45275387b92SKristina Martsenko 453a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 454a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 455a501e324SCatalin Marinas 456cca98e9fSChristoph Hellwig #define pgprot_nx(prot) \ 457034aa9cdSWill Deacon __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN) 458cca98e9fSChristoph Hellwig 459af074848SSteve Capper /* 4604f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4614f04d8f0SCatalin Marinas */ 4624f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 463de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4644f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 465de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 466d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 467d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4683e4e1d3fSChristoph Hellwig /* 4693e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 4703e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 4713e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 4723e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 4733e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 4743e4e1d3fSChristoph Hellwig * endpoint. 4753e4e1d3fSChristoph Hellwig */ 476419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 477419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 478419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 479419e2f18SChristoph Hellwig 4804f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4814f04d8f0SCatalin Marinas struct file; 4824f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4834f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4844f04d8f0SCatalin Marinas 4854f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4864f04d8f0SCatalin Marinas 487ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4884f04d8f0SCatalin Marinas 48936311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 49036311607SMarc Zyngier PMD_TYPE_TABLE) 49136311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 49236311607SMarc Zyngier PMD_TYPE_SECT) 4938aa82df3SSteven Price #define pmd_leaf(pmd) pmd_sect(pmd) 49436311607SMarc Zyngier 495cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 4967d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 4977d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 498206a2a73SSteve Capper #else 499206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 500206a2a73SSteve Capper PUD_TYPE_SECT) 501523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 502523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 503206a2a73SSteve Capper #endif 50436311607SMarc Zyngier 5052330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 5062330b7caSJun Yao extern pgd_t init_pg_end[]; 5072330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 5082330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 5099d2d75edSGavin Shan extern pgd_t idmap_pg_end[]; 5102330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 5112330b7caSJun Yao 5122330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 5132330b7caSJun Yao 5142330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 5152330b7caSJun Yao { 5162330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 5172330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 5182330b7caSJun Yao } 5192330b7caSJun Yao 5204f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 5214f04d8f0SCatalin Marinas { 522e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 523e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 5242330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 5252330b7caSJun Yao return; 5262330b7caSJun Yao } 527e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 5282330b7caSJun Yao 52920a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 5300795edafSWill Deacon 531d0b7a302SWill Deacon if (pmd_valid(pmd)) { 53298f7685eSWill Deacon dsb(ishst); 533d0b7a302SWill Deacon isb(); 534d0b7a302SWill Deacon } 5354f04d8f0SCatalin Marinas } 5364f04d8f0SCatalin Marinas 5374f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 5384f04d8f0SCatalin Marinas { 5394f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 5404f04d8f0SCatalin Marinas } 5414f04d8f0SCatalin Marinas 542dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 5434f04d8f0SCatalin Marinas { 54475387b92SKristina Martsenko return __pmd_to_phys(pmd); 5454f04d8f0SCatalin Marinas } 5464f04d8f0SCatalin Marinas 547974b9b2cSMike Rapoport static inline unsigned long pmd_page_vaddr(pmd_t pmd) 548974b9b2cSMike Rapoport { 549974b9b2cSMike Rapoport return (unsigned long)__va(pmd_page_paddr(pmd)); 550974b9b2cSMike Rapoport } 55174dd022fSQian Cai 552053520f7SMark Rutland /* Find an entry in the third-level page table. */ 553f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 554053520f7SMark Rutland 555961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 556961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 557961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 558961faac1SMark Rutland 55968ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 5604f04d8f0SCatalin Marinas 5616533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5626533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 5636533945aSArd Biesheuvel 5644f04d8f0SCatalin Marinas /* 5654f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 5664f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 5674f04d8f0SCatalin Marinas */ 5684f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 5694f04d8f0SCatalin Marinas 5709f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 5714f04d8f0SCatalin Marinas 5727078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 5737078db46SCatalin Marinas 5744f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 575ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 576f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5778aa82df3SSteven Price #define pud_leaf(pud) pud_sect(pud) 5780795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5794f04d8f0SCatalin Marinas 5804f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5814f04d8f0SCatalin Marinas { 582e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 583e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5842330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5852330b7caSJun Yao return; 5862330b7caSJun Yao } 587e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5882330b7caSJun Yao 58920a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5900795edafSWill Deacon 591d0b7a302SWill Deacon if (pud_valid(pud)) { 59298f7685eSWill Deacon dsb(ishst); 593d0b7a302SWill Deacon isb(); 594d0b7a302SWill Deacon } 5954f04d8f0SCatalin Marinas } 5964f04d8f0SCatalin Marinas 5974f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5984f04d8f0SCatalin Marinas { 5994f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 6004f04d8f0SCatalin Marinas } 6014f04d8f0SCatalin Marinas 602dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 6034f04d8f0SCatalin Marinas { 60475387b92SKristina Martsenko return __pud_to_phys(pud); 6054f04d8f0SCatalin Marinas } 6064f04d8f0SCatalin Marinas 607974b9b2cSMike Rapoport static inline unsigned long pud_page_vaddr(pud_t pud) 608974b9b2cSMike Rapoport { 609974b9b2cSMike Rapoport return (unsigned long)__va(pud_page_paddr(pud)); 610974b9b2cSMike Rapoport } 6117078db46SCatalin Marinas 612974b9b2cSMike Rapoport /* Find an entry in the second-level page table. */ 61320a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 6147078db46SCatalin Marinas 615961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 616961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 617961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 6184f04d8f0SCatalin Marinas 61968ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 62029e56940SSteve Capper 6216533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6226533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 6236533945aSArd Biesheuvel 624dca56dcaSMark Rutland #else 625dca56dcaSMark Rutland 626dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 627dca56dcaSMark Rutland 628961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 629961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 630961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 631961faac1SMark Rutland #define pmd_clear_fixmap() 632961faac1SMark Rutland 6336533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 6346533945aSArd Biesheuvel 6359f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 6364f04d8f0SCatalin Marinas 6379f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 638c79b954bSJungseok Lee 6397078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 6407078db46SCatalin Marinas 641e9f63768SMike Rapoport #define p4d_none(p4d) (!p4d_val(p4d)) 642e9f63768SMike Rapoport #define p4d_bad(p4d) (!(p4d_val(p4d) & 2)) 643e9f63768SMike Rapoport #define p4d_present(p4d) (p4d_val(p4d)) 644c79b954bSJungseok Lee 645e9f63768SMike Rapoport static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) 646c79b954bSJungseok Lee { 647e9f63768SMike Rapoport if (in_swapper_pgdir(p4dp)) { 648e9f63768SMike Rapoport set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d))); 6492330b7caSJun Yao return; 6502330b7caSJun Yao } 6512330b7caSJun Yao 652e9f63768SMike Rapoport WRITE_ONCE(*p4dp, p4d); 653c79b954bSJungseok Lee dsb(ishst); 654eb6a4dccSWill Deacon isb(); 655c79b954bSJungseok Lee } 656c79b954bSJungseok Lee 657e9f63768SMike Rapoport static inline void p4d_clear(p4d_t *p4dp) 658c79b954bSJungseok Lee { 659e9f63768SMike Rapoport set_p4d(p4dp, __p4d(0)); 660c79b954bSJungseok Lee } 661c79b954bSJungseok Lee 662e9f63768SMike Rapoport static inline phys_addr_t p4d_page_paddr(p4d_t p4d) 663c79b954bSJungseok Lee { 664e9f63768SMike Rapoport return __p4d_to_phys(p4d); 665c79b954bSJungseok Lee } 666c79b954bSJungseok Lee 667974b9b2cSMike Rapoport static inline unsigned long p4d_page_vaddr(p4d_t p4d) 668974b9b2cSMike Rapoport { 669974b9b2cSMike Rapoport return (unsigned long)__va(p4d_page_paddr(p4d)); 670974b9b2cSMike Rapoport } 6717078db46SCatalin Marinas 672974b9b2cSMike Rapoport /* Find an entry in the frst-level page table. */ 673e9f63768SMike Rapoport #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 6747078db46SCatalin Marinas 675961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 676e9f63768SMike Rapoport #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr)) 677961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 678c79b954bSJungseok Lee 679e9f63768SMike Rapoport #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d))) 6805d96e0cbSJungseok Lee 6816533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6826533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6836533945aSArd Biesheuvel 684dca56dcaSMark Rutland #else 685dca56dcaSMark Rutland 686e9f63768SMike Rapoport #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;}) 687dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 688dca56dcaSMark Rutland 689961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 690961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 691961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 692961faac1SMark Rutland #define pud_clear_fixmap() 693961faac1SMark Rutland 6946533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6956533945aSArd Biesheuvel 6969f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 697c79b954bSJungseok Lee 6987078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 6997078db46SCatalin Marinas 700961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 701961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 702961faac1SMark Rutland 7034f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 7044f04d8f0SCatalin Marinas { 705a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 7068ef8f360SDave Martin PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP; 7072f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 7082f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 70962d96c71SCatalin Marinas pte = pte_mkdirty(pte); 7104f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 7114f04d8f0SCatalin Marinas return pte; 7124f04d8f0SCatalin Marinas } 7134f04d8f0SCatalin Marinas 7149c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 7159c7e535fSSteve Capper { 7169c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 7179c7e535fSSteve Capper } 7189c7e535fSSteve Capper 71966dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 72066dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 72166dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 72266dbd6e6SCatalin Marinas pte_t entry, int dirty); 72366dbd6e6SCatalin Marinas 724282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 725282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 726282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 727282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 728282aa705SCatalin Marinas pmd_t entry, int dirty) 729282aa705SCatalin Marinas { 730282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 731282aa705SCatalin Marinas } 73273b20c84SRobin Murphy 73373b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 73473b20c84SRobin Murphy { 73573b20c84SRobin Murphy return 0; 73673b20c84SRobin Murphy } 73773b20c84SRobin Murphy 73873b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 73973b20c84SRobin Murphy { 74073b20c84SRobin Murphy return 0; 74173b20c84SRobin Murphy } 742282aa705SCatalin Marinas #endif 743282aa705SCatalin Marinas 7442f4b829cSCatalin Marinas /* 7452f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7462f4b829cSCatalin Marinas */ 7472f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 74806485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 7492f4b829cSCatalin Marinas { 7503bbf7157SCatalin Marinas pte_t old_pte, pte; 7512f4b829cSCatalin Marinas 7523bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7533bbf7157SCatalin Marinas do { 7543bbf7157SCatalin Marinas old_pte = pte; 7553bbf7157SCatalin Marinas pte = pte_mkold(pte); 7563bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7573bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7583bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7592f4b829cSCatalin Marinas 7603bbf7157SCatalin Marinas return pte_young(pte); 7612f4b829cSCatalin Marinas } 7622f4b829cSCatalin Marinas 76306485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 76406485053SCatalin Marinas unsigned long address, 76506485053SCatalin Marinas pte_t *ptep) 76606485053SCatalin Marinas { 76706485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 76806485053SCatalin Marinas } 76906485053SCatalin Marinas 7703403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 7713403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 7723403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 7733403e56bSAlex Van Brunt { 7743403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 7753403e56bSAlex Van Brunt 7763403e56bSAlex Van Brunt if (young) { 7773403e56bSAlex Van Brunt /* 7783403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 7793403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 7803403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 7813403e56bSAlex Van Brunt * window for such an event is bounded by the next 7823403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 7833403e56bSAlex Van Brunt * invalidation. 7843403e56bSAlex Van Brunt */ 7853403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 7863403e56bSAlex Van Brunt } 7873403e56bSAlex Van Brunt 7883403e56bSAlex Van Brunt return young; 7893403e56bSAlex Van Brunt } 7903403e56bSAlex Van Brunt 7912f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7922f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7932f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7942f4b829cSCatalin Marinas unsigned long address, 7952f4b829cSCatalin Marinas pmd_t *pmdp) 7962f4b829cSCatalin Marinas { 7972f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7982f4b829cSCatalin Marinas } 7992f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8002f4b829cSCatalin Marinas 8012f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 8022f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 8032f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 8042f4b829cSCatalin Marinas { 8053bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 8062f4b829cSCatalin Marinas } 8072f4b829cSCatalin Marinas 8082f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 809911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 810911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 8112f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8122f4b829cSCatalin Marinas { 8132f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 8142f4b829cSCatalin Marinas } 8152f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 8162f4b829cSCatalin Marinas 8172f4b829cSCatalin Marinas /* 8188781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 8198781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 8202f4b829cSCatalin Marinas */ 8212f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 8222f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 8232f4b829cSCatalin Marinas { 8243bbf7157SCatalin Marinas pte_t old_pte, pte; 8252f4b829cSCatalin Marinas 8263bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 8273bbf7157SCatalin Marinas do { 8283bbf7157SCatalin Marinas old_pte = pte; 8298781bcbcSSteve Capper /* 8308781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 8318781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 8328781bcbcSSteve Capper */ 8338781bcbcSSteve Capper if (pte_hw_dirty(pte)) 8348781bcbcSSteve Capper pte = pte_mkdirty(pte); 8353bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 8363bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 8373bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 8383bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 8392f4b829cSCatalin Marinas } 8402f4b829cSCatalin Marinas 8412f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 8422f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8432f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8442f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8452f4b829cSCatalin Marinas { 8462f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8472f4b829cSCatalin Marinas } 8481d78a62cSCatalin Marinas 8491d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8501d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8511d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8521d78a62cSCatalin Marinas { 8531d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 8541d78a62cSCatalin Marinas } 8552f4b829cSCatalin Marinas #endif 8562f4b829cSCatalin Marinas 8574f04d8f0SCatalin Marinas /* 8584f04d8f0SCatalin Marinas * Encode and decode a swap entry: 8593676f9efSCatalin Marinas * bits 0-1: present (must be zero) 8609b3e661eSKirill A. Shutemov * bits 2-7: swap type 8619b3e661eSKirill A. Shutemov * bits 8-57: swap offset 862fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 8634f04d8f0SCatalin Marinas */ 8649b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 8654f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 8669b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 8674f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 8684f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 8693676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 8704f04d8f0SCatalin Marinas 8714f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 8723676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 8734f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 8744f04d8f0SCatalin Marinas 8754f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 8764f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 8774f04d8f0SCatalin Marinas 8784f04d8f0SCatalin Marinas /* 8794f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 880aad9061bSGeert Uytterhoeven * PTEs. 8814f04d8f0SCatalin Marinas */ 8824f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 8834f04d8f0SCatalin Marinas 8844f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8854f04d8f0SCatalin Marinas 886cba3574fSWill Deacon /* 887cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 888cba3574fSWill Deacon */ 889cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 890cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 891cba3574fSWill Deacon { 892cba3574fSWill Deacon /* 893120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 894120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 895120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 896cba3574fSWill Deacon */ 897cba3574fSWill Deacon } 898cba3574fSWill Deacon 899cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 900cba3574fSWill Deacon 901529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 902529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 903529c4b05SKristina Martsenko #else 904529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 905529c4b05SKristina Martsenko #endif 906529c4b05SKristina Martsenko 9076af31226SJia He /* 9086af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 9096af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 9106af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 9116af31226SJia He * hardware-managed access flag on arm64. 9126af31226SJia He */ 9136af31226SJia He static inline bool arch_faults_on_old_pte(void) 9146af31226SJia He { 9156af31226SJia He WARN_ON(preemptible()); 9166af31226SJia He 9176af31226SJia He return !cpu_has_hw_af(); 9186af31226SJia He } 9196af31226SJia He #define arch_faults_on_old_pte arch_faults_on_old_pte 9206af31226SJia He 9214f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 9224f04d8f0SCatalin Marinas 9234f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 924