14f04d8f0SCatalin Marinas /* 24f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 34f04d8f0SCatalin Marinas * 44f04d8f0SCatalin Marinas * This program is free software; you can redistribute it and/or modify 54f04d8f0SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 64f04d8f0SCatalin Marinas * published by the Free Software Foundation. 74f04d8f0SCatalin Marinas * 84f04d8f0SCatalin Marinas * This program is distributed in the hope that it will be useful, 94f04d8f0SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 104f04d8f0SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 114f04d8f0SCatalin Marinas * GNU General Public License for more details. 124f04d8f0SCatalin Marinas * 134f04d8f0SCatalin Marinas * You should have received a copy of the GNU General Public License 144f04d8f0SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 154f04d8f0SCatalin Marinas */ 164f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 174f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 184f04d8f0SCatalin Marinas 192f4b829cSCatalin Marinas #include <asm/bug.h> 204f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 214f04d8f0SCatalin Marinas 224f04d8f0SCatalin Marinas #include <asm/memory.h> 234f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 243eca86e7SMark Rutland #include <asm/pgtable-prot.h> 254f04d8f0SCatalin Marinas 264f04d8f0SCatalin Marinas /* 273e1907d5SArd Biesheuvel * VMALLOC range. 2808375198SCatalin Marinas * 29f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 303e1907d5SArd Biesheuvel * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space 313e1907d5SArd Biesheuvel * and fixed mappings 324f04d8f0SCatalin Marinas */ 33f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 3408375198SCatalin Marinas #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 354f04d8f0SCatalin Marinas 363bab79edSArd Biesheuvel #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) 374f04d8f0SCatalin Marinas 38d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 394f04d8f0SCatalin Marinas 404f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 412f4b829cSCatalin Marinas 423bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 43961faac1SMark Rutland #include <asm/fixmap.h> 442f4b829cSCatalin Marinas #include <linux/mmdebug.h> 452f4b829cSCatalin Marinas 464f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 474f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 48c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 494f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 504f04d8f0SCatalin Marinas 514f04d8f0SCatalin Marinas /* 524f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 534f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 544f04d8f0SCatalin Marinas */ 555227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 562077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 574f04d8f0SCatalin Marinas 587078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 597078db46SCatalin Marinas 604f04d8f0SCatalin Marinas #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) 614f04d8f0SCatalin Marinas 624f04d8f0SCatalin Marinas #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 634f04d8f0SCatalin Marinas 644f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 654f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 664f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 677078db46SCatalin Marinas 684f04d8f0SCatalin Marinas /* 694f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 704f04d8f0SCatalin Marinas */ 7184fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 7284fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 7384fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 7484fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 75ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 7693ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 774f04d8f0SCatalin Marinas 78d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 79d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 80d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 81d27cfa1fSArd Biesheuvel }) 82d27cfa1fSArd Biesheuvel 83d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 84d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 85d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 86d27cfa1fSArd Biesheuvel }) 87d27cfa1fSArd Biesheuvel 882f4b829cSCatalin Marinas #ifdef CONFIG_ARM64_HW_AFDBM 89b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 902f4b829cSCatalin Marinas #else 912f4b829cSCatalin Marinas #define pte_hw_dirty(pte) (0) 922f4b829cSCatalin Marinas #endif 932f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 942f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 952f4b829cSCatalin Marinas 96766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 97ec663d96SCatalin Marinas /* 98ec663d96SCatalin Marinas * Execute-only user mappings do not have the PTE_USER bit set. All valid 99ec663d96SCatalin Marinas * kernel mappings have the PTE_UXN bit set. 100ec663d96SCatalin Marinas */ 101ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 102ec663d96SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) 10376c714beSWill Deacon #define pte_valid_young(pte) \ 10476c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 10576c714beSWill Deacon 10676c714beSWill Deacon /* 10776c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 10876c714beSWill Deacon * so that we don't erroneously return false for pages that have been 10976c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 11076c714beSWill Deacon */ 11176c714beSWill Deacon #define pte_accessible(mm, pte) \ 11276c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1134f04d8f0SCatalin Marinas 114b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 115b6d4f280SLaura Abbott { 116b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 117b6d4f280SLaura Abbott return pte; 118b6d4f280SLaura Abbott } 119b6d4f280SLaura Abbott 120b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 121b6d4f280SLaura Abbott { 122b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 123b6d4f280SLaura Abbott return pte; 124b6d4f280SLaura Abbott } 125b6d4f280SLaura Abbott 12644b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 12744b6dfc5SSteve Capper { 128*73e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 129*73e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 130*73e86cb0SCatalin Marinas return pte; 13144b6dfc5SSteve Capper } 1324f04d8f0SCatalin Marinas 13344b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 13444b6dfc5SSteve Capper { 135*73e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 136*73e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 137*73e86cb0SCatalin Marinas return pte; 13844b6dfc5SSteve Capper } 13944b6dfc5SSteve Capper 14044b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 14144b6dfc5SSteve Capper { 142b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 14344b6dfc5SSteve Capper } 14444b6dfc5SSteve Capper 14544b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 14644b6dfc5SSteve Capper { 147b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_DIRTY)); 14844b6dfc5SSteve Capper } 14944b6dfc5SSteve Capper 15044b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 15144b6dfc5SSteve Capper { 152b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 15344b6dfc5SSteve Capper } 15444b6dfc5SSteve Capper 15544b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 15644b6dfc5SSteve Capper { 157b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 15844b6dfc5SSteve Capper } 15944b6dfc5SSteve Capper 16044b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 16144b6dfc5SSteve Capper { 162b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 16344b6dfc5SSteve Capper } 1644f04d8f0SCatalin Marinas 16593ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 16693ef666aSJeremy Linton { 16766b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 16866b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 16993ef666aSJeremy Linton } 17093ef666aSJeremy Linton 17193ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 17293ef666aSJeremy Linton { 17393ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 17493ef666aSJeremy Linton } 17593ef666aSJeremy Linton 1765ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 1775ebe3a44SJames Morse { 1785ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 1795ebe3a44SJames Morse } 1805ebe3a44SJames Morse 18166b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 18266b3923aSDavid Woods { 18366b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 18466b3923aSDavid Woods } 18566b3923aSDavid Woods 1864f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 1874f04d8f0SCatalin Marinas { 1884f04d8f0SCatalin Marinas *ptep = pte; 1897f0b1bf0SCatalin Marinas 1907f0b1bf0SCatalin Marinas /* 1917f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 1927f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 1937f0b1bf0SCatalin Marinas */ 194ec663d96SCatalin Marinas if (pte_valid_not_user(pte)) { 1957f0b1bf0SCatalin Marinas dsb(ishst); 1967f0b1bf0SCatalin Marinas isb(); 1977f0b1bf0SCatalin Marinas } 1984f04d8f0SCatalin Marinas } 1994f04d8f0SCatalin Marinas 2002f4b829cSCatalin Marinas struct mm_struct; 2012f4b829cSCatalin Marinas struct vm_area_struct; 2022f4b829cSCatalin Marinas 2034f04d8f0SCatalin Marinas extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); 2044f04d8f0SCatalin Marinas 2052f4b829cSCatalin Marinas /* 2062f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2072f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2082f4b829cSCatalin Marinas * 2092f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2102f4b829cSCatalin Marinas * 0 0 | 1 0 0 2112f4b829cSCatalin Marinas * 0 1 | 1 1 0 2122f4b829cSCatalin Marinas * 1 0 | 1 0 1 2132f4b829cSCatalin Marinas * 1 1 | 0 1 x 2142f4b829cSCatalin Marinas * 2152f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2162f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2172f4b829cSCatalin Marinas * 218b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2192f4b829cSCatalin Marinas */ 2204f04d8f0SCatalin Marinas static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2214f04d8f0SCatalin Marinas pte_t *ptep, pte_t pte) 2224f04d8f0SCatalin Marinas { 223*73e86cb0SCatalin Marinas if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 224ac15bd63SCatalin Marinas __sync_icache_dcache(pte, addr); 22502522463SWill Deacon 2262f4b829cSCatalin Marinas /* 2272f4b829cSCatalin Marinas * If the existing pte is valid, check for potential race with 2282f4b829cSCatalin Marinas * hardware updates of the pte (ptep_set_access_flags safely changes 2292f4b829cSCatalin Marinas * valid ptes without going through an invalid entry). 2302f4b829cSCatalin Marinas */ 23182d34008SCatalin Marinas if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && 23282d34008SCatalin Marinas pte_valid(*ptep) && pte_valid(pte)) { 23382d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 23482d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 23582d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 23682d34008SCatalin Marinas VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), 23782d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 23882d34008SCatalin Marinas __func__, pte_val(*ptep), pte_val(pte)); 2392f4b829cSCatalin Marinas } 2402f4b829cSCatalin Marinas 2414f04d8f0SCatalin Marinas set_pte(ptep, pte); 2424f04d8f0SCatalin Marinas } 2434f04d8f0SCatalin Marinas 244747a70e6SSteve Capper #define __HAVE_ARCH_PTE_SAME 245747a70e6SSteve Capper static inline int pte_same(pte_t pte_a, pte_t pte_b) 246747a70e6SSteve Capper { 247747a70e6SSteve Capper pteval_t lhs, rhs; 248747a70e6SSteve Capper 249747a70e6SSteve Capper lhs = pte_val(pte_a); 250747a70e6SSteve Capper rhs = pte_val(pte_b); 251747a70e6SSteve Capper 252747a70e6SSteve Capper if (pte_present(pte_a)) 253747a70e6SSteve Capper lhs &= ~PTE_RDONLY; 254747a70e6SSteve Capper 255747a70e6SSteve Capper if (pte_present(pte_b)) 256747a70e6SSteve Capper rhs &= ~PTE_RDONLY; 257747a70e6SSteve Capper 258747a70e6SSteve Capper return (lhs == rhs); 259747a70e6SSteve Capper } 260747a70e6SSteve Capper 2614f04d8f0SCatalin Marinas /* 2624f04d8f0SCatalin Marinas * Huge pte definitions. 2634f04d8f0SCatalin Marinas */ 264084bd298SSteve Capper #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) 265084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 266084bd298SSteve Capper 267084bd298SSteve Capper /* 268084bd298SSteve Capper * Hugetlb definitions. 269084bd298SSteve Capper */ 27066b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 271084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 272084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 273084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 274084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 2754f04d8f0SCatalin Marinas 2764f04d8f0SCatalin Marinas #define __HAVE_ARCH_PTE_SPECIAL 2774f04d8f0SCatalin Marinas 27829e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 27929e56940SSteve Capper { 28029e56940SSteve Capper return __pte(pud_val(pud)); 28129e56940SSteve Capper } 28229e56940SSteve Capper 28329e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 28429e56940SSteve Capper { 28529e56940SSteve Capper return __pmd(pud_val(pud)); 28629e56940SSteve Capper } 28729e56940SSteve Capper 2889c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 2899c7e535fSSteve Capper { 2909c7e535fSSteve Capper return __pte(pmd_val(pmd)); 2919c7e535fSSteve Capper } 292af074848SSteve Capper 2939c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 2949c7e535fSSteve Capper { 2959c7e535fSSteve Capper return __pmd(pte_val(pte)); 2969c7e535fSSteve Capper } 297af074848SSteve Capper 2988ce837ceSArd Biesheuvel static inline pgprot_t mk_sect_prot(pgprot_t prot) 2998ce837ceSArd Biesheuvel { 3008ce837ceSArd Biesheuvel return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); 3018ce837ceSArd Biesheuvel } 3028ce837ceSArd Biesheuvel 30356166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 30456166230SGanapatrao Kulkarni /* 30556166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 30656166230SGanapatrao Kulkarni */ 30756166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 30856166230SGanapatrao Kulkarni { 30956166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 31056166230SGanapatrao Kulkarni } 31156166230SGanapatrao Kulkarni 31256166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 31356166230SGanapatrao Kulkarni { 31456166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 31556166230SGanapatrao Kulkarni } 31656166230SGanapatrao Kulkarni #endif 31756166230SGanapatrao Kulkarni 318af074848SSteve Capper /* 319af074848SSteve Capper * THP definitions. 320af074848SSteve Capper */ 321af074848SSteve Capper 322af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 323af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 32429e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 325af074848SSteve Capper 3265bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 327c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3289c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3299c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3309c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3319c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 33205ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3339c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3349c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3355bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 336af074848SSteve Capper 3370dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3380dbd3b18SSuzuki K Poulose 3399c7e535fSSteve Capper #define __HAVE_ARCH_PMD_WRITE 3409c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 341af074848SSteve Capper 342af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 343af074848SSteve Capper 344af074848SSteve Capper #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 345af074848SSteve Capper #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 346af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 347af074848SSteve Capper 34829e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 349206a2a73SSteve Capper #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 350af074848SSteve Capper 351ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 352af074848SSteve Capper 353a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 354a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 355a501e324SCatalin Marinas 356af074848SSteve Capper /* 3574f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 3584f04d8f0SCatalin Marinas */ 3594f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 360de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 3614f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 362de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 363d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 364d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 3654f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 3664f04d8f0SCatalin Marinas struct file; 3674f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 3684f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 3694f04d8f0SCatalin Marinas 3704f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 3714f04d8f0SCatalin Marinas 372ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 3734f04d8f0SCatalin Marinas 37436311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 37536311607SMarc Zyngier PMD_TYPE_TABLE) 37636311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 37736311607SMarc Zyngier PMD_TYPE_SECT) 37836311607SMarc Zyngier 379cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 380206a2a73SSteve Capper #define pud_sect(pud) (0) 381523d6e9fSzhichang.yuan #define pud_table(pud) (1) 382206a2a73SSteve Capper #else 383206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 384206a2a73SSteve Capper PUD_TYPE_SECT) 385523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 386523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 387206a2a73SSteve Capper #endif 38836311607SMarc Zyngier 3894f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 3904f04d8f0SCatalin Marinas { 3914f04d8f0SCatalin Marinas *pmdp = pmd; 39298f7685eSWill Deacon dsb(ishst); 3937f0b1bf0SCatalin Marinas isb(); 3944f04d8f0SCatalin Marinas } 3954f04d8f0SCatalin Marinas 3964f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 3974f04d8f0SCatalin Marinas { 3984f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 3994f04d8f0SCatalin Marinas } 4004f04d8f0SCatalin Marinas 401dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4024f04d8f0SCatalin Marinas { 403dca56dcaSMark Rutland return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; 4044f04d8f0SCatalin Marinas } 4054f04d8f0SCatalin Marinas 406053520f7SMark Rutland /* Find an entry in the third-level page table. */ 407053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 408053520f7SMark Rutland 409dca56dcaSMark Rutland #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) 410dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 411053520f7SMark Rutland 412053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 413053520f7SMark Rutland #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) 414053520f7SMark Rutland #define pte_unmap(pte) do { } while (0) 415053520f7SMark Rutland #define pte_unmap_nested(pte) do { } while (0) 416053520f7SMark Rutland 417961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 418961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 419961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 420961faac1SMark Rutland 4214f04d8f0SCatalin Marinas #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 4224f04d8f0SCatalin Marinas 4236533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4246533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 4256533945aSArd Biesheuvel 4264f04d8f0SCatalin Marinas /* 4274f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 4284f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 4294f04d8f0SCatalin Marinas */ 4304f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 4314f04d8f0SCatalin Marinas 4329f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 4334f04d8f0SCatalin Marinas 4347078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 4357078db46SCatalin Marinas 4364f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 437ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 438f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 4394f04d8f0SCatalin Marinas 4404f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 4414f04d8f0SCatalin Marinas { 4424f04d8f0SCatalin Marinas *pudp = pud; 44398f7685eSWill Deacon dsb(ishst); 4447f0b1bf0SCatalin Marinas isb(); 4454f04d8f0SCatalin Marinas } 4464f04d8f0SCatalin Marinas 4474f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 4484f04d8f0SCatalin Marinas { 4494f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 4504f04d8f0SCatalin Marinas } 4514f04d8f0SCatalin Marinas 452dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 4534f04d8f0SCatalin Marinas { 454dca56dcaSMark Rutland return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; 4554f04d8f0SCatalin Marinas } 4564f04d8f0SCatalin Marinas 4577078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 4587078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 4597078db46SCatalin Marinas 460dca56dcaSMark Rutland #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) 461dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 4627078db46SCatalin Marinas 463961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 464961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 465961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 4664f04d8f0SCatalin Marinas 4675d96e0cbSJungseok Lee #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) 46829e56940SSteve Capper 4696533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 4706533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 4716533945aSArd Biesheuvel 472dca56dcaSMark Rutland #else 473dca56dcaSMark Rutland 474dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 475dca56dcaSMark Rutland 476961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 477961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 478961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 479961faac1SMark Rutland #define pmd_clear_fixmap() 480961faac1SMark Rutland 4816533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 4826533945aSArd Biesheuvel 4839f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 4844f04d8f0SCatalin Marinas 4859f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 486c79b954bSJungseok Lee 4877078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 4887078db46SCatalin Marinas 489c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 490c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 491c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 492c79b954bSJungseok Lee 493c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 494c79b954bSJungseok Lee { 495c79b954bSJungseok Lee *pgdp = pgd; 496c79b954bSJungseok Lee dsb(ishst); 497c79b954bSJungseok Lee } 498c79b954bSJungseok Lee 499c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 500c79b954bSJungseok Lee { 501c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 502c79b954bSJungseok Lee } 503c79b954bSJungseok Lee 504dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 505c79b954bSJungseok Lee { 506dca56dcaSMark Rutland return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; 507c79b954bSJungseok Lee } 508c79b954bSJungseok Lee 5097078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 5107078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 5117078db46SCatalin Marinas 512dca56dcaSMark Rutland #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) 513dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 5147078db46SCatalin Marinas 515961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 516961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 517961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 518c79b954bSJungseok Lee 5195d96e0cbSJungseok Lee #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) 5205d96e0cbSJungseok Lee 5216533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5226533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 5236533945aSArd Biesheuvel 524dca56dcaSMark Rutland #else 525dca56dcaSMark Rutland 526dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 527dca56dcaSMark Rutland 528961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 529961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 530961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 531961faac1SMark Rutland #define pud_clear_fixmap() 532961faac1SMark Rutland 5336533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 5346533945aSArd Biesheuvel 5359f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 536c79b954bSJungseok Lee 5377078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 5387078db46SCatalin Marinas 5394f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 5404f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 5414f04d8f0SCatalin Marinas 542dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 543dca56dcaSMark Rutland 544dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 5454f04d8f0SCatalin Marinas 5464f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 5474f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 5484f04d8f0SCatalin Marinas 549961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 550961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 551961faac1SMark Rutland 5524f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 5534f04d8f0SCatalin Marinas { 554a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 5551a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 5562f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 5572f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 55862d96c71SCatalin Marinas pte = pte_mkdirty(pte); 5594f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 5604f04d8f0SCatalin Marinas return pte; 5614f04d8f0SCatalin Marinas } 5624f04d8f0SCatalin Marinas 5639c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 5649c7e535fSSteve Capper { 5659c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 5669c7e535fSSteve Capper } 5679c7e535fSSteve Capper 5682f4b829cSCatalin Marinas #ifdef CONFIG_ARM64_HW_AFDBM 56966dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 57066dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 57166dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 57266dbd6e6SCatalin Marinas pte_t entry, int dirty); 57366dbd6e6SCatalin Marinas 574282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 575282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 576282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 577282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 578282aa705SCatalin Marinas pmd_t entry, int dirty) 579282aa705SCatalin Marinas { 580282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 581282aa705SCatalin Marinas } 582282aa705SCatalin Marinas #endif 583282aa705SCatalin Marinas 5842f4b829cSCatalin Marinas /* 5852f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 5862f4b829cSCatalin Marinas */ 5872f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 58806485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 5892f4b829cSCatalin Marinas { 5903bbf7157SCatalin Marinas pte_t old_pte, pte; 5912f4b829cSCatalin Marinas 5923bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 5933bbf7157SCatalin Marinas do { 5943bbf7157SCatalin Marinas old_pte = pte; 5953bbf7157SCatalin Marinas pte = pte_mkold(pte); 5963bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 5973bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 5983bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 5992f4b829cSCatalin Marinas 6003bbf7157SCatalin Marinas return pte_young(pte); 6012f4b829cSCatalin Marinas } 6022f4b829cSCatalin Marinas 60306485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 60406485053SCatalin Marinas unsigned long address, 60506485053SCatalin Marinas pte_t *ptep) 60606485053SCatalin Marinas { 60706485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 60806485053SCatalin Marinas } 60906485053SCatalin Marinas 6102f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6112f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 6122f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 6132f4b829cSCatalin Marinas unsigned long address, 6142f4b829cSCatalin Marinas pmd_t *pmdp) 6152f4b829cSCatalin Marinas { 6162f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 6172f4b829cSCatalin Marinas } 6182f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6192f4b829cSCatalin Marinas 6202f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 6212f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 6222f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 6232f4b829cSCatalin Marinas { 6243bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 6252f4b829cSCatalin Marinas } 6262f4b829cSCatalin Marinas 6272f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 628911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 629911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 6302f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6312f4b829cSCatalin Marinas { 6322f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 6332f4b829cSCatalin Marinas } 6342f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 6352f4b829cSCatalin Marinas 6362f4b829cSCatalin Marinas /* 6372f4b829cSCatalin Marinas * ptep_set_wrprotect - mark read-only while trasferring potential hardware 6382f4b829cSCatalin Marinas * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 6392f4b829cSCatalin Marinas */ 6402f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 6412f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 6422f4b829cSCatalin Marinas { 6433bbf7157SCatalin Marinas pte_t old_pte, pte; 6442f4b829cSCatalin Marinas 6453bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 6463bbf7157SCatalin Marinas do { 6473bbf7157SCatalin Marinas old_pte = pte; 6483bbf7157SCatalin Marinas /* 6493bbf7157SCatalin Marinas * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 650*73e86cb0SCatalin Marinas * clear), set the PTE_DIRTY bit. 6513bbf7157SCatalin Marinas */ 652*73e86cb0SCatalin Marinas if (pte_hw_dirty(pte)) 6533bbf7157SCatalin Marinas pte = pte_mkdirty(pte); 6543bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 6553bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 6563bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 6573bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 6582f4b829cSCatalin Marinas } 6592f4b829cSCatalin Marinas 6602f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 6612f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 6622f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 6632f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 6642f4b829cSCatalin Marinas { 6652f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 6662f4b829cSCatalin Marinas } 6672f4b829cSCatalin Marinas #endif 6682f4b829cSCatalin Marinas #endif /* CONFIG_ARM64_HW_AFDBM */ 6692f4b829cSCatalin Marinas 6704f04d8f0SCatalin Marinas extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 6714f04d8f0SCatalin Marinas extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 6724f04d8f0SCatalin Marinas 6734f04d8f0SCatalin Marinas /* 6744f04d8f0SCatalin Marinas * Encode and decode a swap entry: 6753676f9efSCatalin Marinas * bits 0-1: present (must be zero) 6769b3e661eSKirill A. Shutemov * bits 2-7: swap type 6779b3e661eSKirill A. Shutemov * bits 8-57: swap offset 678fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 6794f04d8f0SCatalin Marinas */ 6809b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 6814f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 6829b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 6834f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 6844f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 6853676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 6864f04d8f0SCatalin Marinas 6874f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 6883676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 6894f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 6904f04d8f0SCatalin Marinas 6914f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 6924f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 6934f04d8f0SCatalin Marinas 6944f04d8f0SCatalin Marinas /* 6954f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 696aad9061bSGeert Uytterhoeven * PTEs. 6974f04d8f0SCatalin Marinas */ 6984f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 6994f04d8f0SCatalin Marinas 7004f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 7014f04d8f0SCatalin Marinas 7024f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 7034f04d8f0SCatalin Marinas 70439b5be9bSWill Deacon void pgd_cache_init(void); 70539b5be9bSWill Deacon #define pgtable_cache_init pgd_cache_init 7064f04d8f0SCatalin Marinas 707cba3574fSWill Deacon /* 708cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 709cba3574fSWill Deacon */ 710cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 711cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 712cba3574fSWill Deacon { 713cba3574fSWill Deacon /* 714120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 715120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 716120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 717cba3574fSWill Deacon */ 718cba3574fSWill Deacon } 719cba3574fSWill Deacon 720cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 721cba3574fSWill Deacon 72203875ad5Syalin wang #define kc_vaddr_to_offset(v) ((v) & ~VA_START) 72303875ad5Syalin wang #define kc_offset_to_vaddr(o) ((o) | VA_START) 7247db743c6SCatalin Marinas 7254f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 7264f04d8f0SCatalin Marinas 7274f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 728