1caab277bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f04d8f0SCatalin Marinas /* 34f04d8f0SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 44f04d8f0SCatalin Marinas */ 54f04d8f0SCatalin Marinas #ifndef __ASM_PGTABLE_H 64f04d8f0SCatalin Marinas #define __ASM_PGTABLE_H 74f04d8f0SCatalin Marinas 82f4b829cSCatalin Marinas #include <asm/bug.h> 94f04d8f0SCatalin Marinas #include <asm/proc-fns.h> 104f04d8f0SCatalin Marinas 114f04d8f0SCatalin Marinas #include <asm/memory.h> 124f04d8f0SCatalin Marinas #include <asm/pgtable-hwdef.h> 133eca86e7SMark Rutland #include <asm/pgtable-prot.h> 143403e56bSAlex Van Brunt #include <asm/tlbflush.h> 154f04d8f0SCatalin Marinas 164f04d8f0SCatalin Marinas /* 173e1907d5SArd Biesheuvel * VMALLOC range. 1808375198SCatalin Marinas * 19f9040773SArd Biesheuvel * VMALLOC_START: beginning of the kernel vmalloc space 20a5315819SMark Brown * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space 213e1907d5SArd Biesheuvel * and fixed mappings 224f04d8f0SCatalin Marinas */ 23f9040773SArd Biesheuvel #define VMALLOC_START (MODULES_END) 2414c127c9SSteve Capper #define VMALLOC_END (- PUD_SIZE - VMEMMAP_SIZE - SZ_64K) 254f04d8f0SCatalin Marinas 26d016bf7eSKirill A. Shutemov #define FIRST_USER_ADDRESS 0UL 274f04d8f0SCatalin Marinas 284f04d8f0SCatalin Marinas #ifndef __ASSEMBLY__ 292f4b829cSCatalin Marinas 303bbf7157SCatalin Marinas #include <asm/cmpxchg.h> 31961faac1SMark Rutland #include <asm/fixmap.h> 322f4b829cSCatalin Marinas #include <linux/mmdebug.h> 3386c9e812SWill Deacon #include <linux/mm_types.h> 3486c9e812SWill Deacon #include <linux/sched.h> 352f4b829cSCatalin Marinas 36c8b6d2ccSSteve Capper extern struct page *vmemmap; 37c8b6d2ccSSteve Capper 384f04d8f0SCatalin Marinas extern void __pte_error(const char *file, int line, unsigned long val); 394f04d8f0SCatalin Marinas extern void __pmd_error(const char *file, int line, unsigned long val); 40c79b954bSJungseok Lee extern void __pud_error(const char *file, int line, unsigned long val); 414f04d8f0SCatalin Marinas extern void __pgd_error(const char *file, int line, unsigned long val); 424f04d8f0SCatalin Marinas 434f04d8f0SCatalin Marinas /* 444f04d8f0SCatalin Marinas * ZERO_PAGE is a global shared page that is always zero: used 454f04d8f0SCatalin Marinas * for zero-mapped memory areas etc.. 464f04d8f0SCatalin Marinas */ 475227cfa7SMark Rutland extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 482077be67SLaura Abbott #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) 494f04d8f0SCatalin Marinas 507078db46SCatalin Marinas #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 517078db46SCatalin Marinas 5275387b92SKristina Martsenko /* 5375387b92SKristina Martsenko * Macros to convert between a physical address and its placement in a 5475387b92SKristina Martsenko * page table entry, taking care of 52-bit addresses. 5575387b92SKristina Martsenko */ 5675387b92SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 5775387b92SKristina Martsenko #define __pte_to_phys(pte) \ 5875387b92SKristina Martsenko ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) 5975387b92SKristina Martsenko #define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) 6075387b92SKristina Martsenko #else 6175387b92SKristina Martsenko #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) 6275387b92SKristina Martsenko #define __phys_to_pte_val(phys) (phys) 6375387b92SKristina Martsenko #endif 644f04d8f0SCatalin Marinas 6575387b92SKristina Martsenko #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) 6675387b92SKristina Martsenko #define pfn_pte(pfn,prot) \ 6775387b92SKristina Martsenko __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 684f04d8f0SCatalin Marinas 694f04d8f0SCatalin Marinas #define pte_none(pte) (!pte_val(pte)) 704f04d8f0SCatalin Marinas #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) 714f04d8f0SCatalin Marinas #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 727078db46SCatalin Marinas 734f04d8f0SCatalin Marinas /* 744f04d8f0SCatalin Marinas * The following only work if pte_present(). Undefined behaviour otherwise. 754f04d8f0SCatalin Marinas */ 7684fe6826SSteve Capper #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) 7784fe6826SSteve Capper #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) 7884fe6826SSteve Capper #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) 7984fe6826SSteve Capper #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) 80ec663d96SCatalin Marinas #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) 8193ef666aSJeremy Linton #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) 8273b20c84SRobin Murphy #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP)) 834f04d8f0SCatalin Marinas 84d27cfa1fSArd Biesheuvel #define pte_cont_addr_end(addr, end) \ 85d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ 86d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 87d27cfa1fSArd Biesheuvel }) 88d27cfa1fSArd Biesheuvel 89d27cfa1fSArd Biesheuvel #define pmd_cont_addr_end(addr, end) \ 90d27cfa1fSArd Biesheuvel ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ 91d27cfa1fSArd Biesheuvel (__boundary - 1 < (end) - 1) ? __boundary : (end); \ 92d27cfa1fSArd Biesheuvel }) 93d27cfa1fSArd Biesheuvel 94b847415cSCatalin Marinas #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) 952f4b829cSCatalin Marinas #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) 962f4b829cSCatalin Marinas #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) 972f4b829cSCatalin Marinas 98766ffb69SWill Deacon #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) 99ec663d96SCatalin Marinas #define pte_valid_not_user(pte) \ 10024cecc37SCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) 10176c714beSWill Deacon #define pte_valid_young(pte) \ 10276c714beSWill Deacon ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) 1036218f96cSCatalin Marinas #define pte_valid_user(pte) \ 1046218f96cSCatalin Marinas ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) 10576c714beSWill Deacon 10676c714beSWill Deacon /* 10776c714beSWill Deacon * Could the pte be present in the TLB? We must check mm_tlb_flush_pending 10876c714beSWill Deacon * so that we don't erroneously return false for pages that have been 10976c714beSWill Deacon * remapped as PROT_NONE but are yet to be flushed from the TLB. 11076c714beSWill Deacon */ 11176c714beSWill Deacon #define pte_accessible(mm, pte) \ 11276c714beSWill Deacon (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) 1134f04d8f0SCatalin Marinas 1146218f96cSCatalin Marinas /* 1156218f96cSCatalin Marinas * p??_access_permitted() is true for valid user mappings (subject to the 11624cecc37SCatalin Marinas * write permission check). PROT_NONE mappings do not have the PTE_VALID bit 11724cecc37SCatalin Marinas * set. 1186218f96cSCatalin Marinas */ 1196218f96cSCatalin Marinas #define pte_access_permitted(pte, write) \ 1206218f96cSCatalin Marinas (pte_valid_user(pte) && (!(write) || pte_write(pte))) 1216218f96cSCatalin Marinas #define pmd_access_permitted(pmd, write) \ 1226218f96cSCatalin Marinas (pte_access_permitted(pmd_pte(pmd), (write))) 1236218f96cSCatalin Marinas #define pud_access_permitted(pud, write) \ 1246218f96cSCatalin Marinas (pte_access_permitted(pud_pte(pud), (write))) 1256218f96cSCatalin Marinas 126b6d4f280SLaura Abbott static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) 127b6d4f280SLaura Abbott { 128b6d4f280SLaura Abbott pte_val(pte) &= ~pgprot_val(prot); 129b6d4f280SLaura Abbott return pte; 130b6d4f280SLaura Abbott } 131b6d4f280SLaura Abbott 132b6d4f280SLaura Abbott static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) 133b6d4f280SLaura Abbott { 134b6d4f280SLaura Abbott pte_val(pte) |= pgprot_val(prot); 135b6d4f280SLaura Abbott return pte; 136b6d4f280SLaura Abbott } 137b6d4f280SLaura Abbott 13844b6dfc5SSteve Capper static inline pte_t pte_wrprotect(pte_t pte) 13944b6dfc5SSteve Capper { 14073e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_WRITE)); 14173e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 14273e86cb0SCatalin Marinas return pte; 14344b6dfc5SSteve Capper } 1444f04d8f0SCatalin Marinas 14544b6dfc5SSteve Capper static inline pte_t pte_mkwrite(pte_t pte) 14644b6dfc5SSteve Capper { 14773e86cb0SCatalin Marinas pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); 14873e86cb0SCatalin Marinas pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 14973e86cb0SCatalin Marinas return pte; 15044b6dfc5SSteve Capper } 15144b6dfc5SSteve Capper 15244b6dfc5SSteve Capper static inline pte_t pte_mkclean(pte_t pte) 15344b6dfc5SSteve Capper { 1548781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY)); 1558781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_RDONLY)); 1568781bcbcSSteve Capper 1578781bcbcSSteve Capper return pte; 15844b6dfc5SSteve Capper } 15944b6dfc5SSteve Capper 16044b6dfc5SSteve Capper static inline pte_t pte_mkdirty(pte_t pte) 16144b6dfc5SSteve Capper { 1628781bcbcSSteve Capper pte = set_pte_bit(pte, __pgprot(PTE_DIRTY)); 1638781bcbcSSteve Capper 1648781bcbcSSteve Capper if (pte_write(pte)) 1658781bcbcSSteve Capper pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); 1668781bcbcSSteve Capper 1678781bcbcSSteve Capper return pte; 16844b6dfc5SSteve Capper } 16944b6dfc5SSteve Capper 17044b6dfc5SSteve Capper static inline pte_t pte_mkold(pte_t pte) 17144b6dfc5SSteve Capper { 172b6d4f280SLaura Abbott return clear_pte_bit(pte, __pgprot(PTE_AF)); 17344b6dfc5SSteve Capper } 17444b6dfc5SSteve Capper 17544b6dfc5SSteve Capper static inline pte_t pte_mkyoung(pte_t pte) 17644b6dfc5SSteve Capper { 177b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_AF)); 17844b6dfc5SSteve Capper } 17944b6dfc5SSteve Capper 18044b6dfc5SSteve Capper static inline pte_t pte_mkspecial(pte_t pte) 18144b6dfc5SSteve Capper { 182b6d4f280SLaura Abbott return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); 18344b6dfc5SSteve Capper } 1844f04d8f0SCatalin Marinas 18593ef666aSJeremy Linton static inline pte_t pte_mkcont(pte_t pte) 18693ef666aSJeremy Linton { 18766b3923aSDavid Woods pte = set_pte_bit(pte, __pgprot(PTE_CONT)); 18866b3923aSDavid Woods return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); 18993ef666aSJeremy Linton } 19093ef666aSJeremy Linton 19193ef666aSJeremy Linton static inline pte_t pte_mknoncont(pte_t pte) 19293ef666aSJeremy Linton { 19393ef666aSJeremy Linton return clear_pte_bit(pte, __pgprot(PTE_CONT)); 19493ef666aSJeremy Linton } 19593ef666aSJeremy Linton 1965ebe3a44SJames Morse static inline pte_t pte_mkpresent(pte_t pte) 1975ebe3a44SJames Morse { 1985ebe3a44SJames Morse return set_pte_bit(pte, __pgprot(PTE_VALID)); 1995ebe3a44SJames Morse } 2005ebe3a44SJames Morse 20166b3923aSDavid Woods static inline pmd_t pmd_mkcont(pmd_t pmd) 20266b3923aSDavid Woods { 20366b3923aSDavid Woods return __pmd(pmd_val(pmd) | PMD_SECT_CONT); 20466b3923aSDavid Woods } 20566b3923aSDavid Woods 20673b20c84SRobin Murphy static inline pte_t pte_mkdevmap(pte_t pte) 20773b20c84SRobin Murphy { 20830e23538SJia He return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); 20973b20c84SRobin Murphy } 21073b20c84SRobin Murphy 2114f04d8f0SCatalin Marinas static inline void set_pte(pte_t *ptep, pte_t pte) 2124f04d8f0SCatalin Marinas { 21320a004e7SWill Deacon WRITE_ONCE(*ptep, pte); 2147f0b1bf0SCatalin Marinas 2157f0b1bf0SCatalin Marinas /* 2167f0b1bf0SCatalin Marinas * Only if the new pte is valid and kernel, otherwise TLB maintenance 2177f0b1bf0SCatalin Marinas * or update_mmu_cache() have the necessary barriers. 2187f0b1bf0SCatalin Marinas */ 219d0b7a302SWill Deacon if (pte_valid_not_user(pte)) { 2207f0b1bf0SCatalin Marinas dsb(ishst); 221d0b7a302SWill Deacon isb(); 222d0b7a302SWill Deacon } 2234f04d8f0SCatalin Marinas } 2244f04d8f0SCatalin Marinas 225907e21c1SShaokun Zhang extern void __sync_icache_dcache(pte_t pteval); 2264f04d8f0SCatalin Marinas 2272f4b829cSCatalin Marinas /* 2282f4b829cSCatalin Marinas * PTE bits configuration in the presence of hardware Dirty Bit Management 2292f4b829cSCatalin Marinas * (PTE_WRITE == PTE_DBM): 2302f4b829cSCatalin Marinas * 2312f4b829cSCatalin Marinas * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) 2322f4b829cSCatalin Marinas * 0 0 | 1 0 0 2332f4b829cSCatalin Marinas * 0 1 | 1 1 0 2342f4b829cSCatalin Marinas * 1 0 | 1 0 1 2352f4b829cSCatalin Marinas * 1 1 | 0 1 x 2362f4b829cSCatalin Marinas * 2372f4b829cSCatalin Marinas * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via 2382f4b829cSCatalin Marinas * the page fault mechanism. Checking the dirty status of a pte becomes: 2392f4b829cSCatalin Marinas * 240b847415cSCatalin Marinas * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) 2412f4b829cSCatalin Marinas */ 2429b604722SMark Rutland 2439b604722SMark Rutland static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep, 2449b604722SMark Rutland pte_t pte) 2454f04d8f0SCatalin Marinas { 24620a004e7SWill Deacon pte_t old_pte; 24720a004e7SWill Deacon 2489b604722SMark Rutland if (!IS_ENABLED(CONFIG_DEBUG_VM)) 2499b604722SMark Rutland return; 2509b604722SMark Rutland 2519b604722SMark Rutland old_pte = READ_ONCE(*ptep); 2529b604722SMark Rutland 2539b604722SMark Rutland if (!pte_valid(old_pte) || !pte_valid(pte)) 2549b604722SMark Rutland return; 2559b604722SMark Rutland if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1) 2569b604722SMark Rutland return; 25702522463SWill Deacon 2582f4b829cSCatalin Marinas /* 2599b604722SMark Rutland * Check for potential race with hardware updates of the pte 2609b604722SMark Rutland * (ptep_set_access_flags safely changes valid ptes without going 2619b604722SMark Rutland * through an invalid entry). 2622f4b829cSCatalin Marinas */ 26382d34008SCatalin Marinas VM_WARN_ONCE(!pte_young(pte), 26482d34008SCatalin Marinas "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", 26520a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 26620a004e7SWill Deacon VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte), 26782d34008SCatalin Marinas "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", 26820a004e7SWill Deacon __func__, pte_val(old_pte), pte_val(pte)); 2692f4b829cSCatalin Marinas } 2702f4b829cSCatalin Marinas 2719b604722SMark Rutland static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, 2729b604722SMark Rutland pte_t *ptep, pte_t pte) 2739b604722SMark Rutland { 2749b604722SMark Rutland if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte)) 2759b604722SMark Rutland __sync_icache_dcache(pte); 2769b604722SMark Rutland 2779b604722SMark Rutland __check_racy_pte_update(mm, ptep, pte); 2789b604722SMark Rutland 2794f04d8f0SCatalin Marinas set_pte(ptep, pte); 2804f04d8f0SCatalin Marinas } 2814f04d8f0SCatalin Marinas 2824f04d8f0SCatalin Marinas /* 2834f04d8f0SCatalin Marinas * Huge pte definitions. 2844f04d8f0SCatalin Marinas */ 285084bd298SSteve Capper #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 286084bd298SSteve Capper 287084bd298SSteve Capper /* 288084bd298SSteve Capper * Hugetlb definitions. 289084bd298SSteve Capper */ 29066b3923aSDavid Woods #define HUGE_MAX_HSTATE 4 291084bd298SSteve Capper #define HPAGE_SHIFT PMD_SHIFT 292084bd298SSteve Capper #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 293084bd298SSteve Capper #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 294084bd298SSteve Capper #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 2954f04d8f0SCatalin Marinas 29675387b92SKristina Martsenko static inline pte_t pgd_pte(pgd_t pgd) 29775387b92SKristina Martsenko { 29875387b92SKristina Martsenko return __pte(pgd_val(pgd)); 29975387b92SKristina Martsenko } 30075387b92SKristina Martsenko 30129e56940SSteve Capper static inline pte_t pud_pte(pud_t pud) 30229e56940SSteve Capper { 30329e56940SSteve Capper return __pte(pud_val(pud)); 30429e56940SSteve Capper } 30529e56940SSteve Capper 306eb3f0624SPunit Agrawal static inline pud_t pte_pud(pte_t pte) 307eb3f0624SPunit Agrawal { 308eb3f0624SPunit Agrawal return __pud(pte_val(pte)); 309eb3f0624SPunit Agrawal } 310eb3f0624SPunit Agrawal 31129e56940SSteve Capper static inline pmd_t pud_pmd(pud_t pud) 31229e56940SSteve Capper { 31329e56940SSteve Capper return __pmd(pud_val(pud)); 31429e56940SSteve Capper } 31529e56940SSteve Capper 3169c7e535fSSteve Capper static inline pte_t pmd_pte(pmd_t pmd) 3179c7e535fSSteve Capper { 3189c7e535fSSteve Capper return __pte(pmd_val(pmd)); 3199c7e535fSSteve Capper } 320af074848SSteve Capper 3219c7e535fSSteve Capper static inline pmd_t pte_pmd(pte_t pte) 3229c7e535fSSteve Capper { 3239c7e535fSSteve Capper return __pmd(pte_val(pte)); 3249c7e535fSSteve Capper } 325af074848SSteve Capper 326f7f0097aSAnshuman Khandual static inline pgprot_t mk_pud_sect_prot(pgprot_t prot) 3278ce837ceSArd Biesheuvel { 328f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT); 329f7f0097aSAnshuman Khandual } 330f7f0097aSAnshuman Khandual 331f7f0097aSAnshuman Khandual static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot) 332f7f0097aSAnshuman Khandual { 333f7f0097aSAnshuman Khandual return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT); 3348ce837ceSArd Biesheuvel } 3358ce837ceSArd Biesheuvel 33656166230SGanapatrao Kulkarni #ifdef CONFIG_NUMA_BALANCING 33756166230SGanapatrao Kulkarni /* 33856166230SGanapatrao Kulkarni * See the comment in include/asm-generic/pgtable.h 33956166230SGanapatrao Kulkarni */ 34056166230SGanapatrao Kulkarni static inline int pte_protnone(pte_t pte) 34156166230SGanapatrao Kulkarni { 34256166230SGanapatrao Kulkarni return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; 34356166230SGanapatrao Kulkarni } 34456166230SGanapatrao Kulkarni 34556166230SGanapatrao Kulkarni static inline int pmd_protnone(pmd_t pmd) 34656166230SGanapatrao Kulkarni { 34756166230SGanapatrao Kulkarni return pte_protnone(pmd_pte(pmd)); 34856166230SGanapatrao Kulkarni } 34956166230SGanapatrao Kulkarni #endif 35056166230SGanapatrao Kulkarni 351af074848SSteve Capper /* 352af074848SSteve Capper * THP definitions. 353af074848SSteve Capper */ 354af074848SSteve Capper 355af074848SSteve Capper #ifdef CONFIG_TRANSPARENT_HUGEPAGE 356af074848SSteve Capper #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) 35729e56940SSteve Capper #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 358af074848SSteve Capper 3595bb1cc0fSCatalin Marinas #define pmd_present(pmd) pte_present(pmd_pte(pmd)) 360c164e038SKirill A. Shutemov #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 3619c7e535fSSteve Capper #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 3620795edafSWill Deacon #define pmd_valid(pmd) pte_valid(pmd_pte(pmd)) 3639c7e535fSSteve Capper #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 3649c7e535fSSteve Capper #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 3659c7e535fSSteve Capper #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 36605ee26d9SMinchan Kim #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 3679c7e535fSSteve Capper #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 3689c7e535fSSteve Capper #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 3695bb1cc0fSCatalin Marinas #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) 370af074848SSteve Capper 3710dbd3b18SSuzuki K Poulose #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 3720dbd3b18SSuzuki K Poulose 3739c7e535fSSteve Capper #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 374af074848SSteve Capper 375af074848SSteve Capper #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 376af074848SSteve Capper 37773b20c84SRobin Murphy #ifdef CONFIG_TRANSPARENT_HUGEPAGE 37873b20c84SRobin Murphy #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) 37973b20c84SRobin Murphy #endif 38030e23538SJia He static inline pmd_t pmd_mkdevmap(pmd_t pmd) 38130e23538SJia He { 38230e23538SJia He return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); 38330e23538SJia He } 38473b20c84SRobin Murphy 38575387b92SKristina Martsenko #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) 38675387b92SKristina Martsenko #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) 38775387b92SKristina Martsenko #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT) 38875387b92SKristina Martsenko #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 389af074848SSteve Capper #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 390af074848SSteve Capper 39135a63966SPunit Agrawal #define pud_young(pud) pte_young(pud_pte(pud)) 392eb3f0624SPunit Agrawal #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 39329e56940SSteve Capper #define pud_write(pud) pte_write(pud_pte(pud)) 39475387b92SKristina Martsenko 395b8e0ba7cSPunit Agrawal #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT)) 396b8e0ba7cSPunit Agrawal 39775387b92SKristina Martsenko #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud)) 39875387b92SKristina Martsenko #define __phys_to_pud_val(phys) __phys_to_pte_val(phys) 39975387b92SKristina Martsenko #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT) 40075387b92SKristina Martsenko #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) 401af074848SSteve Capper 402ceb21835SWill Deacon #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) 403af074848SSteve Capper 40475387b92SKristina Martsenko #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd)) 40575387b92SKristina Martsenko #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys) 40675387b92SKristina Martsenko 407a501e324SCatalin Marinas #define __pgprot_modify(prot,mask,bits) \ 408a501e324SCatalin Marinas __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) 409a501e324SCatalin Marinas 410af074848SSteve Capper /* 4114f04d8f0SCatalin Marinas * Mark the prot value as uncacheable and unbufferable. 4124f04d8f0SCatalin Marinas */ 4134f04d8f0SCatalin Marinas #define pgprot_noncached(prot) \ 414de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) 4154f04d8f0SCatalin Marinas #define pgprot_writecombine(prot) \ 416de2db743SCatalin Marinas __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 417d1e6dc91SLiviu Dudau #define pgprot_device(prot) \ 418d1e6dc91SLiviu Dudau __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) 4193e4e1d3fSChristoph Hellwig /* 4203e4e1d3fSChristoph Hellwig * DMA allocations for non-coherent devices use what the Arm architecture calls 4213e4e1d3fSChristoph Hellwig * "Normal non-cacheable" memory, which permits speculation, unaligned accesses 4223e4e1d3fSChristoph Hellwig * and merging of writes. This is different from "Device-nGnR[nE]" memory which 4233e4e1d3fSChristoph Hellwig * is intended for MMIO and thus forbids speculation, preserves access size, 4243e4e1d3fSChristoph Hellwig * requires strict alignment and can also force write responses to come from the 4253e4e1d3fSChristoph Hellwig * endpoint. 4263e4e1d3fSChristoph Hellwig */ 427419e2f18SChristoph Hellwig #define pgprot_dmacoherent(prot) \ 428419e2f18SChristoph Hellwig __pgprot_modify(prot, PTE_ATTRINDX_MASK, \ 429419e2f18SChristoph Hellwig PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) 430419e2f18SChristoph Hellwig 4314f04d8f0SCatalin Marinas #define __HAVE_PHYS_MEM_ACCESS_PROT 4324f04d8f0SCatalin Marinas struct file; 4334f04d8f0SCatalin Marinas extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 4344f04d8f0SCatalin Marinas unsigned long size, pgprot_t vma_prot); 4354f04d8f0SCatalin Marinas 4364f04d8f0SCatalin Marinas #define pmd_none(pmd) (!pmd_val(pmd)) 4374f04d8f0SCatalin Marinas 438ab4db1f2SCatalin Marinas #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) 4394f04d8f0SCatalin Marinas 44036311607SMarc Zyngier #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 44136311607SMarc Zyngier PMD_TYPE_TABLE) 44236311607SMarc Zyngier #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 44336311607SMarc Zyngier PMD_TYPE_SECT) 4448aa82df3SSteven Price #define pmd_leaf(pmd) pmd_sect(pmd) 44536311607SMarc Zyngier 446cac4b8cdSCatalin Marinas #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 4477d4e2dcfSQian Cai static inline bool pud_sect(pud_t pud) { return false; } 4487d4e2dcfSQian Cai static inline bool pud_table(pud_t pud) { return true; } 449206a2a73SSteve Capper #else 450206a2a73SSteve Capper #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 451206a2a73SSteve Capper PUD_TYPE_SECT) 452523d6e9fSzhichang.yuan #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ 453523d6e9fSzhichang.yuan PUD_TYPE_TABLE) 454206a2a73SSteve Capper #endif 45536311607SMarc Zyngier 4562330b7caSJun Yao extern pgd_t init_pg_dir[PTRS_PER_PGD]; 4572330b7caSJun Yao extern pgd_t init_pg_end[]; 4582330b7caSJun Yao extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 4592330b7caSJun Yao extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; 4602330b7caSJun Yao extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; 4612330b7caSJun Yao 4622330b7caSJun Yao extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); 4632330b7caSJun Yao 4642330b7caSJun Yao static inline bool in_swapper_pgdir(void *addr) 4652330b7caSJun Yao { 4662330b7caSJun Yao return ((unsigned long)addr & PAGE_MASK) == 4672330b7caSJun Yao ((unsigned long)swapper_pg_dir & PAGE_MASK); 4682330b7caSJun Yao } 4692330b7caSJun Yao 4704f04d8f0SCatalin Marinas static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 4714f04d8f0SCatalin Marinas { 472e9ed821bSJames Morse #ifdef __PAGETABLE_PMD_FOLDED 473e9ed821bSJames Morse if (in_swapper_pgdir(pmdp)) { 4742330b7caSJun Yao set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd))); 4752330b7caSJun Yao return; 4762330b7caSJun Yao } 477e9ed821bSJames Morse #endif /* __PAGETABLE_PMD_FOLDED */ 4782330b7caSJun Yao 47920a004e7SWill Deacon WRITE_ONCE(*pmdp, pmd); 4800795edafSWill Deacon 481d0b7a302SWill Deacon if (pmd_valid(pmd)) { 48298f7685eSWill Deacon dsb(ishst); 483d0b7a302SWill Deacon isb(); 484d0b7a302SWill Deacon } 4854f04d8f0SCatalin Marinas } 4864f04d8f0SCatalin Marinas 4874f04d8f0SCatalin Marinas static inline void pmd_clear(pmd_t *pmdp) 4884f04d8f0SCatalin Marinas { 4894f04d8f0SCatalin Marinas set_pmd(pmdp, __pmd(0)); 4904f04d8f0SCatalin Marinas } 4914f04d8f0SCatalin Marinas 492dca56dcaSMark Rutland static inline phys_addr_t pmd_page_paddr(pmd_t pmd) 4934f04d8f0SCatalin Marinas { 49475387b92SKristina Martsenko return __pmd_to_phys(pmd); 4954f04d8f0SCatalin Marinas } 4964f04d8f0SCatalin Marinas 49774dd022fSQian Cai static inline void pte_unmap(pte_t *pte) { } 49874dd022fSQian Cai 499053520f7SMark Rutland /* Find an entry in the third-level page table. */ 500053520f7SMark Rutland #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 501053520f7SMark Rutland 502f069fabaSWill Deacon #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t)) 503dca56dcaSMark Rutland #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) 504053520f7SMark Rutland 505053520f7SMark Rutland #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 506053520f7SMark Rutland 507961faac1SMark Rutland #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) 508961faac1SMark Rutland #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) 509961faac1SMark Rutland #define pte_clear_fixmap() clear_fixmap(FIX_PTE) 510961faac1SMark Rutland 511*68ecabd0SGavin Shan #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd)) 5124f04d8f0SCatalin Marinas 5136533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5146533945aSArd Biesheuvel #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) 5156533945aSArd Biesheuvel 5164f04d8f0SCatalin Marinas /* 5174f04d8f0SCatalin Marinas * Conversion functions: convert a page and protection to a page entry, 5184f04d8f0SCatalin Marinas * and a page entry and page directory to the page they refer to. 5194f04d8f0SCatalin Marinas */ 5204f04d8f0SCatalin Marinas #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 5214f04d8f0SCatalin Marinas 5229f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 2 5234f04d8f0SCatalin Marinas 5247078db46SCatalin Marinas #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 5257078db46SCatalin Marinas 5264f04d8f0SCatalin Marinas #define pud_none(pud) (!pud_val(pud)) 527ab4db1f2SCatalin Marinas #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) 528f02ab08aSPunit Agrawal #define pud_present(pud) pte_present(pud_pte(pud)) 5298aa82df3SSteven Price #define pud_leaf(pud) pud_sect(pud) 5300795edafSWill Deacon #define pud_valid(pud) pte_valid(pud_pte(pud)) 5314f04d8f0SCatalin Marinas 5324f04d8f0SCatalin Marinas static inline void set_pud(pud_t *pudp, pud_t pud) 5334f04d8f0SCatalin Marinas { 534e9ed821bSJames Morse #ifdef __PAGETABLE_PUD_FOLDED 535e9ed821bSJames Morse if (in_swapper_pgdir(pudp)) { 5362330b7caSJun Yao set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud))); 5372330b7caSJun Yao return; 5382330b7caSJun Yao } 539e9ed821bSJames Morse #endif /* __PAGETABLE_PUD_FOLDED */ 5402330b7caSJun Yao 54120a004e7SWill Deacon WRITE_ONCE(*pudp, pud); 5420795edafSWill Deacon 543d0b7a302SWill Deacon if (pud_valid(pud)) { 54498f7685eSWill Deacon dsb(ishst); 545d0b7a302SWill Deacon isb(); 546d0b7a302SWill Deacon } 5474f04d8f0SCatalin Marinas } 5484f04d8f0SCatalin Marinas 5494f04d8f0SCatalin Marinas static inline void pud_clear(pud_t *pudp) 5504f04d8f0SCatalin Marinas { 5514f04d8f0SCatalin Marinas set_pud(pudp, __pud(0)); 5524f04d8f0SCatalin Marinas } 5534f04d8f0SCatalin Marinas 554dca56dcaSMark Rutland static inline phys_addr_t pud_page_paddr(pud_t pud) 5554f04d8f0SCatalin Marinas { 55675387b92SKristina Martsenko return __pud_to_phys(pud); 5574f04d8f0SCatalin Marinas } 5584f04d8f0SCatalin Marinas 5597078db46SCatalin Marinas /* Find an entry in the second-level page table. */ 5607078db46SCatalin Marinas #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 5617078db46SCatalin Marinas 56220a004e7SWill Deacon #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t)) 563dca56dcaSMark Rutland #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) 5647078db46SCatalin Marinas 565961faac1SMark Rutland #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) 566961faac1SMark Rutland #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) 567961faac1SMark Rutland #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) 5684f04d8f0SCatalin Marinas 569*68ecabd0SGavin Shan #define pud_page(pud) phys_to_page(__pud_to_phys(pud)) 57029e56940SSteve Capper 5716533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 5726533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) 5736533945aSArd Biesheuvel 574dca56dcaSMark Rutland #else 575dca56dcaSMark Rutland 576dca56dcaSMark Rutland #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) 577dca56dcaSMark Rutland 578961faac1SMark Rutland /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ 579961faac1SMark Rutland #define pmd_set_fixmap(addr) NULL 580961faac1SMark Rutland #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) 581961faac1SMark Rutland #define pmd_clear_fixmap() 582961faac1SMark Rutland 5836533945aSArd Biesheuvel #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) 5846533945aSArd Biesheuvel 5859f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 2 */ 5864f04d8f0SCatalin Marinas 5879f25e6adSKirill A. Shutemov #if CONFIG_PGTABLE_LEVELS > 3 588c79b954bSJungseok Lee 5897078db46SCatalin Marinas #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) 5907078db46SCatalin Marinas 591c79b954bSJungseok Lee #define pgd_none(pgd) (!pgd_val(pgd)) 592c79b954bSJungseok Lee #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) 593c79b954bSJungseok Lee #define pgd_present(pgd) (pgd_val(pgd)) 594c79b954bSJungseok Lee 595c79b954bSJungseok Lee static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) 596c79b954bSJungseok Lee { 5972330b7caSJun Yao if (in_swapper_pgdir(pgdp)) { 5982330b7caSJun Yao set_swapper_pgd(pgdp, pgd); 5992330b7caSJun Yao return; 6002330b7caSJun Yao } 6012330b7caSJun Yao 60220a004e7SWill Deacon WRITE_ONCE(*pgdp, pgd); 603c79b954bSJungseok Lee dsb(ishst); 604eb6a4dccSWill Deacon isb(); 605c79b954bSJungseok Lee } 606c79b954bSJungseok Lee 607c79b954bSJungseok Lee static inline void pgd_clear(pgd_t *pgdp) 608c79b954bSJungseok Lee { 609c79b954bSJungseok Lee set_pgd(pgdp, __pgd(0)); 610c79b954bSJungseok Lee } 611c79b954bSJungseok Lee 612dca56dcaSMark Rutland static inline phys_addr_t pgd_page_paddr(pgd_t pgd) 613c79b954bSJungseok Lee { 61475387b92SKristina Martsenko return __pgd_to_phys(pgd); 615c79b954bSJungseok Lee } 616c79b954bSJungseok Lee 6177078db46SCatalin Marinas /* Find an entry in the frst-level page table. */ 6187078db46SCatalin Marinas #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) 6197078db46SCatalin Marinas 62020a004e7SWill Deacon #define pud_offset_phys(dir, addr) (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t)) 621dca56dcaSMark Rutland #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) 6227078db46SCatalin Marinas 623961faac1SMark Rutland #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) 624961faac1SMark Rutland #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) 625961faac1SMark Rutland #define pud_clear_fixmap() clear_fixmap(FIX_PUD) 626c79b954bSJungseok Lee 627*68ecabd0SGavin Shan #define pgd_page(pgd) phys_to_page(__pgd_to_phys(pgd)) 6285d96e0cbSJungseok Lee 6296533945aSArd Biesheuvel /* use ONLY for statically allocated translation tables */ 6306533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) 6316533945aSArd Biesheuvel 632dca56dcaSMark Rutland #else 633dca56dcaSMark Rutland 634dca56dcaSMark Rutland #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) 635dca56dcaSMark Rutland 636961faac1SMark Rutland /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ 637961faac1SMark Rutland #define pud_set_fixmap(addr) NULL 638961faac1SMark Rutland #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) 639961faac1SMark Rutland #define pud_clear_fixmap() 640961faac1SMark Rutland 6416533945aSArd Biesheuvel #define pud_offset_kimg(dir,addr) ((pud_t *)dir) 6426533945aSArd Biesheuvel 6439f25e6adSKirill A. Shutemov #endif /* CONFIG_PGTABLE_LEVELS > 3 */ 644c79b954bSJungseok Lee 6457078db46SCatalin Marinas #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 6467078db46SCatalin Marinas 6474f04d8f0SCatalin Marinas /* to find an entry in a page-table-directory */ 6484f04d8f0SCatalin Marinas #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) 6494f04d8f0SCatalin Marinas 650dca56dcaSMark Rutland #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) 651dca56dcaSMark Rutland 652dca56dcaSMark Rutland #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) 6534f04d8f0SCatalin Marinas 6544f04d8f0SCatalin Marinas /* to find an entry in a kernel page-table-directory */ 6554f04d8f0SCatalin Marinas #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 6564f04d8f0SCatalin Marinas 657961faac1SMark Rutland #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) 658961faac1SMark Rutland #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) 659961faac1SMark Rutland 6604f04d8f0SCatalin Marinas static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 6614f04d8f0SCatalin Marinas { 662a6fadf7eSWill Deacon const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 6631a541b4eSSteve Capper PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 6642f4b829cSCatalin Marinas /* preserve the hardware dirty information */ 6652f4b829cSCatalin Marinas if (pte_hw_dirty(pte)) 66662d96c71SCatalin Marinas pte = pte_mkdirty(pte); 6674f04d8f0SCatalin Marinas pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 6684f04d8f0SCatalin Marinas return pte; 6694f04d8f0SCatalin Marinas } 6704f04d8f0SCatalin Marinas 6719c7e535fSSteve Capper static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 6729c7e535fSSteve Capper { 6739c7e535fSSteve Capper return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); 6749c7e535fSSteve Capper } 6759c7e535fSSteve Capper 67666dbd6e6SCatalin Marinas #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 67766dbd6e6SCatalin Marinas extern int ptep_set_access_flags(struct vm_area_struct *vma, 67866dbd6e6SCatalin Marinas unsigned long address, pte_t *ptep, 67966dbd6e6SCatalin Marinas pte_t entry, int dirty); 68066dbd6e6SCatalin Marinas 681282aa705SCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 682282aa705SCatalin Marinas #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 683282aa705SCatalin Marinas static inline int pmdp_set_access_flags(struct vm_area_struct *vma, 684282aa705SCatalin Marinas unsigned long address, pmd_t *pmdp, 685282aa705SCatalin Marinas pmd_t entry, int dirty) 686282aa705SCatalin Marinas { 687282aa705SCatalin Marinas return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); 688282aa705SCatalin Marinas } 68973b20c84SRobin Murphy 69073b20c84SRobin Murphy static inline int pud_devmap(pud_t pud) 69173b20c84SRobin Murphy { 69273b20c84SRobin Murphy return 0; 69373b20c84SRobin Murphy } 69473b20c84SRobin Murphy 69573b20c84SRobin Murphy static inline int pgd_devmap(pgd_t pgd) 69673b20c84SRobin Murphy { 69773b20c84SRobin Murphy return 0; 69873b20c84SRobin Murphy } 699282aa705SCatalin Marinas #endif 700282aa705SCatalin Marinas 7012f4b829cSCatalin Marinas /* 7022f4b829cSCatalin Marinas * Atomic pte/pmd modifications. 7032f4b829cSCatalin Marinas */ 7042f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 70506485053SCatalin Marinas static inline int __ptep_test_and_clear_young(pte_t *ptep) 7062f4b829cSCatalin Marinas { 7073bbf7157SCatalin Marinas pte_t old_pte, pte; 7082f4b829cSCatalin Marinas 7093bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7103bbf7157SCatalin Marinas do { 7113bbf7157SCatalin Marinas old_pte = pte; 7123bbf7157SCatalin Marinas pte = pte_mkold(pte); 7133bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7143bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7153bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7162f4b829cSCatalin Marinas 7173bbf7157SCatalin Marinas return pte_young(pte); 7182f4b829cSCatalin Marinas } 7192f4b829cSCatalin Marinas 72006485053SCatalin Marinas static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, 72106485053SCatalin Marinas unsigned long address, 72206485053SCatalin Marinas pte_t *ptep) 72306485053SCatalin Marinas { 72406485053SCatalin Marinas return __ptep_test_and_clear_young(ptep); 72506485053SCatalin Marinas } 72606485053SCatalin Marinas 7273403e56bSAlex Van Brunt #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 7283403e56bSAlex Van Brunt static inline int ptep_clear_flush_young(struct vm_area_struct *vma, 7293403e56bSAlex Van Brunt unsigned long address, pte_t *ptep) 7303403e56bSAlex Van Brunt { 7313403e56bSAlex Van Brunt int young = ptep_test_and_clear_young(vma, address, ptep); 7323403e56bSAlex Van Brunt 7333403e56bSAlex Van Brunt if (young) { 7343403e56bSAlex Van Brunt /* 7353403e56bSAlex Van Brunt * We can elide the trailing DSB here since the worst that can 7363403e56bSAlex Van Brunt * happen is that a CPU continues to use the young entry in its 7373403e56bSAlex Van Brunt * TLB and we mistakenly reclaim the associated page. The 7383403e56bSAlex Van Brunt * window for such an event is bounded by the next 7393403e56bSAlex Van Brunt * context-switch, which provides a DSB to complete the TLB 7403403e56bSAlex Van Brunt * invalidation. 7413403e56bSAlex Van Brunt */ 7423403e56bSAlex Van Brunt flush_tlb_page_nosync(vma, address); 7433403e56bSAlex Van Brunt } 7443403e56bSAlex Van Brunt 7453403e56bSAlex Van Brunt return young; 7463403e56bSAlex Van Brunt } 7473403e56bSAlex Van Brunt 7482f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7492f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 7502f4b829cSCatalin Marinas static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, 7512f4b829cSCatalin Marinas unsigned long address, 7522f4b829cSCatalin Marinas pmd_t *pmdp) 7532f4b829cSCatalin Marinas { 7542f4b829cSCatalin Marinas return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); 7552f4b829cSCatalin Marinas } 7562f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7572f4b829cSCatalin Marinas 7582f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 7592f4b829cSCatalin Marinas static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 7602f4b829cSCatalin Marinas unsigned long address, pte_t *ptep) 7612f4b829cSCatalin Marinas { 7623bbf7157SCatalin Marinas return __pte(xchg_relaxed(&pte_val(*ptep), 0)); 7632f4b829cSCatalin Marinas } 7642f4b829cSCatalin Marinas 7652f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 766911f56eeSCatalin Marinas #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 767911f56eeSCatalin Marinas static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 7682f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 7692f4b829cSCatalin Marinas { 7702f4b829cSCatalin Marinas return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); 7712f4b829cSCatalin Marinas } 7722f4b829cSCatalin Marinas #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 7732f4b829cSCatalin Marinas 7742f4b829cSCatalin Marinas /* 7758781bcbcSSteve Capper * ptep_set_wrprotect - mark read-only while trasferring potential hardware 7768781bcbcSSteve Capper * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. 7772f4b829cSCatalin Marinas */ 7782f4b829cSCatalin Marinas #define __HAVE_ARCH_PTEP_SET_WRPROTECT 7792f4b829cSCatalin Marinas static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) 7802f4b829cSCatalin Marinas { 7813bbf7157SCatalin Marinas pte_t old_pte, pte; 7822f4b829cSCatalin Marinas 7833bbf7157SCatalin Marinas pte = READ_ONCE(*ptep); 7843bbf7157SCatalin Marinas do { 7853bbf7157SCatalin Marinas old_pte = pte; 7868781bcbcSSteve Capper /* 7878781bcbcSSteve Capper * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY 7888781bcbcSSteve Capper * clear), set the PTE_DIRTY bit. 7898781bcbcSSteve Capper */ 7908781bcbcSSteve Capper if (pte_hw_dirty(pte)) 7918781bcbcSSteve Capper pte = pte_mkdirty(pte); 7923bbf7157SCatalin Marinas pte = pte_wrprotect(pte); 7933bbf7157SCatalin Marinas pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), 7943bbf7157SCatalin Marinas pte_val(old_pte), pte_val(pte)); 7953bbf7157SCatalin Marinas } while (pte_val(pte) != pte_val(old_pte)); 7962f4b829cSCatalin Marinas } 7972f4b829cSCatalin Marinas 7982f4b829cSCatalin Marinas #ifdef CONFIG_TRANSPARENT_HUGEPAGE 7992f4b829cSCatalin Marinas #define __HAVE_ARCH_PMDP_SET_WRPROTECT 8002f4b829cSCatalin Marinas static inline void pmdp_set_wrprotect(struct mm_struct *mm, 8012f4b829cSCatalin Marinas unsigned long address, pmd_t *pmdp) 8022f4b829cSCatalin Marinas { 8032f4b829cSCatalin Marinas ptep_set_wrprotect(mm, address, (pte_t *)pmdp); 8042f4b829cSCatalin Marinas } 8051d78a62cSCatalin Marinas 8061d78a62cSCatalin Marinas #define pmdp_establish pmdp_establish 8071d78a62cSCatalin Marinas static inline pmd_t pmdp_establish(struct vm_area_struct *vma, 8081d78a62cSCatalin Marinas unsigned long address, pmd_t *pmdp, pmd_t pmd) 8091d78a62cSCatalin Marinas { 8101d78a62cSCatalin Marinas return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd))); 8111d78a62cSCatalin Marinas } 8122f4b829cSCatalin Marinas #endif 8132f4b829cSCatalin Marinas 8144f04d8f0SCatalin Marinas /* 8154f04d8f0SCatalin Marinas * Encode and decode a swap entry: 8163676f9efSCatalin Marinas * bits 0-1: present (must be zero) 8179b3e661eSKirill A. Shutemov * bits 2-7: swap type 8189b3e661eSKirill A. Shutemov * bits 8-57: swap offset 819fdc69e7dSCatalin Marinas * bit 58: PTE_PROT_NONE (must be zero) 8204f04d8f0SCatalin Marinas */ 8219b3e661eSKirill A. Shutemov #define __SWP_TYPE_SHIFT 2 8224f04d8f0SCatalin Marinas #define __SWP_TYPE_BITS 6 8239b3e661eSKirill A. Shutemov #define __SWP_OFFSET_BITS 50 8244f04d8f0SCatalin Marinas #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 8254f04d8f0SCatalin Marinas #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 8263676f9efSCatalin Marinas #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) 8274f04d8f0SCatalin Marinas 8284f04d8f0SCatalin Marinas #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 8293676f9efSCatalin Marinas #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) 8304f04d8f0SCatalin Marinas #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 8314f04d8f0SCatalin Marinas 8324f04d8f0SCatalin Marinas #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 8334f04d8f0SCatalin Marinas #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 8344f04d8f0SCatalin Marinas 8354f04d8f0SCatalin Marinas /* 8364f04d8f0SCatalin Marinas * Ensure that there are not more swap files than can be encoded in the kernel 837aad9061bSGeert Uytterhoeven * PTEs. 8384f04d8f0SCatalin Marinas */ 8394f04d8f0SCatalin Marinas #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) 8404f04d8f0SCatalin Marinas 8414f04d8f0SCatalin Marinas extern int kern_addr_valid(unsigned long addr); 8424f04d8f0SCatalin Marinas 8434f04d8f0SCatalin Marinas #include <asm-generic/pgtable.h> 8444f04d8f0SCatalin Marinas 845cba3574fSWill Deacon /* 846cba3574fSWill Deacon * On AArch64, the cache coherency is handled via the set_pte_at() function. 847cba3574fSWill Deacon */ 848cba3574fSWill Deacon static inline void update_mmu_cache(struct vm_area_struct *vma, 849cba3574fSWill Deacon unsigned long addr, pte_t *ptep) 850cba3574fSWill Deacon { 851cba3574fSWill Deacon /* 852120798d2SWill Deacon * We don't do anything here, so there's a very small chance of 853120798d2SWill Deacon * us retaking a user fault which we just fixed up. The alternative 854120798d2SWill Deacon * is doing a dsb(ishst), but that penalises the fastpath. 855cba3574fSWill Deacon */ 856cba3574fSWill Deacon } 857cba3574fSWill Deacon 858cba3574fSWill Deacon #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) 859cba3574fSWill Deacon 860529c4b05SKristina Martsenko #ifdef CONFIG_ARM64_PA_BITS_52 861529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) 862529c4b05SKristina Martsenko #else 863529c4b05SKristina Martsenko #define phys_to_ttbr(addr) (addr) 864529c4b05SKristina Martsenko #endif 865529c4b05SKristina Martsenko 8666af31226SJia He /* 8676af31226SJia He * On arm64 without hardware Access Flag, copying from user will fail because 8686af31226SJia He * the pte is old and cannot be marked young. So we always end up with zeroed 8696af31226SJia He * page after fork() + CoW for pfn mappings. We don't always have a 8706af31226SJia He * hardware-managed access flag on arm64. 8716af31226SJia He */ 8726af31226SJia He static inline bool arch_faults_on_old_pte(void) 8736af31226SJia He { 8746af31226SJia He WARN_ON(preemptible()); 8756af31226SJia He 8766af31226SJia He return !cpu_has_hw_af(); 8776af31226SJia He } 8786af31226SJia He #define arch_faults_on_old_pte arch_faults_on_old_pte 8796af31226SJia He 8804f04d8f0SCatalin Marinas #endif /* !__ASSEMBLY__ */ 8814f04d8f0SCatalin Marinas 8824f04d8f0SCatalin Marinas #endif /* __ASM_PGTABLE_H */ 883